skgeinit.h

这是Marvell Technology Group Ltd. 4355 (rev 12)网卡在linux下的驱动程序源代码

/******************************************************************************
 *
 * Name:	skgeinit.h
 * Project:	Gigabit Ethernet Adapters, Common Modules
 * Version:	$Revision: 2.79 $
 * Date:	$Date: 2008/04/15 15:37:57 $
 * Purpose:	Structures and prototypes for the GE Init Module
 *
 ******************************************************************************/

/******************************************************************************
 *
 *	LICENSE:
 *	(C)Copyright Marvell.
 *	
 *	This program is free software; you can redistribute it and/or modify
 *	it under the terms of the GNU General Public License as published by
 *	the Free Software Foundation; either version 2 of the License, or
 *	(at your option) any later version.
 *	
 *	The information in this file is provided "AS IS" without warranty.
 *	/LICENSE
 *
 ******************************************************************************/

#ifndef __INC_SKGEINIT_H_
#define __INC_SKGEINIT_H_

#ifdef __cplusplus
extern "C" {
#endif	/* __cplusplus */

/* defines ********************************************************************/

#define SK_TEST_VAL		0x11335577UL

/* modifying Link LED behaviour (used with SkGeLinkLED()) */
#define SK_LNK_OFF		LED_OFF
#define SK_LNK_ON		(LED_ON | LED_BLK_OFF | LED_SYNC_OFF)
#define SK_LNK_BLINK	(LED_ON | LED_BLK_ON  | LED_SYNC_ON)
#define SK_LNK_PERM		(LED_ON | LED_BLK_OFF | LED_SYNC_ON)
#define SK_LNK_TST		(LED_ON | LED_BLK_ON  | LED_SYNC_OFF)

/* parameter 'Mode' when calling SK_HWAC_LINK_LED() */
#define SK_LED_OFF		LED_OFF
#define SK_LED_ACTIVE	(LED_ON | LED_BLK_OFF | LED_SYNC_OFF)
#define SK_LED_STANDBY	(LED_ON | LED_BLK_ON  | LED_SYNC_OFF)

/* addressing LED Registers in SkGeXmitLED() */
#define XMIT_LED_INI	0
#define XMIT_LED_CNT	(RX_LED_VAL - RX_LED_INI)
#define XMIT_LED_CTRL	(RX_LED_CTRL- RX_LED_INI)
#define XMIT_LED_TST	(RX_LED_TST - RX_LED_INI)

/* parameter 'Mode' when calling SkGeXmitLED() */
#define SK_LED_DIS	0
#define SK_LED_ENA	1
#define SK_LED_TST	2

/* Counter and Timer constants, for a host clock of 62.5 MHz */
#define SK_XMIT_DUR		0x002faf08UL	/*  50 ms */
#define SK_BLK_DUR		0x01dcd650UL	/* 500 ms */

#define SK_DPOLL_DEF	0x00ee6b28UL	/* 250 ms at 62.5 MHz (Genesis) */
#define SK_DPOLL_DEF_Y2	0x0000124fUL	/*  75 us (Yukon-2) */

#define SK_DPOLL_MAX	0x00ffffffUL	/* 268 ms at 62.5 MHz */
										/* 215 ms at 78.12 MHz (Yukon) */

#define SK_FACT_62		100			/* default 62.5 MHz --> 100 % */
#define SK_FACT_50		 80			/* on YUKON-FE+:  50 MHz */
#define SK_FACT_53		 85			/* on GENESIS:	53.12 MHz */
#define SK_FACT_78		125			/* on YUKON:	78.12 MHz */
#define SK_FACT_100		160			/* on YUKON-FE:	 100 MHz */
#define SK_FACT_125		200			/* on YUKON-EC:	 125 MHz */

/* Timeout values */
#define SK_MAC_TO_53	72			/* MAC arbiter timeout */
#define SK_PKT_TO_53	0x2000		/* Packet arbiter timeout */
#define SK_PKT_TO_MAX	0xffff		/* Maximum value */
#define SK_RI_TO_53		36			/* RAM interface timeout */

#define SK_PHY_ACC_TO	600000		/* PHY access timeout */

/* RAM Buffer High Pause Threshold values */
#define SK_RB_ULPP		( 8 * 1024)	/* Upper Level in kB/8 */
#define SK_RB_LLPP_S	(10 * 1024)	/* Lower Level for small Queues */
#define SK_RB_LLPP_B	(16 * 1024)	/* Lower Level for big Queues */

/* Threshold values for Yukon-EC Ultra and Extreme*/
#define SK_ECU_ULPP		0x0080	/* Upper Pause Threshold (multiples of 8) */
#define SK_DEV521_ULPP	0x00c4	/* Upper Pause Threshold for Dev. 5.21 */
#define SK_ECU_LLPP		0x0060	/* Lower Pause Threshold (multiples of 8) */
#define SK_ECU_AE_THR	0x0070	/* Almost Empty Threshold */
#define SK_ECU_TXFF_LEV	0x01a0	/* Tx BMU FIFO Level */
#define SK_ECU_JUMBO_WM	0x0400	/* Jumbo Mode Watermark */

#ifndef SK_BMU_RX_WM
#define SK_BMU_RX_WM		0x600	/* BMU Rx Watermark */
#endif

#ifndef SK_BMU_TX_WM
#define SK_BMU_TX_WM		0x600	/* BMU Tx Watermark */
#endif

/* performance sensitive drivers should set this define to 0x80 */
#ifndef SK_BMU_RX_WM_PEX
#define SK_BMU_RX_WM_PEX	0x80	/* BMU Rx Watermark for PEX */
#endif

/* XMAC II Rx High Watermark */
#define SK_XM_RX_HI_WM	0x05aa		/* 1450 */

/* XMAC II Tx Threshold */
#define SK_XM_THR_REDL	0x01fb		/* .. for redundant link usage */
#define SK_XM_THR_SL	0x01fb		/* .. for single link adapters */
#define SK_XM_THR_MULL	0x01fb		/* .. for multiple link usage */
#define SK_XM_THR_JUMBO	0x03fc		/* .. for jumbo frame usage */

/* values for PortUsage */
#define SK_RED_LINK		1		/* redundant link usage */
#define SK_MUL_LINK		2		/* multiple link usage */
#define SK_JUMBO_LINK	3		/* driver uses jumbo frames */

/* Minimum RAM Buffer Rx Queue Size */
#define SK_MIN_RXQ_SIZE	(((pAC)->GIni.GIYukon2) ? 10 : 16)		/* 10/16 kB */

/* Minimum RAM Buffer Tx Queue Size */
#define SK_MIN_TXQ_SIZE	(((pAC)->GIni.GIYukon2) ? 10 : 16)		/* 10/16 kB */

/* Queue Size units (Genesis/Yukon) */
#define QZ_UNITS		7
#define QZ_STEP			8

/* Queue Size units (Yukon-2) */
#define QZ_STEP_Y2		1

/* Percentage of queue size from whole memory */
/* 80 % for receive */
#define RAM_QUOTA_RX	80
/*  0 % for sync transfer */
#define RAM_QUOTA_SYNC	0
/* the rest (20%) is taken for async transfer */

/* Types of RAM Buffer Queues */
#define SK_RX_SRAM_Q	1	/* small receive queue */
#define SK_RX_BRAM_Q	2	/* big receive queue */
#define SK_TX_RAM_Q		3	/* small or big transmit queue */

/* parameter 'Dir' when calling SkGeStopPort() */
#define SK_STOP_TX	1	/* Stops the transmit path, resets the XMAC */
#define SK_STOP_RX	2	/* Stops the receive path */
#define SK_STOP_ALL	3	/* Stops Rx and Tx path, resets the XMAC */

/* parameter 'RstMode' when calling SkGeStopPort() */
#define SK_SOFT_RST	1	/* perform a software reset */
#define SK_HARD_RST	2	/* perform a hardware reset */

/* Init Levels */
#define SK_INIT_DATA	0	/* Init level 0: init data structures */
#define SK_INIT_IO		1	/* Init level 1: init with IOs */
#define SK_INIT_RUN		2	/* Init level 2: init for run time */

/* Link Mode Parameter */
#define SK_LMODE_HALF		1	/* Half Duplex Mode */
#define SK_LMODE_FULL		2	/* Full Duplex Mode */
#define SK_LMODE_AUTOHALF	3	/* AutoHalf Duplex Mode */
#define SK_LMODE_AUTOFULL	4	/* AutoFull Duplex Mode */
#define SK_LMODE_AUTOBOTH	5	/* AutoBoth Duplex Mode */
#define SK_LMODE_AUTOSENSE	6	/* configured mode auto sensing */
#define SK_LMODE_INDETERMINATED	7	/* indeterminated */

/* Auto-negotiation timeout in 100ms granularity */
#define SK_AND_MAX_TO		6	/* Wait 600 msec before link comes up */

/* Auto-negotiation error codes */
#define SK_AND_OK			0	/* no error */
#define SK_AND_OTHER		1	/* other error than below */
#define SK_AND_DUP_CAP		2	/* Duplex capabilities error */

/* Link Speed Capabilities */
#define SK_LSPEED_CAP_AUTO			BIT_0S	/* Automatic resolution */
#define SK_LSPEED_CAP_10MBPS		BIT_1S	/* 10 Mbps */
#define SK_LSPEED_CAP_100MBPS		BIT_2S	/* 100 Mbps */
#define SK_LSPEED_CAP_1000MBPS		BIT_3S	/* 1000 Mbps */
#define SK_LSPEED_CAP_INDETERMINATED BIT_4S /* indeterminated */

/* Link Speed Parameter */
#define SK_LSPEED_AUTO				1	/* Automatic resolution */
#define SK_LSPEED_10MBPS			2	/* 10 Mbps */
#define SK_LSPEED_100MBPS			3	/* 100 Mbps */
#define SK_LSPEED_1000MBPS			4	/* 1000 Mbps */
#define SK_LSPEED_INDETERMINATED	5	/* indeterminated */

/* Link Speed Current State */
#define SK_LSPEED_STAT_UNKNOWN		1
#define SK_LSPEED_STAT_10MBPS		2
#define SK_LSPEED_STAT_100MBPS		3
#define SK_LSPEED_STAT_1000MBPS		4
#define SK_LSPEED_STAT_INDETERMINATED 5

/* Link Capability Parameter */
#define SK_LMODE_CAP_HALF		BIT_0S	/* Half Duplex Mode */
#define SK_LMODE_CAP_FULL		BIT_1S	/* Full Duplex Mode */
#define SK_LMODE_CAP_AUTOHALF	BIT_2S	/* AutoHalf Duplex Mode */
#define SK_LMODE_CAP_AUTOFULL	BIT_3S	/* AutoFull Duplex Mode */
#define SK_LMODE_CAP_INDETERMINATED BIT_4S /* indeterminated */

/* Link Mode Current State */
#define SK_LMODE_STAT_UNKNOWN	1	/* Unknown Duplex Mode */
#define SK_LMODE_STAT_HALF		2	/* Half Duplex Mode */
#define SK_LMODE_STAT_FULL		3	/* Full Duplex Mode */
#define SK_LMODE_STAT_AUTOHALF	4	/* Half Duplex Mode obtained by Auto-Neg */
#define SK_LMODE_STAT_AUTOFULL	5	/* Full Duplex Mode obtained by Auto-Neg */
#define SK_LMODE_STAT_INDETERMINATED 6	/* indeterminated */

/* Flow Control Mode Parameter (and capabilities) */
#define SK_FLOW_MODE_NONE		1	/* No Flow Control */
#define SK_FLOW_MODE_LOC_SEND	2	/* Local station sends PAUSE */
#define SK_FLOW_MODE_SYMMETRIC	3	/* Both stations may send PAUSE */
#define SK_FLOW_MODE_SYM_OR_REM	4	/* Both stations may send PAUSE or
					 * just the remote station may send PAUSE
					 */
#define SK_FLOW_MODE_INDETERMINATED 5	/* indeterminated */

/* Flow Control Status Parameter */
#define SK_FLOW_STAT_NONE		1	/* No Flow Control */
#define SK_FLOW_STAT_REM_SEND	2	/* Remote Station sends PAUSE */
#define SK_FLOW_STAT_LOC_SEND	3	/* Local station sends PAUSE */
#define SK_FLOW_STAT_SYMMETRIC	4	/* Both station may send PAUSE */
#define SK_FLOW_STAT_INDETERMINATED 5	/* indeterminated */

/* Master/Slave Mode Capabilities */
#define SK_MS_CAP_AUTO		BIT_0S	/* Automatic resolution */
#define SK_MS_CAP_MASTER	BIT_1S	/* This station is master */
#define SK_MS_CAP_SLAVE		BIT_2S	/* This station is slave */
#define SK_MS_CAP_INDETERMINATED BIT_3S	/* indeterminated */

/* Set Master/Slave Mode Parameter (and capabilities) */
#define SK_MS_MODE_AUTO		1	/* Automatic resolution */
#define SK_MS_MODE_MASTER	2	/* This station is master */
#define SK_MS_MODE_SLAVE	3	/* This station is slave */
#define SK_MS_MODE_INDETERMINATED 4	/* indeterminated */

/* Master/Slave Status Parameter */
#define SK_MS_STAT_UNSET	1	/* The M/S status is not set */
#define SK_MS_STAT_MASTER	2	/* This station is master */
#define SK_MS_STAT_SLAVE	3	/* This station is slave */
#define SK_MS_STAT_FAULT	4	/* M/S resolution failed */
#define SK_MS_STAT_INDETERMINATED 5	/* indeterminated */

/* parameter 'Mode' when calling SkMacSetRxCmd() */
#define SK_STRIP_FCS_ON		BIT_0S	/* Enable  FCS stripping of Rx frames */
#define SK_STRIP_FCS_OFF	BIT_1S	/* Disable FCS stripping of Rx frames */
#define SK_STRIP_PAD_ON		BIT_2S	/* Enable  pad byte stripping of Rx fr */
#define SK_STRIP_PAD_OFF	BIT_3S	/* Disable pad byte stripping of Rx fr */
#define SK_LENERR_OK_ON		BIT_4S	/* Don't chk fr for in range len error */
#define SK_LENERR_OK_OFF	BIT_5S	/* Check frames for in range len error */
#define SK_BIG_PK_OK_ON		BIT_6S	/* Don't set Rx Error bit for big frames */
#define SK_BIG_PK_OK_OFF	BIT_7S	/* Set Rx Error bit for big frames */
#define SK_SELF_RX_ON		BIT_8S	/* Enable  Rx of own packets */
#define SK_SELF_RX_OFF		BIT_9S	/* Disable Rx of own packets */

/* parameter 'Para' when calling SkMacSetRxTxEn() */
#define SK_MAC_LOOPB_ON		BIT_0S	/* Enable  MAC Loopback Mode */
#define SK_MAC_LOOPB_OFF	BIT_1S	/* Disable MAC Loopback Mode */
#define SK_PHY_LOOPB_ON		BIT_2S	/* Enable  PHY Loopback Mode */
#define SK_PHY_LOOPB_OFF	BIT_3S	/* Disable PHY Loopback Mode */
#define SK_PHY_FULLD_ON		BIT_4S	/* Enable  GMII Full Duplex */
#define SK_PHY_FULLD_OFF	BIT_5S	/* Disable GMII Full Duplex */

/* States of PState */
#define SK_PRT_RESET	0	/* the port is reset */
#define SK_PRT_STOP		1	/* the port is stopped (similar to SW reset) */
#define SK_PRT_INIT		2	/* the port is initialized */
#define SK_PRT_RUN		3	/* the port has an active link */

/* PHY power down modes */
#define PHY_PM_OPERATIONAL_MODE		0	/* PHY operational mode */
#define PHY_PM_DEEP_SLEEP			1	/* Coma mode --> minimal power */
#define PHY_PM_IEEE_POWER_DOWN		2	/* IEEE 22.2.4.1.5 compl. power down */
#define PHY_PM_ENERGY_DETECT		3	/* Energy detect */
#define PHY_PM_ENERGY_DETECT_PLUS	4	/* Energy detect plus */
#define PHY_PM_POWER_STATE_MANAGER	5	/* Power State Manager (PSM) */

/* PCI Bus Types */
#define SK_PCI_BUS		BIT_0S		/* normal PCI bus */
#define SK_PCIX_BUS		BIT_1S		/* PCI-X bus */
#define SK_PEX_BUS		BIT_2S		/* PCI-Express bus */

/* Default receive frame limit for Workaround of XMAC Errata */
#define SK_DEF_RX_WA_LIM	SK_CONSTU64(100)

/* values for GILedBlinkCtrl (LED Blink Control) */
#define SK_ACT_LED_BLINK	BIT_0S	/* Activity LED blinking */
#define SK_DUP_LED_NORMAL	BIT_1S	/* Duplex LED normal */
#define SK_LED_LINK100_ON	BIT_2S	/* Link 100M LED on */
#define SK_DUAL_LED_ACT_LNK	BIT_3S	/* Dual LED ACT/LNK configuration */
#define SK_LED_LINK_MUX_P60	BIT_4S	/* Link LED muxed to pin 60 */
#define SK_LED_COMB_ACT_LNK	BIT_5S	/* Combined ACT/LNK LED mode */
#define SK_ACT_LED_NOTR_OFF	BIT_6S	/* Activity LED off (no traffic) */

/* Link Partner Status */
#define SK_LIPA_UNKNOWN	0	/* Link partner is in unknown state */
#define SK_LIPA_MANUAL	1	/* Link partner is in detected manual state */
#define SK_LIPA_AUTO	2	/* Link partner is in auto-negotiation state */

/* Maximum Restarts before restart is ignored (3Com WA) */
#define SK_MAX_LRESTART	3	/* Max. 3 times the link is restarted */

/* Max. Auto-neg. timeouts before link detection in sense mode is reset */
#define SK_MAX_ANEG_TO	10	/* Max. 10 times the sense mode is reset */


/******************************************************************************
 *
 * HW_FEATURE() macro
 */

/* DWORD 0: Features */
#define HWF_ENA_POW_SAV_W_WOL	0x08000000UL	/* Power saving with WOL ena. */
#define HWF_FORCE_AUTO_NEG		0x04000000UL	/* Force Auto-Negotiation */
#define HWF_CLK_GATING_ENABLE	0x02000000UL	/* Enable Clock Gating */
#define HWF_RED_CORE_CLK_SUP	0x01000000UL	/* Reduced Core Clock supp. */
#define HWF_RESTORE_LOST_BARS	0x00800000UL	/* Save and restore PCI BARs */
#define HWF_ASPM_SWITCHING		0x00400000UL	/* Activate ASPM feature */
#define HWF_TX_IP_ID_INCR_ON	0x00200000UL	/* Enable Tx IP ID Increment */
#define HWF_ADV_CSUM_SUPPORT	0x00100000UL	/* Sel Csum of IP and TCP/UDP */
#define HWF_PSM_SUPPORTED		0x00080000UL	/* Power State Manager support*/
#define HWF_NEW_FLOW_CONTROL	0x00040000UL	/* New Flow-Control support*/
#define HWF_HW_WOL_ENABLE		0x00020000UL	/* Enable HW WOL */


/*-RMV- DWORD 1: Deviations (all in use) */
#define HWF_WA_DEV_4222			0x18000000UL	/*-RMV- 4.222 (Done Idx rep.) */
#define HWF_WA_DEV_56			0x14000000UL	/*-RMV- 5.6 (Rx Chksum 0xffff)*/
#define HWF_WA_DEV_54			0x12000000UL	/*-RMV- 5.4 (Missing Status LE)*/
#define HWF_WA_DEV_53			0x11000000UL	/*-RMV- 5.3 (Tx Done LSOv2 rep)*/
#define HWF_WA_DEV_LIM_IPV6_RSS	0x10800000UL	/*-RMV- IPV6 RSS limitted */
#define HWF_WA_DEV_4217			0x10400000UL	/*-RMV- 4.217 (PCI-E blockage) */
#define HWF_WA_DEV_4200			0x10200000UL	/*-RMV- 4.200 (D3 Blue Screen)*/
#define HWF_WA_DEV_4185CS		0x10100000UL	/*-RMV- 4.185 (ECU 100 CS cal)*/
#define HWF_WA_DEV_4185			0x10080000UL	/*-RMV- 4.185 (ECU Tx h check)*/
#define HWF_WA_DEV_4167			0x10040000UL	/*-RMV- 4.167 (Rx OvSize Hang)*/
#define HWF_WA_DEV_4152			0x10020000UL	/*-RMV- 4.152 (RSS issue) */
#define HWF_WA_DEV_4115			0x10010000UL	/*-RMV- 4.115 (Rx MAC FIFO) */
#define HWF_WA_DEV_4109			0x10008000UL	/*-RMV- 4.109 (BIU hang) */
#define HWF_WA_DEV_483			0x10004000UL	/*-RMV- 4.83 (Rx TCP wrong) */
#define HWF_WA_DEV_479			0x10002000UL	/*-RMV- 4.79 (Rx BMU hang II) */
#define HWF_WA_DEV_472			0x10001000UL	/*-RMV- 4.72 (GPHY2 MDC clk) */
#define HWF_WA_DEV_463			0x10000800UL	/*-RMV- 4.63 (Rx BMU hang I) */
#define HWF_WA_DEV_427			0x10000400UL	/*-RMV- 4.27 (Tx Done Rep) */
#define HWF_WA_DEV_42			0x10000200UL	/*-RMV- 4.2 (pref unit burst) */
#define HWF_WA_DEV_46			0x10000100UL	/*-RMV- 4.6 (CPU crash II) */
#define HWF_WA_DEV_43_418		0x10000080UL	/*-RMV- 4.3 & 4.18 (PCI unexp */
												/*-RMV- compl&Stat BMU deadl) */
#define HWF_WA_DEV_420			0x10000040UL	/*-RMV- 4.20 (Status BMU ov) */
#define HWF_WA_DEV_423			0x10000020UL	/*-RMV- 4.23 (TCP Segm Hang) */
#define HWF_WA_DEV_424			0x10000010UL	/*-RMV- 4.24 (MAC reg overwr) */
#define HWF_WA_DEV_425			0x10000008UL	/*-RMV- 4.25 (Magic packet */
												/*-RMV- with odd offset) */
#define HWF_WA_DEV_428			0x10000004UL	/*-RMV- 4.28 (Poll-U &BigEndi)*/
#define HWF_WA_FIFO_FLUSH_YLA0	0x10000002UL	/*-RMV- dis Rx GMAC FIFO Flush*/
												/*-RMV- for Yu-L Rev. A0 only */
#define HWF_WA_COMA_MODE		0x10000001UL	/*-RMV- Coma Mode WA req */

/*-RMV- DWORD 2: Deviations */
#define HWF_WA_DEV_548			0x20000800UL	/*-RMV- 5.48 (IPv4 Header CS) */
#define HWF_WA_DEV_4216			0x20000400UL	/*-RMV- 4.216 (fragm. IPV4+RSS)*/
#define HWF_WA_DEV_519			0x20000200UL	/*-RMV- 5.19 (MACsec: unexp. LE)*/
#define HWF_WA_DEV_517			0x20000100UL	/*-RMV- 5.17 (MACsec+FlowThrough)*/
#define HWF_WA_DEV_515			0x20000080UL	/*-RMV- 5.15 (MACsec TX underr)*/
#define HWF_WA_DEV_542			0x20000040UL	/*-RMV- 5.42 (CPU CLK + Flash) */
#define HWF_WA_DEV_4229			0x20000020UL	/*-RMV- 4.229 (RSS + VLAN) */
#define HWF_WA_DEV_521			0x20000010UL	/*-RMV- 5.21 (wrong RFSW) */
#define HWF_WA_DEV_520			0x20000008UL	/*-RMV- 5.20 (Tx lost of data)*/
#define HWF_WA_DEV_511			0x20000004UL	/*-RMV- 5.11 (Tx Underrun) */
#define HWF_WA_DEV_510			0x20000002UL	/*-RMV- 5.10 (Tx Checksum) */
#define HWF_WA_DEV_51			0x20000001UL	/*-RMV- 5.1 (MACSec sync) */

#if 0
#define HWF_SYNC_TX_SUP			0x20800000UL	/* Synch. Tx Queue available */
#define HWF_SINGLE_PORT_DEVICE	0x20400000UL	/* Device has only one LAN IF */
#define HWF_JUMBO_FRAMES_SUP	0x20200000UL	/* Jumbo Frames supported */