skgehw.h

这是Marvell Technology Group Ltd. 4355 (rev 12)网卡在linux下的驱动程序源代码

/*	Possible values: 0, 2, 4, 8, 16, 32, 64, 128 */

/*	PCI_HEADER_T	8 bit	Header Type */
#define PCI_HD_MF_DEV	BIT_7S	/* 0= single, 1= multi-func dev */
#define PCI_HD_TYPE		0x7f	/* Bit 6..0:	Header Layout (0=normal) */

/*	PCI_BIST	8 bit	Built-in selftest */
/*	Built-in Self test not supported (optional) */

/*	PCI_BASE_1ST	32 bit	1st Base address */
#define PCI_MEMSIZE		0x4000L		/* use 16 kB Memory Base */
#define PCI_MEMBASE_MSK 0xffffc000L	/* Bit 31..14:	Memory Base Address */
#define PCI_MEMSIZE_MSK 0x00003ff0L	/* Bit 13.. 4:	Memory Size Req. */
#define PCI_PREFEN		BIT_3		/* Prefetch enable */
#define PCI_MEM_TYP_MSK	(3L<<1)		/* Bit	2.. 1:	Memory Type Mask */
#define PCI_MEMSPACE	BIT_0		/* Memory Space Indicator */

#define PCI_MEM32BIT	(0L<<1)		/* Base addr anywhere in 32 Bit range */
#define PCI_MEM1M		(1L<<1)		/* Base addr below 1 MegaByte */
#define PCI_MEM64BIT	(2L<<1)		/* Base addr anywhere in 64 Bit range */

/*	PCI_BASE_2ND	32 bit	2nd Base address */
#define PCI_IOBASE		0xffffff00L	/* Bit 31.. 8:	I/O Base address */
#define PCI_IOSIZE		0x000000fcL	/* Bit	7.. 2:	I/O Size Requirements */
								/* Bit	1:	reserved */
#define PCI_IOSPACE		BIT_0		/* I/O Space Indicator */

/*	PCI_BASE_ROM	32 bit	Expansion ROM Base Address */
#define PCI_ROMBASE_MSK	0xfffe0000L	/* Bit 31..17:	ROM Base address */
#define PCI_ROMBASE_SIZ	(0x1cL<<14)	/* Bit 16..14:	Treat as Base or Size */
#define PCI_ROMSIZE		(0x38L<<11)	/* Bit 13..11:	ROM Size Requirements */
								/* Bit 10.. 1:	reserved */
#define PCI_ROMEN		BIT_0		/* Address Decode enable */

/* Device Dependent Region */
/*	PCI_OUR_REG_1		32 bit	Our Register 1 */
								/* Bit 31..29:	reserved */
#define PCI_PHY_COMA	BIT_28		/* Set PHY to Coma Mode (YUKON only) */
#define PCI_TEST_CAL	BIT_27		/* Test PCI buffer calib. (YUKON only) */
#define PCI_EN_CAL		BIT_26		/* Enable PCI buffer calib. (YUKON only) */
#define PCI_VIO			BIT_25		/* PCI I/O Voltage, 0 = 3.3V, 1 = 5V */
/* Yukon-2 */
#define PCI_Y2_PIG_ENA		BIT_31	/* Enable Plug-in-Go (YUKON-2) */
#define PCI_Y2_DLL_DIS		BIT_30	/* Disable PCI DLL (YUKON-2) */
#define PCI_SW_PWR_ON_RST	BIT_30	/* SW Power-on-reset (Yukon-Ext only) */
#define PCI_Y2_PHY2_COMA	BIT_29	/* Set PHY 2 to Coma Mode (YUKON-2) */
#define PCI_Y2_PHY1_COMA	BIT_28	/* Set PHY 1 to Coma Mode (YUKON-2) */
#define PCI_Y2_PHY2_POWD	BIT_27	/* Set PHY 2 to Power Down (YUKON-2) */
#define PCI_Y2_PHY1_POWD	BIT_26	/* Set PHY 1 to Power Down (YUKON-2) */
								/* Bit 25:	reserved */
#define PCI_DIS_BOOT	BIT_24		/* Disable BOOT via ROM */
#define PCI_EN_IO		BIT_23		/* Mapping to I/O space */
#define PCI_EN_FPROM	BIT_22		/* Enable FLASH mapping to memory */
									/*		1 = Map Flash to memory */
									/*		0 = Disable addr. dec */
#define PCI_PAGESIZE	(3L<<20)	/* Bit 21..20:	FLASH Page Size */
#define PCI_PAGE_16		(0L<<20)	/*		 16 k pages */
#define PCI_PAGE_32K	(1L<<20)	/*		 32 k pages */
#define PCI_PAGE_64K	(2L<<20)	/*		 64 k pages */
#define PCI_PAGE_128K	(3L<<20)	/*		128 k pages */
								/* Bit 19:	reserved */
#define PCI_PAGEREG		(7L<<16)	/* Bit 18..16:	Page Register */
#define PCI_NOTAR		BIT_15		/* No turnaround cycle */
#define PCI_PEX_LEGNAT	BIT_15		/* PEX PM legacy/native mode (YUKON-2) */
#define PCI_FORCE_BE	BIT_14		/* Assert all BEs on MR */
#define PCI_DIS_MRL		BIT_13		/* Disable Mem Read Line */
#define PCI_DIS_MRM		BIT_12		/* Disable Mem Read Multiple */
#define PCI_DIS_MWI		BIT_11		/* Disable Mem Write & Invalidate */
#define PCI_DISC_CLS	BIT_10		/* Disc: cacheLsz bound */
#define PCI_BURST_DIS	BIT_9		/* Burst Disable */
#define PCI_DIS_PCI_CLK	BIT_8		/* Disable PCI clock driving */
#define PCI_SKEW_DAS	(0xfL<<4)	/* Bit	7.. 4:	Skew Ctrl, DAS Ext */
#define PCI_SKEW_BASE	0xfL		/* Bit	3.. 0:	Skew Ctrl, Base */
#define PCI_CLS_OPT		BIT_3		/* Cache Line Size opt. PCI-X (YUKON-2) */

/* Yukon-EC Ultra only */
								/* Bit 14..10:	reserved */
#define PCI_PHY_LNK_TIM_MSK	(3L<<8)	/* Bit  9.. 8:	GPHY Link Trigger Timer */
#define PCI_ENA_L1_EVENT	BIT_7	/* Enable PEX L1 Event */
#define PCI_ENA_GPHY_LNK	BIT_6	/* Enable PEX L1 on GPHY Link down */
#define PCI_FORCE_PEX_L1	BIT_5	/* Force to PEX L1 */
								/* Bit  4.. 0:	reserved */

/*	PCI_OUR_REG_2		32 bit	Our Register 2 */
#define PCI_VPD_WR_THR	(0xffL<<24)	/* Bit 31..24:	VPD Write Threshold */
#define PCI_DEV_SEL		(0x7fL<<17)	/* Bit 23..17:	EEPROM Device Select */
#define PCI_VPD_ROM_SZ	(7L<<14)	/* Bit 16..14:	VPD ROM Size */
								/* Bit 13..12:	reserved */
#define PCI_PATCH_DIR	(0xfL<<8)	/* Bit 11.. 8:	Ext Patches dir 3..0 */
#define PCI_PATCH_DIR_3	BIT_11
#define PCI_PATCH_DIR_2	BIT_10
#define PCI_PATCH_DIR_1	BIT_9
#define PCI_PATCH_DIR_0	BIT_8
#define PCI_EXT_PATCHS	(0xfL<<4)	/* Bit	7.. 4:	Extended Patches 3..0 */
#define PCI_EXT_PATCH_3	BIT_7
#define PCI_EXT_PATCH_2	BIT_6
#define PCI_EXT_PATCH_1	BIT_5
#define PCI_EXT_PATCH_0	BIT_4
#define PCI_EN_DUMMY_RD	BIT_3		/* Enable Dummy Read */
#define PCI_REV_DESC	BIT_2		/* Reverse Descriptor Bytes */
								/* Bit	1:	reserved */
#define PCI_USEDATA64	BIT_0		/* Use 64Bit Data bus ext */

/* Power Management (PM) Region */
/*	PCI_PM_CAP_REG		16 bit	Power Management Capabilities */
#define PCI_PME_SUP_MSK	(0x1f<<11)	/* Bit 15..11:	PM Event (PME) Supp. Mask */
#define PCI_PME_D3C_SUP	BIT_15S		/* PME from D3cold Support (if VAUX) */
#define PCI_PME_D3H_SUP	BIT_14S		/* PME from D3hot Support */
#define PCI_PME_D2_SUP	BIT_13S		/* PME from D2 Support */
#define PCI_PME_D1_SUP	BIT_12S		/* PME from D1 Support */
#define PCI_PME_D0_SUP	BIT_11S		/* PME from D0 Support */
#define PCI_PM_D2_SUP	BIT_10S		/* D2 Support in 33 MHz mode */
#define PCI_PM_D1_SUP	BIT_9S		/* D1 Support */
								/* Bit	8.. 6:	reserved */
#define PCI_PM_DSI		BIT_5S		/* Device Specific Initialization */
#define PCI_PM_APS		BIT_4S		/* Auxialiary Power Source */
#define PCI_PME_CLOCK	BIT_3S		/* PM Event Clock */
#define PCI_PM_VER_MSK		7		/* Bit	2.. 0:	PM PCI Spec. version */

/*	PCI_PM_CTL_STS		16 bit	Power Management Control/Status */
#define PCI_PME_STATUS	BIT_15S		/* PME Status (YUKON only) */
#define PCI_PM_DAT_SCL	(3<<13)		/* Bit 14..13:	Data Reg. scaling factor */
#define PCI_PM_DAT_SEL	(0xf<<9)	/* Bit 12.. 9:	PM data selector field */
#define PCI_PME_EN		BIT_8S		/* Enable PME# generation (YUKON only) */
								/* Bit	7.. 2:	reserved */
#define PCI_PM_STATE_MSK	3		/* Bit	1.. 0:	Power Management State */

#define PCI_PM_STATE_D0		0		/* D0:	Operational (default) */
#define PCI_PM_STATE_D1		1		/* D1:	(YUKON only) */
#define PCI_PM_STATE_D2		2		/* D2:	(YUKON only) */
#define PCI_PM_STATE_D3		3		/* D3:	HOT, Power Down and Reset */

/* VPD Region */
/*	PCI_VPD_ADR_REG		16 bit	VPD Address Register */
#define PCI_VPD_FLAG	BIT_15S		/* starts VPD rd/wr cycle */
#define PCI_VPD_ADR_MSK	0x7fff		/* Bit 14.. 0:	VPD Address Mask */

/* Serial EEPROM Loader Control Register */
/*	PCI_SER_LD_CTRL			16 bit		Serial EEPROM Loader Control Register */
#define	PCI_SER_LD_FLAG	BIT_15S		/* Bit 15		starts EEPROM cfg loader */
#define PCI_SER_LD_ADDR	0x3fff		/* Bit  0..14	config loader start addr */

/*	PCI_OUR_STATUS		32 bit	Adapter Status Register (Yukon-2) */
#define PCI_OS_PCI64B	BIT_31		/* Conventional PCI 64 bits Bus */
#define PCI_OS_PCIX		BIT_30		/* PCI-X Bus */
#define PCI_OS_MODE_MSK	(3L<<28)	/* Bit 29..28:	PCI-X Bus Mode Mask */
#define PCI_OS_PCI66M	BIT_27		/* PCI 66 MHz Bus */
#define PCI_OS_PCI_X	BIT_26		/* PCI/PCI-X Bus (0 = PEX) */
#define PCI_OS_DLLE_MSK	(3L<<24)	/* Bit 25..24:	DLL Status Indication */
#define PCI_OS_DLLR_MSK	(0xfL<<20)	/* Bit 23..20:	DLL Row Counters Values */
#define PCI_OS_DLLC_MSK	(0xfL<<16)	/* Bit 19..16:	DLL Col. Counters Values */
								/* Bit 15.. 8:	reserved */

#define PCI_OS_SPEED(val)	((val & PCI_OS_MODE_MSK) >> 28)	/* PCI-X Speed */
/* possible values for the speed field of the register */
#define PCI_OS_SPD_PCI		0		/* PCI Conventional Bus */
#define PCI_OS_SPD_X66		1		/* PCI-X 66MHz Bus */
#define PCI_OS_SPD_X100		2		/* PCI-X 100MHz Bus */
#define PCI_OS_SPD_X133		3		/* PCI-X 133MHz Bus */

/*	PCI_OUR_REG_3		32 bit	Our Register 3 (Yukon-ECU only) */
								/* Bit 31..18:	reserved */
#define P_CLK_ASF_REGS_DIS		BIT_18	/* Disable Clock ASF (Yukon-Ext only) */
#define P_CLK_COR_REGS_D0_DIS	BIT_17	/* Disable Clock Core Regs D0 */
#define P_CLK_PCI_REGS_D0_DIS	BIT_16	/* Disable Clock PCI  Regs D0 */
#define P_CLK_COR_YTB_ARB_DIS	BIT_15	/* Disable Clock YTB  Arbiter */
#define P_CLK_MAC_LNK1_D3_DIS	BIT_14	/* Disable Clock MAC  Link1 D3 */
#define P_CLK_COR_LNK1_D0_DIS	BIT_13	/* Disable Clock Core Link1 D0 */
#define P_CLK_MAC_LNK1_D0_DIS	BIT_12	/* Disable Clock MAC  Link1 D0 */
#define P_CLK_COR_LNK1_D3_DIS	BIT_11	/* Disable Clock Core Link1 D3 */
#define P_CLK_PCI_MST_ARB_DIS	BIT_10	/* Disable Clock PCI  Master Arb. */
#define P_CLK_COR_REGS_D3_DIS	BIT_9	/* Disable Clock Core Regs D3 */
#define P_CLK_PCI_REGS_D3_DIS	BIT_8	/* Disable Clock PCI  Regs D3 */
#define P_CLK_REF_LNK1_GM_DIS	BIT_7	/* Disable Clock Ref. Link1 GMAC */
#define P_CLK_COR_LNK1_GM_DIS	BIT_6	/* Disable Clock Core Link1 GMAC */
#define P_CLK_PCI_COMMON_DIS	BIT_5	/* Disable Clock PCI  Common */
#define P_CLK_COR_COMMON_DIS	BIT_4	/* Disable Clock Core Common */
#define P_CLK_PCI_LNK1_BMU_DIS	BIT_3	/* Disable Clock PCI  Link1 BMU */
#define P_CLK_COR_LNK1_BMU_DIS	BIT_2	/* Disable Clock Core Link1 BMU */
#define P_CLK_PCI_LNK1_BIU_DIS	BIT_1	/* Disable Clock PCI  Link1 BIU */
#define P_CLK_COR_LNK1_BIU_DIS	BIT_0	/* Disable Clock Core Link1 BIU */

#define PCIE_OUR3_WOL_D3_COLD_SET	( \
							P_CLK_ASF_REGS_DIS | \
							P_CLK_COR_REGS_D0_DIS | \
							P_CLK_COR_LNK1_D0_DIS | \
							P_CLK_MAC_LNK1_D0_DIS | \
							P_CLK_PCI_MST_ARB_DIS | \
							P_CLK_COR_COMMON_DIS | \
							P_CLK_COR_LNK1_BMU_DIS)

/*	PCI_OUR_REG_4		32 bit	Our Register 4 (Yukon-ECU only) */
#define P_PEX_LTSSM_STAT_MSK	(0x7fL<<25)	/* Bit 31..25:	PEX LTSSM Mask */
									/* (Link Training & Status State Machine) */
#define P_ASPM_GPHY_INT_ENA		BIT_24	/* GPHY Interrupt (Yukon-Ext. only) */
#define P_TIMER_VALUE_MSK		(0xffL<<16)	/* Bit 23..16:	Timer Value Mask */
#define P_FORCE_ASPM_REQUEST	BIT_15	/* Force ASPM Request (A1 only) */
										/* (Active State Power Management) */
										/* Bit 14..12: Force ASPM on Event */
#define P_ASPM_GPHY_LINK_DOWN	BIT_14	/* GPHY Link Down (A1 only) */
#define P_ASPM_INT_FIFO_EMPTY	BIT_13	/* Internal FIFO Empty (A1 only) */
#define P_ASPM_CLKRUN_REQUEST	BIT_12	/* CLKRUN Request (A1 only) */
								/* Bit 11.. 7:	reserved */
#define P_PIN63_LINK_LED_ENA	BIT_8	/* Enable Pin #63 as Link LED (A3) */
#define P_ASPM_FORCE_ASPM_L1	BIT_7	/* Force ASPM L1  Enable (A1b only) */
#define P_ASPM_FORCE_ASPM_L0S	BIT_6	/* Force ASPM L0s Enable (A1b only) */
#define P_ASPM_FORCE_CLKREQ_PIN	BIT_5	/* Force CLKREQn pin low (A1b only) */
#define P_ASPM_FORCE_CLKREQ_ENA	BIT_4	/* Force CLKREQ Enable (A1b only) */
#define P_ASPM_CLKREQ_PAD_CTL	BIT_3	/* CLKREQ PAD Control (A1 only) */
#define P_ASPM_A1_MODE_SELECT	BIT_2	/* A1 Mode Select (A1 only) */
#define P_CLK_GATE_PEX_UNIT_ENA	BIT_1	/* Enable Gate PEX Unit Clock */
#define P_CLK_GATE_ROOT_COR_ENA	BIT_0	/* Enable Gate Root Core Clock */

#define P_PEX_LTSSM_STAT(x)		(SHIFT25(x) & P_PEX_LTSSM_STAT_MSK)
#define P_PEX_LTSSM_L1_STAT		0x34
#define P_PEX_LTSSM_DET_STAT	0x01

#define P_ASPM_CONTROL_MSK	(P_FORCE_ASPM_REQUEST | P_ASPM_GPHY_LINK_DOWN | \
							 P_ASPM_CLKRUN_REQUEST | P_ASPM_INT_FIFO_EMPTY | \
							 P_PIN63_LINK_LED_ENA)

#define PCIE_OUR4_DYN_CLK_GATE_SET	( \
							P_PEX_LTSSM_STAT(P_PEX_LTSSM_L1_STAT) | \
							P_TIMER_VALUE_MSK | \
							P_ASPM_INT_FIFO_EMPTY | \
							P_ASPM_CLKRUN_REQUEST | \
							P_ASPM_FORCE_CLKREQ_ENA | \
							P_ASPM_A1_MODE_SELECT | \
							P_CLK_GATE_ROOT_COR_ENA)

/*	PCI_OUR_REG_5		32 bit	Our Register 5 (Yukon-ECU only) */
										/* Bit 31..27:	for A3 & later */
#define P_CTL_DIV_CORE_CLK_ENA	BIT_31	/* Divide Core Clock Enable */
#define P_CTL_SRESET_VMAIN_AV	BIT_30	/* Soft Reset for Vmain_av De-Glitch */
#define P_CTL_BYPASS_VMAIN_AV	BIT_29	/* Bypass En. for Vmain_av De-Glitch */
#define P_CTL_TIM_VMAIN_AV_MSK	(3<<27)	/* Bit 28..27: Timer Vmain_av Mask */
										/* Bit 26..14: Release Clock on Event */
#define P_REL_PCIE_RST_DE_ASS	BIT_26	/* PCIe Reset De-Asserted */
#define P_REL_GPHY_REC_PACKET	BIT_25	/* GPHY Received Packet */
#define P_REL_INT_FIFO_N_EMPTY	BIT_24	/* Internal FIFO Not Empty */
#define P_REL_MAIN_PWR_AVAIL	BIT_23	/* Main Power Available */
#define P_REL_CLKRUN_REQ_REL	BIT_22	/* CLKRUN Request Release */
#define P_REL_PCIE_RESET_ASS	BIT_21	/* PCIe Reset Asserted */
#define P_REL_PME_ASSERTED		BIT_20	/* PME Asserted */
#define P_REL_PCIE_EXIT_L1_ST	BIT_19	/* PCIe Exit L1 State */
#define P_REL_LOADER_NOT_FIN	BIT_18	/* EPROM Loader Not Finished */
#define P_REL_PCIE_RX_EX_IDLE	BIT_17	/* PCIe Rx Exit Electrical Idle State */
#define P_REL_GPHY_LINK_UP		BIT_16	/* GPHY Link Up */
#define P_REL_CPU_TO_SLEEP		BIT_15	/* CPU Goes to Sleep */
#define P_REL_GPHY_ASS_IRQ		BIT_14	/* GPHY Asserts IRQ */
									/* Bit 13:	reserved */
										/* Bit 12.. 0: Mask for Gate Clock */
#define P_GAT_GPHY_ASS_IRQ		BIT_12	/* GPHY Asserts IRQ */
#define P_GAT_CPU_TO_SLEEP		BIT_11	/* CPU Goes to Sleep and Events */
#define P_GAT_PCIE_RST_ASSERTED	BIT_10	/* PCIe Reset Asserted */
#define P_GAT_GPHY_N_REC_PACKET	BIT_9	/* GPHY Not Received Packet */
#define P_GAT_INT_FIFO_EMPTY	BIT_8	/* Internal FIFO Empty */
#define P_GAT_MAIN_PWR_N_AVAIL	BIT_7	/* Main Power Not Available */
#define P_GAT_CLKRUN_REQ_REL	BIT_6	/* CLKRUN Not Requested */
#define P_GAT_PCIE_RESET_ASS	BIT_5	/* PCIe Reset Asserted */
#define P_GAT_PME_DE_ASSERTED	BIT_4	/* PME De-Asserted */
#define P_GAT_PCIE_ENTER_L1_ST	BIT_3	/* PCIe Enter L1 State */
#define P_GAT_LOADER_FINISHED	BIT_2	/* EPROM Loader Finished */
#define P_GAT_PCIE_RX_EL_IDLE	BIT_1	/* PCIe Rx Electrical Idle State */
#define P_GAT_GPHY_LINK_DOWN	BIT_0	/* GPHY Link Down */

#define PCIE_OUR5_EVENT_CLK_D3_SET	( \
							P_REL_GPHY_REC_PACKET | \
							P_REL_INT_FIFO_N_EMPTY | \
							P_REL_CLKRUN_REQ_REL | \
							P_REL_PCIE_EXIT_L1_ST | \
							P_REL_PCIE_RX_EX_IDLE | \
							P_GAT_GPHY_N_REC_PACKET | \
							P_GAT_INT_FIFO_EMPTY | \
							P_GAT_CLKRUN_REQ_REL | \
							P_GAT_PCIE_ENTER_L1_ST | \
							P_GAT_PCIE_RX_EL_IDLE)

/*	PCI_CFG_REG_1			32 bit	Config Register 1 (Yukon-Ext only) */
#define P_CF1_DIS_REL_EVT_RST	BIT_24	/* Dis. Rel. Event during PCIE reset */
										/* Bit 23..21: Release Clock on Event */
#define P_CF1_REL_LDR_NOT_FIN	BIT_23	/* EEPROM Loader Not Finished */
#define P_CF1_REL_VMAIN_AVLBL	BIT_22	/* Vmain available */
#define P_CF1_REL_PCIE_RESET	BIT_21	/* PCI-E reset */
										/* Bit 20..18: Gate Clock on Event */
#define P_CF1_GAT_LDR_NOT_FIN	BIT_20	/* EEPROM Loader Finished */
#define P_CF1_GAT_PCIE_RX_IDLE	BIT_19	/* PCI-E Rx Electrical idle */
#define P_CF1_GAT_PCIE_RESET	BIT_18	/* PCI-E Reset */
#define P_CF1_PRST_PHY_CLKREQ	BIT_17	/* Enable PCI-E rst & PM2PHY gen. CLKREQ */