skgehw.h

这是Marvell Technology Group Ltd. 4355 (rev 12)网卡在linux下的驱动程序源代码

/******************************************************************************
 *
 * Name:	skgehw.h
 * Project:	Gigabit Ethernet Adapters, Common Modules
 * Version:	$Revision: 2.80 $
 * Date:	$Date: 2008/04/22 09:07:41 $
 * Purpose:	Defines and Macros for the Gigabit Ethernet Adapter Product Family
 *
 ******************************************************************************/

/******************************************************************************
 *
 *	LICENSE:
 *	(C)Copyright Marvell.
 *	
 *	This program is free software; you can redistribute it and/or modify
 *	it under the terms of the GNU General Public License as published by
 *	the Free Software Foundation; either version 2 of the License, or
 *	(at your option) any later version.
 *	
 *	The information in this file is provided "AS IS" without warranty.
 *	/LICENSE
 *
 ******************************************************************************/

#ifndef __INC_SKGEHW_H
#define __INC_SKGEHW_H

#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */

/* defines ********************************************************************/

#define BIT_31		(1UL << 31)
#define BIT_30		(1L << 30)
#define BIT_29		(1L << 29)
#define BIT_28		(1L << 28)
#define BIT_27		(1L << 27)
#define BIT_26		(1L << 26)
#define BIT_25		(1L << 25)
#define BIT_24		(1L << 24)
#define BIT_23		(1L << 23)
#define BIT_22		(1L << 22)
#define BIT_21		(1L << 21)
#define BIT_20		(1L << 20)
#define BIT_19		(1L << 19)
#define BIT_18		(1L << 18)
#define BIT_17		(1L << 17)
#define BIT_16		(1L << 16)
#define BIT_15		(1L << 15)
#define BIT_14		(1L << 14)
#define BIT_13		(1L << 13)
#define BIT_12		(1L << 12)
#define BIT_11		(1L << 11)
#define BIT_10		(1L << 10)
#define BIT_9		(1L << 9)
#define BIT_8		(1L << 8)
#define BIT_7		(1L << 7)
#define BIT_6		(1L << 6)
#define BIT_5		(1L << 5)
#define BIT_4		(1L << 4)
#define BIT_3		(1L << 3)
#define BIT_2		(1L << 2)
#define BIT_1		(1L << 1)
#define BIT_0		1L

#define BIT_15S		(1U << 15)
#define BIT_14S		(1 << 14)
#define BIT_13S		(1 << 13)
#define BIT_12S		(1 << 12)
#define BIT_11S		(1 << 11)
#define BIT_10S		(1 << 10)
#define BIT_9S		(1 << 9)
#define BIT_8S		(1 << 8)
#define BIT_7S		(1 << 7)
#define BIT_6S		(1 << 6)
#define BIT_5S		(1 << 5)
#define BIT_4S		(1 << 4)
#define BIT_3S		(1 << 3)
#define BIT_2S		(1 << 2)
#define BIT_1S		(1 << 1)
#define BIT_0S		1

#define SHIFT31(x)	((x) << 31)
#define SHIFT30(x)	((x) << 30)
#define SHIFT29(x)	((x) << 29)
#define SHIFT28(x)	((x) << 28)
#define SHIFT27(x)	((x) << 27)
#define SHIFT26(x)	((x) << 26)
#define SHIFT25(x)	((x) << 25)
#define SHIFT24(x)	((x) << 24)
#define SHIFT23(x)	((x) << 23)
#define SHIFT22(x)	((x) << 22)
#define SHIFT21(x)	((x) << 21)
#define SHIFT20(x)	((x) << 20)
#define SHIFT19(x)	((x) << 19)
#define SHIFT18(x)	((x) << 18)
#define SHIFT17(x)	((x) << 17)
#define SHIFT16(x)	((x) << 16)
#define SHIFT15(x)	((x) << 15)
#define SHIFT14(x)	((x) << 14)
#define SHIFT13(x)	((x) << 13)
#define SHIFT12(x)	((x) << 12)
#define SHIFT11(x)	((x) << 11)
#define SHIFT10(x)	((x) << 10)
#define SHIFT9(x)	((x) << 9)
#define SHIFT8(x)	((x) << 8)
#define SHIFT7(x)	((x) << 7)
#define SHIFT6(x)	((x) << 6)
#define SHIFT5(x)	((x) << 5)
#define SHIFT4(x)	((x) << 4)
#define SHIFT3(x)	((x) << 3)
#define SHIFT2(x)	((x) << 2)
#define SHIFT1(x)	((x) << 1)
#define SHIFT0(x)	((x) << 0)

/* Macro for arbitrary alignment of a given pointer */
#define ALIGN_ADDR( ADDRESS, GRANULARITY ) { \
	SK_UPTR addr = (SK_UPTR)(ADDRESS); \
	if (addr & ((GRANULARITY)-1)) { \
		addr += (GRANULARITY); \
		addr &= ~(SK_UPTR)((GRANULARITY)-1); \
		ADDRESS = (void *)addr; \
	}\
}

/*
 * Configuration Space header
 * Since this module is used for different OS', those may be
 * duplicate on some of them (e.g. Linux). But to keep the
 * common source, we have to live with this...
 */
#define PCI_VENDOR_ID	0x00	/* 16 bit	Vendor ID */
#define PCI_DEVICE_ID	0x02	/* 16 bit	Device ID */
#define PCI_COMMAND		0x04	/* 16 bit	Command */
#define PCI_STATUS		0x06	/* 16 bit	Status */
#define PCI_REV_ID		0x08	/*  8 bit	Revision ID */
#define PCI_CLASS_CODE	0x09	/* 24 bit	Class Code */
#define PCI_CACHE_LSZ	0x0c	/*  8 bit	Cache Line Size */
#define PCI_LAT_TIM		0x0d	/*  8 bit	Latency Timer */
#define PCI_HEADER_T	0x0e	/*  8 bit	Header Type */
#define PCI_BIST		0x0f	/*  8 bit	Built-in selftest */
#define PCI_BASE_1ST	0x10	/* 32 bit	1st Base address */
#define PCI_BASE_2ND	0x14	/* 32 bit	2nd Base address */
	/* Bytes 0x18..0x2b:	reserved */
#define PCI_SUB_VID		0x2c	/* 16 bit	Subsystem Vendor ID */
#define PCI_SUB_ID		0x2e	/* 16 bit	Subsystem ID */
#define PCI_BASE_ROM	0x30	/* 32 bit	Expansion ROM Base Address */
#define PCI_CAP_PTR		0x34	/*  8 bit	Capabilities Pointer */
	/* Bytes 0x35..0x3b:	reserved */
#define PCI_IRQ_LINE	0x3c	/*  8 bit	Interrupt Line */
#define PCI_IRQ_PIN		0x3d	/*  8 bit	Interrupt Pin */
#define PCI_MIN_GNT		0x3e	/*  8 bit	Min_Gnt */
#define PCI_MAX_LAT		0x3f	/*  8 bit	Max_Lat */
	/* Device Dependent Region */
#define PCI_OUR_REG_1	0x40	/* 32 bit	Our Register 1 */
#define PCI_OUR_REG_2	0x44	/* 32 bit	Our Register 2 */
	/* Power Management Region */
#define PCI_PM_CAP_ID	0x48	/*  8 bit	Power Management Cap. ID */
#define PCI_PM_NITEM	0x49	/*  8 bit	PM Next Item Pointer */
#define PCI_PM_CAP_REG	0x4a	/* 16 bit	Power Management Capabilities */
#define PCI_PM_CTL_STS	0x4c	/* 16 bit	Power Manag. Control/Status */
	/* Byte 0x4e:	reserved */
#define PCI_PM_DAT_REG	0x4f	/*  8 bit	Power Manag. Data Register */
	/* VPD Region */
#define PCI_VPD_CAP_ID	0x50	/*  8 bit	VPD Cap. ID */
#define PCI_VPD_NITEM	0x51	/*  8 bit	VPD Next Item Pointer */
#define PCI_VPD_ADR_REG	0x52	/* 16 bit	VPD Address Register */
#define PCI_VPD_DAT_REG	0x54	/* 32 bit	VPD Data Register */
	/* Bytes 0x58..0x59:	reserved */
#define PCI_SER_LD_CTRL	0x5a	/* 16 bit	SEEPROM Loader Ctrl (YUKON only) */
	/* Bytes 0x5c..0xfc:	used by Yukon-2 */
#define PCI_MSI_CAP_ID	0x5c	/*  8 bit	MSI Capability ID Register */
#define PCI_MSI_NITEM	0x5d	/*  8 bit	MSI Next Item Pointer */
#define PCI_MSI_CTRL	0x5e	/* 16 bit	MSI Message Control */
#define PCI_MSI_ADR_LO	0x60	/* 32 bit	MSI Message Address (Lower) */
#define PCI_MSI_ADR_HI	0x64	/* 32 bit	MSI Message Address (Upper) */
#define PCI_MSI_DATA	0x68	/* 16 bit	MSI Message Data */
	/* Bytes 0x6a..0x6b:	reserved */
#define PCI_X_CAP_ID	0x6c	/*  8 bit	PCI-X Capability ID Register */
#define PCI_X_NITEM		0x6d	/*  8 bit	PCI-X Next Item Pointer */
#define PCI_X_COMMAND	0x6e	/* 16 bit	PCI-X Command */
#define PCI_X_PE_STAT	0x70	/* 32 bit	PCI-X / PE Status */
#define PCI_CAL_CTRL	0x74	/* 16 bit	PCI Calibration Control Register */
#define PCI_CAL_STAT	0x76	/* 16 bit	PCI Calibration Status Register */
#define PCI_DISC_CNT	0x78	/* 16 bit	PCI Discard Counter */
#define PCI_RETRY_CNT	0x7a	/*  8 bit	PCI Retry Counter */
	/* Byte 0x7b:	reserved */
#define PCI_OUR_STATUS	0x7c	/* 32 bit	Adapter Status Register */
#define PCI_OUR_REG_3	0x80	/* 32 bit	Our Register 3 (Yukon-ECU only) */
#define PCI_OUR_REG_4	0x84	/* 32 bit	Our Register 4 (Yukon-ECU only) */
#define PCI_OUR_REG_5	0x88	/* 32 bit	Our Register 5 (Yukon-ECU only) */
#define PCI_ERR_REP_MSK	0x8c	/* 32 bit	Error Rep. Mask (Yukon-ECU A1b) */
#define PCI_CFG_REG_0	0x90	/* 32 bit	Config Register 0 (Yukon-Ext only) */
#define PCI_CFG_REG_1	0x94	/* 32 bit	Config Register 1 (Yukon-Ext only) */
	/* Bytes 0x98..0xdf:	reserved */

/* PCI Express Capability */
#define PEX_CAP_ID		0xe0	/*  8 bit	PEX Capability ID */
#define PEX_NITEM		0xe1	/*  8 bit	PEX Next Item Pointer */
#define PEX_CAP_REG		0xe2	/* 16 bit	PEX Capability Register */
#define PEX_DEV_CAP		0xe4	/* 32 bit	PEX Device Capabilities */
#define PEX_DEV_CTRL	0xe8	/* 16 bit	PEX Device Control */
#define PEX_DEV_STAT	0xea	/* 16 bit	PEX Device Status */
#define PEX_LNK_CAP		0xec	/* 32 bit	PEX Link Capabilities */
#define PEX_LNK_CTRL	0xf0	/* 16 bit	PEX Link Control */
#define PEX_LNK_STAT	0xf2	/* 16 bit	PEX Link Status */
	/* Bytes 0xf4..0xff:	reserved */

/*
 * Yukon-Extreme B0: These registers have been moved to 0xc0..0xd2.
 *					 Use PEX_CAP_REGS() macro to access
 */
#define PEX_CAP_REG_OFFS	0x20
#define PEX_CAP_REGS(Reg)	((Reg) - (pAC->GIni.GIPexCapOffs))

/* PCI Express Extended Capabilities */
#define PEX_ADV_ERR_REP		0x100	/* 32 bit	PEX Advanced Error Reporting */
#define PEX_UNC_ERR_STAT	0x104	/* 32 bit	PEX Uncorr. Errors Status */
#define PEX_UNC_ERR_MASK	0x108	/* 32 bit	PEX Uncorr. Errors Mask */
#define PEX_UNC_ERR_SEV		0x10c	/* 32 bit	PEX Uncorr. Errors Severity */
#define PEX_COR_ERR_STAT	0x110	/* 32 bit	PEX Correc. Errors Status */
#define PEX_COR_ERR_MASK	0x114	/* 32 bit	PEX Correc. Errors Mask */
#define PEX_ADV_ERR_CAP_C	0x118	/* 32 bit	PEX Advanced Error Cap./Ctrl */
#define PEX_HEADER_LOG		0x11c	/* 4x32 bit	PEX Header Log Register */

#define PEX_COMPL_TIMEOUT	0x220	/* 32 bit	PEX Completion Timeout */
#define PEX_FLOW_CONTROL	0x224	/* 32 bit	PEX Flow Control */

/* PCI Express Ack Timer for 1x Link */
#define PEX_ACK_LAT_TOX1	0x228	/* 16 bit	PEX Ack Latency Timeout x1 */
#define PEX_ACK_RPLY_TOX1	0x22a	/* 16 bit	PEX Ack Reply Timeout val x1 */

/*
 * I2C Address (PCI Config)
 *
 * Note:
 *	The temperature and voltage sensors are relocated on a different I2C bus
 */
#define I2C_ADDR_VPD	0xa0	/* I2C address for the VPD EEPROM */

/*
 * Define Bits and Values of the registers
 */
/*	PCI_COMMAND	16 bit	Command */
								/* Bit 15..11:	reserved */
#define PCI_INT_DIS		BIT_10S		/* Interrupt INTx# disable (PCI 2.3) */
#define PCI_FBTEN		BIT_9S		/* Fast Back-To-Back enable */
#define PCI_SERREN		BIT_8S		/* SERR enable */
#define PCI_ADSTEP		BIT_7S		/* Address Stepping */
#define PCI_PERREN		BIT_6S		/* Parity Report Response enable */
#define PCI_VGA_SNOOP	BIT_5S		/* VGA palette snoop */
#define PCI_MWIEN		BIT_4S		/* Memory write an inv cycl enable */
#define PCI_SCYCEN		BIT_3S		/* Special Cycle enable */
#define PCI_BMEN		BIT_2S		/* Bus Master enable */
#define PCI_MEMEN		BIT_1S		/* Memory Space Access enable */
#define PCI_IOEN		BIT_0S		/* I/O Space Access enable */

#define PCI_COMMAND_VAL	(PCI_INT_DIS | PCI_SERREN | PCI_PERREN | \
						 PCI_BMEN | PCI_MEMEN | PCI_IOEN)

/*	PCI_STATUS	16 bit	Status */
#define PCI_PERR		BIT_15S		/* Parity Error */
#define PCI_SERR		BIT_14S		/* Signaled SERR */
#define PCI_RMABORT		BIT_13S		/* Received Master Abort */
#define PCI_RTABORT		BIT_12S		/* Received Target Abort */
								/* Bit 11:	reserved */
#define PCI_DEVSEL		(3<<9)		/* Bit 10.. 9:	DEVSEL Timing */
#define PCI_DEV_FAST	(0<<9)		/*		fast */
#define PCI_DEV_MEDIUM	(1<<9)		/*		medium */
#define PCI_DEV_SLOW	(2<<9)		/*		slow */
#define PCI_DATAPERR	BIT_8S		/* DATA Parity error detected */
#define PCI_FB2BCAP		BIT_7S		/* Fast Back-to-Back Capability */
#define PCI_UDF			BIT_6S		/* User Defined Features */
#define PCI_66MHZCAP	BIT_5S		/* 66 MHz PCI bus clock capable */
#define PCI_NEWCAP		BIT_4S		/* New cap. list implemented */
#define PCI_INT_STAT	BIT_3S		/* Interrupt INTx# Status (PCI 2.3) */
								/* Bit  2.. 0:	reserved */

#define PCI_ERRBITS	(PCI_PERR | PCI_SERR | PCI_RMABORT | PCI_RTABORT |\
					 PCI_DATAPERR)

/*	PCI_CLASS_CODE	24 bit	Class Code */
/*	Byte 2:		Base Class		(02) */
/*	Byte 1:		SubClass		(00) */
/*	Byte 0:		Programming Interface	(00) */

/*	PCI_CACHE_LSZ	8 bit	Cache Line Size */