mvyexhw.h

这是Marvell Technology Group Ltd. 4355 (rev 12)网卡在linux下的驱动程序源代码

/* Enable TX BMU Read IDLE for ASPM Request */
#define	CONFIG_REG1_EN_ASPM_TX_BMU_RD				BIT_1			
/* Enable TX BMU Write IDLE for ASPM Request */
#define	CONFIG_REG1_EN_ASPM_TX_BMU_WR				BIT_0			

/*	PSM_CONFIG_REG0			0x0098	PSM Config Register 0 */
/* PSM Timer Configuration Value */
#define	PSM_CONFIG_REG0_PSM_TIM_CONF_MSK		SHIFT0(0xffffffff)	
#define	PSM_CONFIG_REG0_PSM_TIM_CONF_BASE		0

/*	PSM_CONFIG_REG1			0x009C	PSM Config Register 1 */
/* GPHY Energy Detect Status */
#define	PSM_CONFIG_REG1_GPHY_ENERGY_STS				BIT_31			
#define	PSM_CONFIG_REG1_UART_MODE_MSK				SHIFT29(0x3)	/* UART_Mode */
#define	PSM_CONFIG_REG1_UART_MODE_BASE				29
/* Enable Clock Free Running for ASF Subsystem */
#define	PSM_CONFIG_REG1_CLK_RUN_ASF					BIT_28			
/* Disable UART clock */
#define	PSM_CONFIG_REG1_UART_CLK_DISABLE			BIT_27			
/* Tie internal Vaux to 1'b1 */
#define	PSM_CONFIG_REG1_VAUX_ONE					BIT_26			
/* Default value for UART_RI_n */
#define	PSM_CONFIG_REG1_UART_FC_RI_VAL				BIT_25			
/* Default value for UART_DCD_n */
#define	PSM_CONFIG_REG1_UART_FC_DCD_VAL				BIT_24			
/* Default value for UART_DSR_n */
#define	PSM_CONFIG_REG1_UART_FC_DSR_VAL				BIT_23			
/* Default value for UART_CTS_n */
#define	PSM_CONFIG_REG1_UART_FC_CTS_VAL				BIT_22			
/* Enable Latch current Vaux_avlbl */
#define	PSM_CONFIG_REG1_LATCH_VAUX					BIT_21			
/* Force Testmode pin as input PAD */
#define	PSM_CONFIG_REG1_FORCE_TESTMODE_INPUT		BIT_20			
#define	PSM_CONFIG_REG1_UART_RST					BIT_19			/* UART_RST */
/* PCIE L1 Event Polarity for PSM */
#define	PSM_CONFIG_REG1_PSM_PCIE_L1_POL				BIT_18			
/* PSM Timer Status */
#define	PSM_CONFIG_REG1_TIMER_STAT					BIT_17			
/* GPHY INT Status */
#define	PSM_CONFIG_REG1_GPHY_INT					BIT_16			
/* Force internal Testmode as 1'b0 */
#define	PSM_CONFIG_REG1_FORCE_TESTMODE_ZERO			BIT_15			
/* ENABLE INT for CLKRUN on ASPM and CLKREQ */
#define	PSM_CONFIG_REG1_EN_INT_ASPM_CLKREQ			BIT_14			
/* ENABLE Snd_task for CLKRUN on ASPM and CLKREQ */
#define	PSM_CONFIG_REG1_EN_SND_TASK_ASPM_CLKREQ		BIT_13			
/* Disable CLK_GATE control snd_task */
#define	PSM_CONFIG_REG1_DIS_CLK_GATE_SND_TASK		BIT_12			
/* Disable flip-flop chain for sndmsg_inta */
#define	PSM_CONFIG_REG1_DIS_FF_CHIAN_SND_INTA		BIT_11			
/*		Bit(s) PSM_CONFIG_REG1_RSRV_10 reserved */
/* Disable Loader SM after PSM Goes back to IDLE */
#define	PSM_CONFIG_REG1_DIS_LOADER					BIT_9			
/* Do Power Down, Start PSM Scheme */
#define	PSM_CONFIG_REG1_DO_PWDN						BIT_8			
/* Disable Plug-in-Go SM after PSM Goes back to IDLE */
#define	PSM_CONFIG_REG1_DIS_PIG						BIT_7			
/* Disable Internal PCIe Reset after PSM Goes back to IDLE */
#define	PSM_CONFIG_REG1_DIS_PERST					BIT_6			
/* Enable REG18 Power Down for PSM */
#define	PSM_CONFIG_REG1_EN_REG18_PD					BIT_5			
/* Disable EEPROM Loader after PSM Goes back to IDLE */
#define	PSM_CONFIG_REG1_EN_PSM_LOAD					BIT_4			
/* Enable PCIe Hot Reset for PSM */
#define	PSM_CONFIG_REG1_EN_PSM_HOT_RST				BIT_3			
/* Enable PCIe Reset Event for PSM */
#define	PSM_CONFIG_REG1_EN_PSM_PERST				BIT_2			
/* Enable PCIe L1 Event for PSM */
#define	PSM_CONFIG_REG1_EN_PSM_PCIE_L1				BIT_1			
/* Enable PSM Scheme */
#define	PSM_CONFIG_REG1_EN_PSM						BIT_0			

/*	VPD_CTRL_ADD					0x00A0	VPD Start End Address */
#define	VPD_CTRL_ADD_VPD_END_MSK			SHIFT24(0xff)	/* VPD_END */
#define	VPD_CTRL_ADD_VPD_END_BASE			24
#define	VPD_CTRL_ADD_VPD_W_START_MSK		SHIFT16(0xff)	/* VPD_W_START */
#define	VPD_CTRL_ADD_VPD_W_START_BASE		16
#define	VPD_CTRL_ADD_VPD_START_MSK			SHIFT8(0xff)	/* VPD_START */
#define	VPD_CTRL_ADD_VPD_START_BASE			8
#define	VPD_CTRL_ADD_OTP_BYTE_EN_MSK		SHIFT4(0xf)		/* OTP_BYTE_EN */
#define	VPD_CTRL_ADD_OTP_BYTE_EN_BASE		4
/*		Bit(s) VPD_CTRL_ADD_RSRV_3 reserved */
#define	VPD_CTRL_ADD_EEPROM_EN				BIT_2			/* EEPROM_EN */
#define	VPD_CTRL_ADD_OTP_EN					BIT_1			/* OTP_EN */
#define	VPD_CTRL_ADD_VPD_SEL				BIT_0			/* VPD_SEL */

/* Yukon-Supreme */
/*	FLASH_LDR_CTRL			0x00A4	Flash Loader Control Register */
#define	FLASH_LDR_CTRL_OTP_FLAG						BIT_31			/* Flag */
#define	FLASH_LDR_CTRL_FLASH_REGION					BIT_30			/* Flash Region */
/* Start Address for Flash Loader */
#define	FLASH_LDR_CTRL_FLASH_ADDR_MSK				SHIFT16(0x3fff)	
#define	FLASH_LDR_CTRL_FLASH_ADDR_BASE				16
/* Flash Start Address for PCI Loader */
#define	FLASH_LDR_CTRL_FLASH_LOADER_PCI_MSK			SHIFT8(0xff)	
#define	FLASH_LDR_CTRL_FLASH_LOADER_PCI_BASE		8
/* Flash Loader Start Address for PiG */
#define	FLASH_LDR_CTRL_FLASH_LOADER_PIG_MSK			SHIFT0(0xff)	
#define	FLASH_LDR_CTRL_FLASH_LOADER_PIG_BASE		0

/* Yukon-Fe+ */
/*	OTP_LDR_CTRL					0x00A4	OTP Loader Control Register */
#define	OTP_LDR_CTRL_OTP_FLAG						BIT_31			/* Flag */
#define	OTP_LDR_CTRL_OTP_ADDR_MSK					SHIFT16(0x7fff)	/* OTP Address */
#define	OTP_LDR_CTRL_OTP_ADDR_BASE					16
/* EEPROM timeout flag */
#define	OTP_LDR_CTRL_EEPROM_TIMEOUT_FLAG			BIT_15			
/* EEPROM timeout disable */
#define	OTP_LDR_CTRL_EEPROM_TIMEOUT_DIS				BIT_14			
/*		Bit(s) OTP_LDR_CTRL_RSRV_13_12 reserved */
/* EEPROM timeout value */
#define	OTP_LDR_CTRL_EEPROM_TIMEOUT_VAL_MSK			SHIFT9(0x7)		
#define	OTP_LDR_CTRL_EEPROM_TIMEOUT_VAL_BASE		9
/*		Bit(s) OTP_LDR_CTRL_RSRV_8 reserved */
/* OTP start Address */
#define	OTP_LDR_CTRL_OTP_ST_ADD_MSK					SHIFT0(0xff)	
#define	OTP_LDR_CTRL_OTP_ST_ADD_BASE				0

/* Yukon-Supreme */
/*	LD_STATUS_0				0x00A8	LOADER STATUS */
/* Flash AHB Timeout */
#define	LD_STATUS_0_FLASH_LOADER_TIMEOUT		BIT_31				
/* EEPROM Serial Interface Timeout */
#define	LD_STATUS_0_EEPROM_LOADER_TIMEOUT		BIT_30				
/*		Bit(s) LD_STATUS_0_RSRV_29_0 reserved */

/* Yukon-Fe+ */
/*	OTP_MEM_CTRL_0					0x00A8	OTP Memory Control Register 0 */
#define	OTP_MEM_CTRL_0_CE2RD_SU_TIME_MSK		SHIFT24(0xff)	/* CERD setup time */
#define	OTP_MEM_CTRL_0_CE2RD_SU_TIME_BASE		24
/* Write data hold time */
#define	OTP_MEM_CTRL_0_WRDAT_HLD_TIME_MSK		SHIFT20(0xf)	
#define	OTP_MEM_CTRL_0_WRDAT_HLD_TIME_BASE		20
#define	OTP_MEM_CTRL_0_WRDAT_VLD_TIME_MSK		SHIFT16(0xf)	/* Write valid time */
#define	OTP_MEM_CTRL_0_WRDAT_VLD_TIME_BASE		16
/* Write data setup time */
#define	OTP_MEM_CTRL_0_WRDAT_SU_TIME_MSK		SHIFT12(0xf)	
#define	OTP_MEM_CTRL_0_WRDAT_SU_TIME_BASE		12
/* Read data setup time */
#define	OTP_MEM_CTRL_0_RDDAT_SU_TIME_MSK		SHIFT4(0xff)	
#define	OTP_MEM_CTRL_0_RDDAT_SU_TIME_BASE		4
#define	OTP_MEM_CTRL_0_RST_PULSE_WIDTH_MSK		SHIFT0(0xf)		/* RSTB pulse width */
#define	OTP_MEM_CTRL_0_RST_PULSE_WIDTH_BASE		0

/*	OTP_MEM_CTRL_1					0x00AC	OTP Memory Control Register 1 */
/* CPUMPEN hold time */
#define	OTP_MEM_CTRL_1_CPUMEM_HLD_TIME_MSK		SHIFT28(0xf)	
#define	OTP_MEM_CTRL_1_CPUMEM_HLD_TIME_BASE		28
/* CPUMPEN setup time */
#define	OTP_MEM_CTRL_1_CPUMEM_SU_TIME_MSK		SHIFT24(0xf)	
#define	OTP_MEM_CTRL_1_CPUMEM_SU_TIME_BASE		24
#define	OTP_MEM_CTRL_1_PGMEN_HLD_TIME_MSK		SHIFT16(0xff)	/* PGMEN hold time */
#define	OTP_MEM_CTRL_1_PGMEN_HLD_TIME_BASE		16
#define	OTP_MEM_CTRL_1_PGMEN_VLD_TIME_MSK		SHIFT4(0xfff)	/* Program time */
#define	OTP_MEM_CTRL_1_PGMEN_VLD_TIME_BASE		4
#define	OTP_MEM_CTRL_1_PGMEN_SU_TIME_MSK		SHIFT0(0xf)		/* PGMEN setup time */
#define	OTP_MEM_CTRL_1_PGMEN_SU_TIME_BASE		0

/*	OTP_MEM_CTRL_2					0x00B0	OTP Memory Control Register 2 */
/* OTP ctrl module status */
#define	OTP_MEM_CTRL_2_OTP_DBG_BITS_MSK			SHIFT16(0xffff)	
#define	OTP_MEM_CTRL_2_OTP_DBG_BITS_BASE		16
#define	OTP_MEM_CTRL_2_OTP_TST_MODE_MSK			SHIFT8(0xff)	/* OTP test mode */
#define	OTP_MEM_CTRL_2_OTP_TST_MODE_BASE		8
/*		Bit(s) OTP_MEM_CTRL_2_RSRV_7 reserved */
/* Auto read back after programming */
#define	OTP_MEM_CTRL_2_AUTO_RD_AFTER_WR			BIT_6			
/* OTP test mode enable */
#define	OTP_MEM_CTRL_2_TSTMODE_ENA				BIT_5			
#define	OTP_MEM_CTRL_2_OTP_RST_WHEN_WR			BIT_4			/* OTP reset mode */
/* OTP CEB always low */
#define	OTP_MEM_CTRL_2_CEB_KEEP_LOW				BIT_3			
#define	OTP_MEM_CTRL_2_BYPASS2RSTB				BIT_2			/* OTP RSTB */
#define	OTP_MEM_CTRL_2_BYPASS2RSTB_ENA			BIT_1			/* OTP RSTB enable */
/* OTP interface module reset */
#define	OTP_MEM_CTRL_2_OTP_IF_FREEZE			BIT_0			

/*	OTP_MEM_ST_0					0x00B4	OTP Memory Status Register 0 */
/* OTP memory LOCK pin */
#define	OTP_MEM_ST_0_OTP_LOCK_PIN			BIT_31				
/*		Bit(s) OTP_MEM_ST_0_RSRV_30_24 reserved */
/* OTP memory DOUT pin */
#define	OTP_MEM_ST_0_OTP_DOUT_PIN			BIT_23				
/*		Bit(s) OTP_MEM_ST_0_RSRV_22_0 reserved */

/* Yukon-Supreme */
/*	VPD_FLASH_CTRL			0x00B8	EEPROM and Flash Control Register */
/* Disable MDIO to YTB Bus Read/Write */
#define	VPD_FLASH_CTRL_MDIO2YTB_DIS					BIT_31			
/* Software Reset MDIO to YTB Bus */
#define	VPD_FLASH_CTRL_MDIO2YTB_SWRST				BIT_30			
/*		Bit(s) VPD_FLASH_CTRL_RSRV_29_28 reserved */
/* Flash Loader AHB Request Timeout Disable */
#define	VPD_FLASH_CTRL_FLASH_AHB_TIMEOUT_DIS		BIT_27			
/* TWSI Serial Interface Timeout Disable */
#define	VPD_FLASH_CTRL_TWSI_IF_TIMEOUT_DIS			BIT_26			
/*		Bit(s) VPD_FLASH_CTRL_RSRV_25_24 reserved */
/* Flash Loader AHB Request Timeout Value */
#define	VPD_FLASH_CTRL_FLASH_AHB_TIMEOUT_MSK		SHIFT21(0x7)	
#define	VPD_FLASH_CTRL_FLASH_AHB_TIMEOUT_BASE		21
/*		Bit(s) VPD_FLASH_CTRL_RSRV_20 reserved */
/* TWSI Serial Interface Timeout Value */
#define	VPD_FLASH_CTRL_TWSI_IF_TIMEOUT_MSK			SHIFT17(0x7)	
#define	VPD_FLASH_CTRL_TWSI_IF_TIMEOUT_BASE			17
/*		Bit(s) VPD_FLASH_CTRL_RSRV_16 reserved */
/* EEPROM Loader Timeout Disable */
#define	VPD_FLASH_CTRL_EEPROM_TMOUT_DIS				BIT_15			
/* Flash Loader Timeout Disable */
#define	VPD_FLASH_CTRL_FLASH_TMOUT_DIS				BIT_14			
/* EEPROM Loader Timeout Value */
#define	VPD_FLASH_CTRL_EEPROM_TMOUT_VALUE_MSK		SHIFT12(0x3)	
#define	VPD_FLASH_CTRL_EEPROM_TMOUT_VALUE_BASE		12
/* Flash Loader Timeout Value */
#define	VPD_FLASH_CTRL_FLASH_TMOUT_VALUE_MSK		SHIFT10(0x3)	
#define	VPD_FLASH_CTRL_FLASH_TMOUT_VALUE_BASE		10
/* EEPROM Speed Select */
#define	VPD_FLASH_CTRL_SPEED_SELECT_MSK				SHIFT0(0x3ff)	
#define	VPD_FLASH_CTRL_SPEED_SELECT_BASE			0

/* Yukon-Fe+ */
/*	VPD_CTRL						0x00B8	EEPROM and OTP Control Register */
/* mdio to ytb bus IF disable */
#define	VPD_CTRL_MDIO2YTB_DIS			BIT_31			
/* mdio to ytb bus IF software reset */
#define	VPD_CTRL_MDIO2YTB_SWRST			BIT_30			
#define	VPD_CTRL_OTP_TOP_RST			BIT_29			/* otp_top software reset */
/*		Bit(s) VPD_CTRL_RSRV_28_18 reserved */
#define	VPD_CTRL_OTP_IF_TMOUT_MSK		SHIFT16(0x3)	/* otp timeout reg */
#define	VPD_CTRL_OTP_IF_TMOUT_BASE		16
/* EEPROM loader timeout disable */
#define	VPD_CTRL_TMOUT_DIS				BIT_15			
/*		Bit(s) VPD_CTRL_RSRV_14 reserved */
/* EEPROM loader timeout val */
#define	VPD_CTRL_TMOUT_VALUE_MSK		SHIFT12(0x3)	
#define	VPD_CTRL_TMOUT_VALUE_BASE		12
/*		Bit(s) VPD_CTRL_RSRV_11_10 reserved */
#define	VPD_CTRL_SPEED_SELECT_MSK		SHIFT0(0x3ff)	/* EEPROM speed select */
#define	VPD_CTRL_SPEED_SELECT_BASE		0

/*	OTP_MEM_CTRL_3					0x00BC	LDO Control Register */
/*		Bit(s) OTP_MEM_CTRL_3_RSRV_31_14 reserved */
/* CLK generator filter bypass */
#define	OTP_MEM_CTRL_3_CLK_GEN_BYPASS			BIT_13				
/* CLK generator soft reset */
#define	OTP_MEM_CTRL_3_CLK_GEN_RST				BIT_12				
/* CLK generator filter control */
#define	OTP_MEM_CTRL_3_CLK_GEN_CTRL_MSK			SHIFT8(0xf)			
#define	OTP_MEM_CTRL_3_CLK_GEN_CTRL_BASE		8
/* LDO 2.5 V testmode sel */
#define	OTP_MEM_CTRL_3_LDO25TSTMODE_MSK			SHIFT4(0x7)			
#define	OTP_MEM_CTRL_3_LDO25TSTMODE_BASE		4
/* LDO 1.2 V testmode sel */
#define	OTP_MEM_CTRL_3_LDO12TSTMODE_MSK			SHIFT0(0x7)			
#define	OTP_MEM_CTRL_3_LDO12TSTMODE_BASE		0

/*	PCIE_CAP_ID						0x00C0	PE Capability ID Register (PM Cap
 *											ID)
 */
#define	PCIE_CAP_ID_MSK			SHIFT0(0xffU)	/* Cap ID */
#define	PCIE_CAP_ID_BASE		0

/*	PCIE_NPTR				0x00C1	PE Next Item Pointer Register */
#define	PCIE_NPTR_MSK		SHIFT0(0xffU)	/* Next Item Pointer */
#define	PCIE_NPTR_BASE		0

/*	PCIE_CAP				0x00C2	PE Capabilities Register */
/*		Bit(s) PCIE_CAP_RSRV_15_14 reserved */
#define	PCIE_CAP_INTMSG_NUM_MSK			SHIFT9(0x1fU)	/* Interrupt Message Number */
#define	PCIE_CAP_INTMSG_NUM_BASE		9
/*		Bit(s) PCIE_CAP_RSRV_8 reserved */
#define	PCIE_CAP_PORT_TYP_MSK			SHIFT4(0xfU)	/* Device/Port Type */
#define	PCIE_CAP_PORT_TYP_BASE			4
#define	PCIE_CAP_CAP_VER_MSK			SHIFT0(0xfU)	/* Capability Version */
#define	PCIE_CAP_CAP_VER_BASE			0

/*	DEVICE_CAPABILITIES		0x00C4	Device Capabilities Register */
/*		Bit(s) DEVICE_CAPABILITIES_RSRV_31_28 reserved */
/* Captured Slot Power Limit Scale */
#define	DEVICE_CAPABILITIES_SPL_SCALE_MSK			SHIFT26(0x3)	
#define	DEVICE_CAPABILITIES_SPL_SCALE_BASE			26
/* Captured Slot Power Limit Value */
#define	DEVICE_CAPABILITIES_SPL_VAL_MSK				SHIFT18(0xff)	
#define	DEVICE_CAPABILITIES_SPL_VAL_BASE			18
/*		Bit(s) DEVICE_CAPABILITIES_RSRV_17_16 reserved */
/* Role-Based Error Reporting */
#define	DEVICE_CAPABILITIES_ROLE_BASED_ERR_RPT		BIT_15			
/* Power Indicator Present */
#define	DEVICE_CAPABILITIES_PI_PRS					BIT_14			
/* Attention Indicator Present */
#define	DEVICE_CAPABILITIES_AI_PRS					BIT_13			
/* Attention Button Present */
#define	DEVICE_CAPABILITIES_AB_PRS					BIT_12			
/* Endpoint L1 Acceptable Latency */
#define	DEVICE_CAPABILITIES_L1_AC_LAT_MSK			SHIFT9(0x7)		
#define	DEVICE_CAPABILITIES_L1_AC_LAT_BASE			9
/* Endpoint L0s Acceptable Latency */
#define	DEVICE_CAPABILITIES_L0_AC_LAT_MSK			SHIFT6(0x7)		
#define	DEVICE_CAPABILITIES_L0_AC_LAT_BASE			6
/* Extended Tag Field Supported */
#define	DEVICE_CAPABILITIES_EXTTAG_SUP				BIT_5			
/* Phantom Functions Supported */
#define	DEVICE_CAPABILITIES_PHANTOM_SUP_MSK			SHIFT3(0x3)		
#define	DEVICE_CAPABILITIES_PHANTOM_SUP_BASE		3
/* Max Payload Size Supported */
#define	DEVICE_CAPABILITIES_MAX_PLS_SUP_MSK			SHIFT0(0x7)		
#define	DEVICE_CAPABILITIES_MAX_PLS_SUP_BASE		0

/*	PCIE_DEVCTRL			0x00C8	Device Control Register */
/*		Bit(s) PCIE_DEVCTRL_RSRV_15 reserved */
#define	PCIE_DEVCTRL_MAX_RRS_MSK		SHIFT12(0x7U)	/* Max Read Request Size */