mvyexhw.h

这是Marvell Technology Group Ltd. 4355 (rev 12)网卡在linux下的驱动程序源代码

/*	PCIE_OUR3				0x0080	Our Register 3 */
/* Mask L0 Condition */
#define	PCIE_OUR3_MASK_L0_COMMA					BIT_31			
/* Mask L0s Condition */
#define	PCIE_OUR3_MASK_L0S_COMMA				BIT_30			
/* Select MACSec clock */
#define	PCIE_OUR3_MACSEC_CLK_SEL				BIT_29			
/*		Bit(s) PCIE_OUR3_RSRV_27_20 reserved */
/* Select MAC Rx Clock for Tx */
#define	PCIE_OUR3_CLK_RX_TO_TX					BIT_28			
/* Disable Free Running Clock for GMAC and WOL */
#define	PCIE_OUR3_DIS_CLK_WOL_GMAC				BIT_27          /* Yukon-Supreme */			
/*		Bit(s) PCIE_OUR3_RSRV_26_21 reserved */
/* Disable clk_clk for ASF Flash */
#define	PCIE_OUR3_CLK_FLASH_DIS					BIT_20			/* Yukon-Supreme */
/* Disable clk_clk for USB */
#define	PCIE_OUR3_CLK_USB_DIS					BIT_19          /* Yukon-Supreme */
/* Disable clk_clk for USB */
#define	PCIE_OUR3_CLK_USB_DIS					BIT_19			
#define	PCIE_OUR3_CLK_ASF_REGS_DIS				BIT_18			/* Disable clk_asf */
/*		Bit(s) PCIE_OUR3_RSRV_17 reserved */
/* Disable clk_pci_regs_d0 */
#define	PCIE_OUR3_CLK_PCI_REGS_DIS				BIT_16			
/* Disable clk_core_ytb_arb */
#define	PCIE_OUR3_CLK_CORE_YTB_ARB_DIS			BIT_15			
/* Disable clk_mac_lnk1_d3 */
#define	PCIE_OUR3_CLK_MAC_LNK1_D3_DIS			BIT_14			
/* Disable clk_core_lnk1_d0 */
#define	PCIE_OUR3_CLK_CORE_LNK1_D0_DIS			BIT_13			
/* Disable clk_mac_lnk1_d0 */
#define	PCIE_OUR3_CLK_MAC_LNK1_D0_DIS			BIT_12			
/* Disable clk_core_lnk1_d3 */
#define	PCIE_OUR3_CLK_CORE_LNK1_D3_DIS			BIT_11			
/* Disable clk_pci_master_arb */
#define	PCIE_OUR3_CLK_PCI_MST_ARB_DIS			BIT_10			
/* Disable clk_core_regs_d3 */
#define	PCIE_OUR3_CLK_CORE_REGS_D3_DIS			BIT_9			
/* Disable clk_pci_regs_d3 */
#define	PCIE_OUR3_CLK_PCI_REGS_D3_DIS			BIT_8			
/* Disable clk_ref_lnk1_gmac */
#define	PCIE_OUR3_CLK_REF_LNK1_GMAC_DIS			BIT_7			
/* Disable clk_core_lnk1_gmac */
#define	PCIE_OUR3_CLK_CORE_LNK1_GMAC_DIS		BIT_6			
/* Disable clk_pci_common */
#define	PCIE_OUR3_CLK_PCI_COM_DIS				BIT_5			
/* Disable clk_core_common */
#define	PCIE_OUR3_CLK_CORE_COM_DIS				BIT_4			
/* Disable clk_pci_lnk1_bmu */
#define	PCIE_OUR3_CLK_PCI_LNK1_BMU_DIS			BIT_3			
/* Disable clk_core_lnk1_bmu */
#define	PCIE_OUR3_CLK_CORE_LNK1_BMU_DIS			BIT_2			
/* Disable pci_clk_biu */
#define	PCIE_OUR3_PCI_CLK_BIU_DIS				BIT_1			
/* Disable clk_core_biu */
#define	PCIE_OUR3_CLK_CORE_BIU_DIS				BIT_0			

#define PCIE_OUR3_WOL_D3_COLD_SETTING		\
	( PCIE_OUR3_CLK_CORE_LNK1_BMU_DIS	|	\
	  PCIE_OUR3_CLK_CORE_COM_DIS		|	\
	  PCIE_OUR3_CLK_PCI_MST_ARB_DIS		|	\
	  PCIE_OUR3_CLK_MAC_LNK1_D0_DIS		|	\
	  PCIE_OUR3_CLK_CORE_LNK1_D0_DIS	|	\
	  PCIE_OUR3_CLK_PCI_REGS_DIS		|	\
	  PCIE_OUR3_CLK_MACSEC_REGS_DIS 	|	\
	  PCIE_OUR3_CLK_ASF_REGS_DIS)

/*	PCIE_OUR4				0x0084	Our Register 4 */
/* PEXUNIT LTSSM State for Gating Core Clock */
#define	PCIE_OUR4_PEX_LTSSM_STATE_MSK			SHIFT25(0x7f)	
#define	PCIE_OUR4_PEX_LTSSM_STATE_BASE			25
#define	PCIE_OUR4_GPHY_INT_ASPM					BIT_24			/* GPHY Get INT */
#define	PCIE_OUR4_TIM_VAL_MSK					SHIFT16(0xff)	/* Timer Value */
#define	PCIE_OUR4_TIM_VAL_BASE					16
/* Force ASPM Request */
#define	PCIE_OUR4_FORCE_ASPM_REQ				BIT_15			
#define	PCIE_OUR4_GPHY_LNK_DOWN					BIT_14			/* GPHY Link Down */
/* Internal FIFO Empty */
#define	PCIE_OUR4_INT_FIFO_EMPTY				BIT_13			
#define	PCIE_OUR4_CLKRUN_REQ					BIT_12			/* Clkrun Request */
/* Enable EC SMBUS Pin mode */
#define	PCIE_OUR4_EN_EC_SMBUS_PIN				BIT_11			
/* Enable PCIe RX Overflow Status */
#define	PCIE_OUR4_EN_PCIE_RX_OVERFLOW			BIT_10			
/* Enable ASPM at No-D0 mode */
#define	PCIE_OUR4_EN_ASPM_NOND0					BIT_9			
/* Enable Pin #63 as LED_LINK */
#define	PCIE_OUR4_EN_LED_LINK_PIN63				BIT_8			
/* Force ASPM L1 Enable */
#define	PCIE_OUR4_FORCE_ASPM_L1_ENA				BIT_7			
/* Force ASPM L0s Enable */
#define	PCIE_OUR4_FORCE_ASPM_L0S_ENA			BIT_6			
/* Force CLKREQn Pin Low */
#define	PCIE_OUR4_FORCE_CLKREQN_PIN_LO			BIT_5			
/* Force CLKREQ Scheme Enable */
#define	PCIE_OUR4_FORCE_CLKREQ_SCHEME_ENA		BIT_4			
/* CLKREQn PAD Control */
#define	PCIE_OUR4_CLKREQN_PAD_CTRL				BIT_3			
#define	PCIE_OUR4_A1_MODE_SEL					BIT_2			/* A1 Mode Select */
/* Enable Gate Pexunit Clock */
#define	PCIE_OUR4_GATE_PEXUNIT_CLK_ENA			BIT_1			
/* Enable Gate Root Core Clock */
#define	PCIE_OUR4_GATE_ROOT_CORE_CLK_ENA		BIT_0			

/*	PCIE_OUR5				0x0088	Our Register 5 */
/*		Bit(s) PCIE_OUR5_RSRV_31 reserved */
/* Divide Core Clock Enable */
#define	PCIE_OUR5_DIV_CORE_CLK_ENA				BIT_31			
/* Soft Reset for Vmain_avlbl De-Glitch Logic */
#define	PCIE_OUR5_SOFT_RST_VMAIN_DEGLITCH		BIT_30			
/* Bypass Enable for Vmain_avlbl De-Glitch */
#define	PCIE_OUR5_BYPASS_VMAIN_DEGLITCH_ENA		BIT_29			
/* Timer of Vmain_avlbl De-Glitch */
#define	PCIE_OUR5_TIM_VMAIN_DEGLITCH_MSK		SHIFT27(0x3)	
#define	PCIE_OUR5_TIM_VMAIN_DEGLITCH_BASE		27
/* PCIe Reset De-Asserted Release Event */
#define	PCIE_OUR5_PCIE_RST_DEASS				BIT_26			
/* GPHY Received Packet Release Event */
#define	PCIE_OUR5_GPHY_RX_PKT					BIT_25			
/* Internal FIFO Not Empty Release Event */
#define	PCIE_OUR5_INT_FIFO_NOT_EMPTY			BIT_24			
/* Main Power is Available Release Event */
#define	PCIE_OUR5_MAIN_PWR_AVL					BIT_23			
/* CLKRUN Request Release Event */
#define	PCIE_OUR5_CLKRUN_REQ					BIT_22			
/* PCIe Reset Asserted Release Event */
#define	PCIE_OUR5_PCIE_RST_ASS					BIT_21			
/* PME Asserted Release Event */
#define	PCIE_OUR5_PME_ASS						BIT_20			
/* PCIe Exits L1 State Release Event */
#define	PCIE_OUR5_PCIE_EX_L1_STATE				BIT_19			
/* EPROM Loader Not Finished Release Event */
#define	PCIE_OUR5_EPROM_LDR_NOT_FIN				BIT_18			
/* PCIe RX Exits ELEC IDLE Release Event */
#define	PCIE_OUR5_PCIE_RX_EX_ELEC_IDLE			BIT_17			
/* GPHY Link Up Release Event */
#define	PCIE_OUR5_GPHY_LNK_UP					BIT_16			
/* CPU Goes to Sleep Release Event */
#define	PCIE_OUR5_CPU_SLEEP						BIT_15			
/* GPHY get INT Release Event */
#define	PCIE_OUR5_GPHY_INT						BIT_14			
/*		Bit(s) PCIE_OUR5_RSRV_13 reserved */
/* GPHY get INT Gate Event */
#define	PCIE_OUR5_GPHY_INT_EV					BIT_12			
/* CPU Goes to Sleep and Events Gate Event */
#define	PCIE_OUR5_CPU_SLEEP_EV					BIT_11			
/* PCIe Reset Asserted and Events Gate Event */
#define	PCIE_OUR5_PCIE_RST_ASS_EV				BIT_10			
/* GPHY Not Received Packet Gate Event */
#define	PCIE_OUR5_GPHY_NOT_RX_PKT				BIT_9			
/* Internal FIFO Empty Gate Event */
#define	PCIE_OUR5_INTERNAL_FIFO_EMPTY			BIT_8			
/* Main Power is Not Available Gate Event */
#define	PCIE_OUR5_MAIN_PWR_NOT_AVL				BIT_7			
/* CLKRUN Not Requested Gate Event */
#define	PCIE_OUR5_CLKRUN_NOT_REQ				BIT_6			
/* PCIe Reset De-Asserted and Events Gate Event */
#define	PCIE_OUR5_PCIE_RST_DEASS_EV				BIT_5			
/* PME De-Asserted Gate Event */
#define	PCIE_OUR5_PME_DEASS						BIT_4			
/* PCIe Goes to L1 State Gate Event */
#define	PCIE_OUR5_PCIE_GO_L1_STATE				BIT_3			
/* EPROM Loader Finished Gate Event */
#define	PCIE_OUR5_EPROM_LDR_FIN					BIT_2			
/* PCIe Rx ELEC IDLE Gate Event */
#define	PCIE_OUR5_PCIE_RX_ELEC_IDLE				BIT_1			
/* GPHY Link Down Gate Event */
#define	PCIE_OUR5_GPHY_LNK_DOWN					BIT_0			

/*	PCIE_ER_MASK			0x008C	Error Reporting Mask Register */
/* Enable the Device Feature Set SERR */
#define	PCIE_ER_MASK_DEV_FEAT_SET_SERR_ENA		BIT_31			
/* Receiver Error Mask */
#define	PCIE_ER_MASK_RCV_ERR_MASK				BIT_30			
/*		Bit(s) PCIE_ER_MASK_RSRV_29_28 reserved */
/* Enable Uncorrectable Error (UR Error) */
#define	PCIE_ER_MASK_UR_ENA						BIT_27			
/* Enable Uncorrectable Error (ECRC Error) */
#define	PCIE_ER_MASK_ECRCERR_ENA				BIT_26			
/* Enable Uncorrectable Error (Malformed TLP) */
#define	PCIE_ER_MASK_MTLP_ENA					BIT_25			
/* Enable Uncorrectable Error (RX Overflow) */
#define	PCIE_ER_MASK_RCVOVFL_ENA				BIT_24			
/* Enable Uncorrectable Error (Unexpected Completion) */
#define	PCIE_ER_MASK_UNEXPCPL_ENA				BIT_23			
/* Enable Uncorrectable Error (Completer Abort) */
#define	PCIE_ER_MASK_CPLABRT_ENA				BIT_22			
/* Enable Uncorrectable Error (Completion Timeout) */
#define	PCIE_ER_MASK_CPLTO_ENA					BIT_21			
/* Enable Uncorrectable Error (Flow Control Protocol Error) */
#define	PCIE_ER_MASK_FCPROTERR_ENA				BIT_20			
/* Enable Uncorrectable Error (Poisoned TLP) */
#define	PCIE_ER_MASK_PTLP_ENA					BIT_19			
/* Enable Uncorrectable Error (Data Link Protocol Error) */
#define	PCIE_ER_MASK_DLPRTERR_ENA				BIT_18			
/* Enable Uncorrectable Error (Training Error) */
#define	PCIE_ER_MASK_TRAINERR_ENA				BIT_17			
/*		Bit(s) PCIE_ER_MASK_RSRV_16 reserved */
/* Enable Uncorrectable Error (UR Error) Send Error Message */
#define	PCIE_ER_MASK_UR_SEND_ENA				BIT_15			
/* Enable Uncorrectable Error (ECRC Error) Send Error Message */
#define	PCIE_ER_MASK_ECRCERR_SEND_ENA			BIT_14			
/* Enable Uncorrectable Error (Malformed TLP) Send Error Message */
#define	PCIE_ER_MASK_MTLP_SEND_ENA				BIT_13			
/* Enable Uncorrectable Error (RX Overflow) Send Error Message */
#define	PCIE_ER_MASK_RCVOVFL_SEND_ENA			BIT_12			
/* Enable Uncorrectable Error (Unexpected Completion) Send Error Message */
#define	PCIE_ER_MASK_CPLUC_SEND_ENA				BIT_11			
/* Enable Uncorrectable Error (Completer Abort) Send Error Message */
#define	PCIE_ER_MASK_CPLABRT_SEND_ENA			BIT_10			
/* Enable Uncorrectable Error (Completion Timeout) Send Error Message */
#define	PCIE_ER_MASK_CPLTO_SEND_ENA				BIT_9			
/* Enable Uncorrectable Error (Flow Control Protocol Error) Send Error Message */
#define	PCIE_ER_MASK_FCPROTERR_SEND_ENA			BIT_8			
/* Enable Uncorrectable Error (Poisoned TLP) Send Error Message */
#define	PCIE_ER_MASK_PTLP_SEND_ENA				BIT_7			
/* Enable Uncorrectable Error (Data Link Protocol Error) Send Error Message */
#define	PCIE_ER_MASK_DLPRTERR_SEND_ENA			BIT_6			
/* Enable Uncorrectable Error (Training Error) Send Error Message */
#define	PCIE_ER_MASK_TRAINERR_SEND_ENA			BIT_5			
/* Enable Correctable Error (Replay Timer Timeout) Send Error Message */
#define	PCIE_ER_MASK_RPLYTO_SEND_ENA			BIT_4			
/* Enable Correctable Error (REPLAY_NUM RollOver) Send Error Message */
#define	PCIE_ER_MASK_RPLYNUMRO_SEND_ENA			BIT_3			
/* Enable Correctable Error (Bad DLLP) Send Error Message */
#define	PCIE_ER_MASK_BADDLLP_SEND_ENA			BIT_2			
/* Enable Correctable Error (Bad TLP) Send Error Message */
#define	PCIE_ER_MASK_BADTLP_SEND_ENA			BIT_1			
/* Enable Correctable Error (RX Error) Send Error Message */
#define	PCIE_ER_MASK_RXERR_SEND_ENA				BIT_0			

/*	CONFIG_REG0				0x0090	Config Register 0 */
#define	CONFIG_REG0_RTC_MSK							SHIFT24(0xff)	/* RTC Timing */
#define	CONFIG_REG0_RTC_BASE						24
#define	CONFIG_REG0_WTC_MSK							SHIFT16(0xff)	/* WTC Timing */
#define	CONFIG_REG0_WTC_BASE						16
/* Disable PCIe Reset Extend after Lom_disable */
#define	CONFIG_REG0_PCIRST_LOM						BIT_15			
/* Enable CPU Fast INT to Clock Gating */
#define	CONFIG_REG0_CLK_GATE_CPU_INT				BIT_14			
/* Enable Clock Free Running for ASF Subsystem */
#define	CONFIG_REG0_CLK_RUN_ASF						BIT_13			/* Yukon-Supreme */
/* Enable clock free running for Flash subsystem */
#define	CONFIG_REG0_CLK_RUN_FLASH					BIT_12			/* Yukon-Supreme */
/* Random Generator Speed Control */			
#define	CONFIG_REG0_OSC_PU							BIT_12			/* OSC Power Up */
/* OSC Speed Control */
#define	CONFIG_REG0_OSC_SPEED_CTRL_MSK				SHIFT9(0x7)		
#define	CONFIG_REG0_OSC_SPEED_CTRL_BASE				BIT_9
#define	CONFIG_REG0_OSC_OUT							BIT_8			/* OSC output */
/* Random Generator output */
#define	CONFIG_REG0_RNDG_OUT						BIT_8			
/*		Bit(s) CONFIG_REG0_RSRV_7 reserved */
#define	CONFIG_REG0_YTB_ARB_MODE_MSK				SHIFT5(0x3)		/* YTB ARB Mode */
#define	CONFIG_REG0_YTB_ARB_MODE_BASE				5
/* Disable GPHY Reset on Lom_disable Mode */
#define	CONFIG_REG0_GPHY_RST_LOMDISABLE				BIT_4			
/* Disable GPHY DPLL Reset on Lom_disable Mode */
#define	CONFIG_REG0_GPHY_RST_DPLL_LOMDISABLE		BIT_3			
/* Disable GPHY DPLL Power Down on Lom_disable Mode */
#define	CONFIG_REG0_GPHY_PD_DPLL_LOMDISABLE			BIT_2			
/* Enable GPHY PD on Lom_disable Mode */
#define	CONFIG_REG0_GPHY_PD_LOMDISABLE				BIT_1			
/* <mu>C Lock VPD */
#define	CONFIG_REG0_CPU_LOCK_VPD					BIT_0			

/*	CONFIG_REG1				0x0094	Config Register 1 */
/* Testmode Enable */
#define	CONFIG_REG1_EN_TESTMODE						BIT_31			
/* Testmode Select */
#define	CONFIG_REG1_TESTMODE_SEL_MSK				SHIFT28(0x7)	
#define	CONFIG_REG1_TESTMODE_SEL_BASE				28
/*		Bit(s) CONFIG_REG1_RSRV_27 reserved */
/* USB RESUME Release Clock Event */
#define	CONFIG_REG1_USB_RESUME_RELEASE_CLK			BIT_26			
/* USB RESUME Gate Clock Event */
#define	CONFIG_REG1_USB_RESUME_GATE_CLK				BIT_25			
/* Disable Release Event in Our Register 4 during PCIe Reset Asserted */
#define	CONFIG_REG1_DIS_CFG84_EVENT					BIT_24			
/* EPROM Loader Not Finished Release Event */
#define	CONFIG_REG1_EPROM_LDR_NOT_FIN_RELEASE		BIT_23			
/* Vmain_avlbl Release Gated Clock Release Event */
#define	CONFIG_REG1_VMAIN_AVLB_RELEASE				BIT_22			
/* PCIe Reset Release Gated Clock Release Event */
#define	CONFIG_REG1_PCIE_RST_RELEASE				BIT_21			
/* EPROM Loader Finished Gate Event */
#define	CONFIG_REG1_EPROM_LDR_FIN					BIT_20			
/* PCI Express Rx Electrical IDLE Gate Event */
#define	CONFIG_REG1_PCIE_RX_ELEC_IDLE				BIT_19			
/* PCIe Reset Assert Gate Event */
#define	CONFIG_REG1_PCIE_RST						BIT_18			
/* Enable PCIe Reset and pm2phy_off Generate CLKREQ for Auto-Gated Clock */
#define	CONFIG_REG1_EN_PERST_PMOFF_CLKREQ			BIT_17			
/* Enable PCIe Reset Generate CLKREQ for Auto-Gated Clock */
#define	CONFIG_REG1_EN_PERST_CLKREQ					BIT_16			
/*		Bit(s) CONFIG_REG1_RSRV_15_9 reserved */
/* Enable Core Level Config Loader Done for Gated Clock */
#define	CONFIG_REG1_EN_CFG_LOAD_DONE				BIT_8			
/* Enable PCIe Header Log Fix */
#define	CONFIG_REG1_ENA_PCIE_HDRLOG_FIX				BIT_7			
/* Enable PCIe CRS Fix */
#define	CONFIG_REG1_EN_PCIE_CRS_FIX					BIT_6			
/* FIFO Clock Duty Cycle Control */
#define	CONFIG_REG1_FIFO_CLK_DUTY_CYC_CTRL			BIT_5			
/* Disable pexunit Synchronization Fix */
#define	CONFIG_REG1_DIS_PEX_SYNC_FIX				BIT_4			
/* Enable CPU Reset Gated by YTB cmd */
#define	CONFIG_REG1_EN_CPU_RST_YTB_CMD				BIT_3			
/* Disable PCIe 2.0 Linkup Fix */
#define	CONFIG_REG1_DIS_PCIE20_LINKUP_FIX			BIT_2