mvyexhw.h

这是Marvell Technology Group Ltd. 4355 (rev 12)网卡在linux下的驱动程序源代码

												 */
#define	PCIE_PL_STAT					0x0214	/* 32 bit	PE Physical Layer
												 *			Status Register
												 */
#define	PCIE_CPLTO						0x0220	/* 32 bit	PE Completion
												 *			Timeout Register
												 */
#define	PCIE_FC							0x0224	/* 32 bit	PE Flow Control
												 *			Register
												 */
#define	PCIE_ACKTIM_X1					0x0228	/* 32 bit	PE Ack Timer for 1x
												 *			Link Register
												 */

/*
 *
 *	THE BIT DEFINES
 *
 */
/*	PCI_VEN_ID				0x0000	Vendor ID Register */
#define	PCI_VEN_ID_MSK		SHIFT0(0xffffU)	/* Vendor ID */
#define	PCI_VEN_ID_BASE		0

/*	PCI_DEV_ID				0x0002	Device ID Register */
#define	PCI_DEV_ID_MSK		SHIFT0(0xffffU)	/* Device ID */
#define	PCI_DEV_ID_BASE		0

/*	PCI_CMD					0x0004	Command Register */
/*		Bit(s) PCI_CMD_RSRV_15_11 reserved */
#define	PCI_CMD_INT_DIS				BIT_10S			/* Interrupt Disable */
/*		Bit(s) PCI_CMD_RSRV_9 reserved */
#define	PCI_CMD_SERR_ENA			BIT_8S			/* SERR Enable */
/*		Bit(s) PCI_CMD_RSRV_7 reserved */
#define	PCI_CMD_PERREN				BIT_6S			/* Parity Error Response */
/*		Bit(s) PCI_CMD_RSRV_5_3 reserved */
#define	PCI_CMD_BMEN				BIT_2S			/* Bus Master Enable */
#define	PCI_CMD_MEMEN				BIT_1S			/* Memory Space Access Enable */
#define	PCI_CMD_IOEN				BIT_0S			/* I/O Space Access Enable */

/*	PCI_STAT				0x0006	Status Register */
#define	PCI_STAT_PERR				BIT_15S			/* Parity Error */
#define	PCI_STAT_SERR				BIT_14S			/* Signaled SERRn */
#define	PCI_STAT_RMABORT			BIT_13S			/* Received Master Abort */
#define	PCI_STAT_RTABORT			BIT_12S			/* Received Target Abort */
/*		Bit(s) PCI_STAT_RSRV_11_9 reserved */
#define	PCI_STAT_DATAPERR			BIT_8S			/* Data Parity Error Detected */
/*		Bit(s) PCI_STAT_RSRV_7_5 reserved */
#define	PCI_STAT_NEWCAP				BIT_4S			/* New Capabilities Bit */
#define	PCI_STAT_INTSTA				BIT_3S			/* Interrupt Message Pending */
/*		Bit(s) PCI_STAT_RSRV_2_0 reserved */

/*	PCI_REV_ID				0x0008	Revision ID Register */
#define	PCI_REV_ID_MSK		SHIFT0(0xffU)	/* Revision ID */
#define	PCI_REV_ID_BASE		0

/*	PCI_PIF					0x0009	Programming Interface Register, Lower Byte */
#define	PCI_PIF_MSK			SHIFT0(0xffU)	/* Prog Interface */
#define	PCI_PIF_BASE		0

/*	PCI_SCC					0x000A	Sub-Class Register, Middle Byte */
#define	PCI_SCC_MSK			SHIFT0(0xffU)	/* Sub Class */
#define	PCI_SCC_BASE		0

/*	PCI_BCC					0x000B	Base-Class Register, Upper Byte */
#define	PCI_BCC_MSK			SHIFT0(0xffU)	/* Base Class */
#define	PCI_BCC_BASE		0

/*	PCI_CLS					0x000C	Cache Line Size Register */
/*		Bit(s) PCI_CLS_RSRV_7_0 reserved */

/*	PCI_LAT_TIM				0x000D	Latency Timer Register */
/*		Bit(s) PCI_LAT_TIM_RSRV_7_0 reserved */

/*	PCI_HDRTYP				0x000E	Header Type Register */
/*		Bit(s) PCI_HDRTYP_RSRV_7_0 reserved */

/*	PCI_BIST				0x000F	Built-in Self Test (BIST) Register */
/*		Bit(s) PCI_BIST_RSRV_7_0 reserved */

/*	PCI_BAR1_LO				0x0010	Base Address Register (1st), Lower Address */
#define	PCI_BAR1_LO_BASE_MSK		SHIFT14(0x3ffff)	/* Lower MEMBASE Address */
#define	PCI_BAR1_LO_BASE_BASE		14
#define	PCI_BAR1_LO_SIZE_MSK		SHIFT4(0x3ff)		/* Memory Size Requirements */
#define	PCI_BAR1_LO_SIZE_BASE		4
#define	PCI_BAR1_LO_PREFEN			BIT_3				/* Prefetch Enable */
#define	PCI_BAR1_LO_TYPE_MSK		SHIFT1(0x3)			/* Memory Type */
#define	PCI_BAR1_LO_TYPE_BASE		1
#define	PCI_BAR1_LO_IO_SPC			BIT_0				/* Memory Space Indicator */

/*	PCI_BAR1_HI				0x0014	Base Address Register (1st), Upper Address */
#define	PCI_BAR1_HI_BASE_MSK		SHIFT0(0xffffffff)	/* Upper MEMBASE */
#define	PCI_BAR1_HI_BASE_BASE		0

/*	PCI_BAR2				0x0018	Base Address Register (2nd) */
#define	PCI_BAR2_BASE_MSK		SHIFT8(0xffffff)	/* I/O Base Address MSb */
#define	PCI_BAR2_BASE_BASE		8
#define	PCI_BAR2_SIZE_MSK		SHIFT2(0x3f)		/* I/O Size Requirements */
#define	PCI_BAR2_SIZE_BASE		2
/*		Bit(s) PCI_BAR2_RSRV_1 reserved */
#define	PCI_BAR2_IO_SPC			BIT_0				/* I/O Space Indicator */

/*	PCI_SSVEN_ID			0x002C	Subsystem Vendor ID Register */
#define	PCI_SSVEN_ID_MSK		SHIFT0(0xffffU)	/* Subsystem Vendor ID */
#define	PCI_SSVEN_ID_BASE		0

/*	PCI_SSDEV_ID			0x002E	Subsystem ID Register */
#define	PCI_SSDEV_ID_MSK		SHIFT0(0xffffU)	/* Subsystem ID */
#define	PCI_SSDEV_ID_BASE		0

/*	PCI_ERBAR				0x0030	Expansion Rom Base Address Register */
#define	PCI_ERBAR_BASE_MSK				SHIFT17(0x7fff)	/* ROM Base Address MSb */
#define	PCI_ERBAR_BASE_BASE				17
#define	PCI_ERBAR_BASE_SIZE_MSK			SHIFT14(0x7)	/* Rombase/size */
#define	PCI_ERBAR_BASE_SIZE_BASE		14
#define	PCI_ERBAR_SIZE_MSK				SHIFT11(0x7)	/* ROM Size Requirements */
#define	PCI_ERBAR_SIZE_BASE				11
/*		Bit(s) PCI_ERBAR_RSRV_10_1 reserved */
#define	PCI_ERBAR_ENA					BIT_0			/* Address Decode Enable */

/*	PCI_NCAP_PTR			0x0034	New Capabilities Pointer (New Cap Ptr)
 *									Register
 */
#define	PCI_NCAP_PTR_MSK		SHIFT0(0xffU)	/* New Capabilities Pointer */
#define	PCI_NCAP_PTR_BASE		0

/*	PCI_INT_LINE			0x003C	Interrupt Line Register */
#define	PCI_INT_LINE_MSK		SHIFT0(0xffU)	/* Interrupt Line */
#define	PCI_INT_LINE_BASE		0

/*	PCI_INT_PIN				0x003D	Interrupt Pin Register */
#define	PCI_INT_PIN_MSK			SHIFT0(0xffU)	/* Interrupt Pin */
#define	PCI_INT_PIN_BASE		0

/*	PCI_MIN_GNT				0x003E	Min_Gnt Register */
/*		Bit(s) PCI_MIN_GNT_RSRV_7_0 reserved */

/*	PCI_MAX_LAT				0x003F	Max_Lat Register */
/*		Bit(s) PCI_MAX_LAT_RSRV_7_0 reserved */

/*	PCI_OUR1				0x0040	Our Register 1 */
/*		Bit(s) PCI_OUR1_RSRV_31 reserved */
#define	PCI_OUR1_SW_POR					BIT_30			/* Software Power-on-reset */
/* Enable Generation Preset during Software POR */
#define	PCI_OUR1_EN_GEN_PRSET			BIT_29			
#define	PCI_OUR1_GP_COMA				BIT_28			/* Set PHY to Coma Mode */
#define	PCI_OUR1_DIS_SPI_LOAD			BIT_27			/* Disable SPI Loader */
#define	PCI_OUR1_GP_PWD					BIT_26			/* PHY Power Down Mode */
#define	PCI_OUR1_DIS_VPD_LOAD			BIT_25			/* Disable VPD Loader */
#define	PCI_OUR1_ENBOOT					BIT_24			/* Enable Boot */
#define	PCI_OUR1_ENIOMAP				BIT_23			/* Enable I/O Mapping */
#define	PCI_OUR1_ENEPROM				BIT_22			/* Enable Eprom */
/* Pagesize[1:0]/SPI Flash Memory */
#define	PCI_OUR1_PAGE_SIZ_MSK			SHIFT20(0x3)	
#define	PCI_OUR1_PAGE_SIZ_BASE			20
                                                        /* Yukon-Supreme */
#define	PCI_OUR1_ROM_SRC_SEL			BIT_19			/* ROM Source Select */
#define	PCI_OUR1_PAGE_SEL_MSK			SHIFT16(0x7)	/* Page Register[2:0] */
#define	PCI_OUR1_PAGE_SEL_BASE			16
#define	PCI_OUR1_DBG_PEX_PME			BIT_15			/* Debug PCI Express PME */
/*		Bit(s) PCI_OUR1_RSRV_14_10 reserved */
/* Timer for GPHY Link Trigger */
#define	PCI_OUR1_GP_TRIG_TIM_MSK		SHIFT8(0x3)		
#define	PCI_OUR1_GP_TRIG_TIM_BASE		8
#define	PCI_OUR1_L1_EVT_ENA				BIT_7			/* L1 Event Enable */
#define	PCI_OUR1_GP_LNK_ENA				BIT_6			/* Enable GPHY Link */
#define	PCI_OUR1_FORCE_L1				BIT_5			/* Force to L1 */
/*		Bit(s) PCI_OUR1_RSRV_4_1 reserved */
/* PCIe Receiver Overflow Control */
#define	PCI_OUR1_PEX_RX_OF_CTRL			BIT_0			

/*	PCI_OUR2				0x0044	Our Register 2 */
/*		Bit(s) PCI_OUR2_RSRV_31_24 reserved */
#define	PCI_OUR2_VPD_DEVSEL_MSK			SHIFT17(0x7f)	/* VPD Devsel */
#define	PCI_OUR2_VPD_DEVSEL_BASE		17
#define	PCI_OUR2_VPD_ROMSIZE_MSK		SHIFT14(0x7)	/* VPD ROM Size */
#define	PCI_OUR2_VPD_ROMSIZE_BASE		14
/*		Bit(s) PCI_OUR2_RSRV_13_0 reserved */

/*	PCI_PM_CAP_ID			0x0048	Power Management Capability ID Register
 *									(PM Cap ID)
 */
#define	PCI_PM_CAP_ID_MSK		SHIFT0(0xffU)	/* Power Management Capabilities ID */
#define	PCI_PM_CAP_ID_BASE		0

/*	PCI_PM_NXT_PTR			0x0049	Power Management Next Item Pointer Register */
#define	PCI_PM_NXT_PTR_MSK		SHIFT0(0xffU)	/* Next Item Pointer */
#define	PCI_PM_NXT_PTR_BASE		0

/*	PCI_PM_CAP				0x004A	Power Management Capabilities Register */
/* D3 Cold Power Management Event Support */
#define	PCI_PM_CAP_D3C_ENA				BIT_15S			
/* D3 Hot Power Management Event Support */
#define	PCI_PM_CAP_D3H_ENA				BIT_14S			
/* D2 Power Management Event Support */
#define	PCI_PM_CAP_D2_ENA				BIT_13S			
/* D1 Power Management Event Support */
#define	PCI_PM_CAP_D1_ENA				BIT_12S			
/* D0 Power Management Event Support */
#define	PCI_PM_CAP_D0_ENA				BIT_11S			
#define	PCI_PM_CAP_D2_SUP				BIT_10S			/* D2 Support */
#define	PCI_PM_CAP_D1_SUP				BIT_9S			/* D1 Support */
/*		Bit(s) PCI_PM_CAP_RSRV_8_6 reserved */
/* Device Specific Initialization */
#define	PCI_PM_CAP_DSI_ENA				BIT_5S			
/*		Bit(s) PCI_PM_CAP_RSRV_4_3 reserved */
#define	PCI_PM_CAP_VER_ID_MSK			SHIFT0(0x7U)	/* Version */
#define	PCI_PM_CAP_VER_ID_BASE			0

/*	PCI_PM_CSR				0x004C	Power Management Control/Status Register */
#define	PCI_PM_CSR_PME_STAT				BIT_15S			/* PME Status */
#define	PCI_PM_CSR_D_SCALE_MSK			SHIFT13(0x3U)	/* Data Scale */
#define	PCI_PM_CSR_D_SCALE_BASE			13
#define	PCI_PM_CSR_D_SEL_MSK			SHIFT9(0xfU)	/* Data Select */
#define	PCI_PM_CSR_D_SEL_BASE			9
#define	PCI_PM_CSR_PMEEN				BIT_8S			/* PME En */
/*		Bit(s) PCI_PM_CSR_RSRV_7_2 reserved */
#define	PCI_PM_CSR_PWST_MSK				SHIFT0(0x3U)	/* Power State */
#define	PCI_PM_CSR_PWST_BASE			0

/*	PCI_PM_DATA				0x004F	Power Management Data Register */
#define	PCI_PM_DATA_MSK			SHIFT0(0xffU)	/* Data */
#define	PCI_PM_DATA_BASE		0

/*	PCI_VPD_CAP_ID			0x0050	VPD Capability ID Register (VPD Cap ID) */
#define	PCI_VPD_CAP_ID_MSK		SHIFT0(0xffU)	/* VPD Capabilities ID */
#define	PCI_VPD_CAP_ID_BASE		0

/*	PCI_VPD_NPTR			0x0051	VPD Next Item Pointer Register */
#define	PCI_VPD_NPTR_MSK		SHIFT0(0xffU)	/* Next Item Pointer */
#define	PCI_VPD_NPTR_BASE		0

/*	PCI_VPD_ADDR			0x0052	VPD Address Register */
#define	PCI_VPD_ADDR_FLAG		BIT_15S			/* Flag */
#define	PCI_VPD_ADDR_MSK		SHIFT0(0x7fffU)	/* VPD Address */
#define	PCI_VPD_ADDR_BASE		0

/*	PCI_VPD_DATA			0x0054	VPD Data Register */
#define	PCI_VPD_DATA_MSK		SHIFT0(0xffffffff)	/* VPD Data */
#define	PCI_VPD_DATA_BASE		0

/*	PCI_LDR_CTRL			0x0058	TWSI EEPROM Loader Control Register */
#define	PCI_LDR_CTRL_FLAG				BIT_31			/* Flag */
/* TWSI EEPROM Loader Address */
#define	PCI_LDR_CTRL_ADDR_TWSI_MSK		SHIFT16(0x7fff)	
#define	PCI_LDR_CTRL_ADDR_TWSI_BASE		16
/* EEPROM Loader Start Address for PCI Loader */
#define	PCI_LDR_CTRL_ADDR_PCI_MSK		SHIFT8(0xff)	
#define	PCI_LDR_CTRL_ADDR_PCI_BASE		8
/* EEPROM loader start Address for PiG */
#define	PCI_LDR_CTRL_ADDR_PIG_MSK		SHIFT0(0xff)	
#define	PCI_LDR_CTRL_ADDR_PIG_BASE		0

/*	PCI_MSI_CAP_ID			0x005C	MSI Capability ID Register (MSI Cap ID) */
#define	PCI_MSI_CAP_ID_MSK		SHIFT0(0xffU)	/* MSI Capabilities ID */
#define	PCI_MSI_CAP_ID_BASE		0

/*	PCI_MSI_NPTR			0x005D	MSI Next Item Pointer Register */
#define	PCI_MSI_NPTR_MSK		SHIFT0(0xffU)	/* Next Item Pointer */
#define	PCI_MSI_NPTR_BASE		0

/*	PCI_MSI_CTRL			0x005E	MSI Message Control Register */
/*		Bit(s) PCI_MSI_CTRL_RSRV_15_8 reserved */
#define	PCI_MSI_CTRL_64CAP				BIT_7S			/* 64-bit Address Capable */
#define	PCI_MSI_CTRL_MM_ENA_MSK			SHIFT4(0x7U)	/* Multiple Message Enable */
#define	PCI_MSI_CTRL_MM_ENA_BASE		4
#define	PCI_MSI_CTRL_MM_CAP_MSK			SHIFT1(0x7U)	/* Multiple Message Capable */
#define	PCI_MSI_CTRL_MM_CAP_BASE		1
#define	PCI_MSI_CTRL_ENA				BIT_0S			/* MSI Enable */

/*	PCI_MSI_ADDR_LO			0x0060	MSI Message Address Register, Lower Address */
/* MSI Message Address, Lower Address */
#define	PCI_MSI_ADDR_LO_MSK					SHIFT2(0x3fffffff)	
#define	PCI_MSI_ADDR_LO_BASE				2
/*		Bit(s) PCI_MSI_ADDR_LO_RSRV_1_0 reserved */

/*	PCI_MSI_ADDR_HI			0x0064	MSI Message Address Register, Upper Address */
/* MSI Message Address, Upper Address */
#define	PCI_MSI_ADDR_HI_MSK			SHIFT0(0xffffffff)	
#define	PCI_MSI_ADDR_HI_BASE		0

/*	PCI_MSI_DATA			0x0068	MSI Message Data Register */
/*		Bit(s) PCI_MSI_DATA_RSRV_31_16 reserved */
#define	PCI_MSI_DATA_MSK					SHIFT0(0xffff)	/* Message Data */
#define	PCI_MSI_DATA_BASE					0

/*	PCIE_STAT				0x0070	PCI Express Status Register */
/*		Bit(s) PCIE_STAT_RSRV_31_30 reserved */
#define	PCIE_STAT_FIX_MSK				SHIFT16(0x3fff)	/* Fixed Value */
#define	PCIE_STAT_FIX_BASE				16
#define	PCIE_STAT_BUS_NUM_MSK			SHIFT8(0xff)	/* Request ID (Bus Number) */
#define	PCIE_STAT_BUS_NUM_BASE			8
/* Request ID (Device Number) */
#define	PCIE_STAT_DEV_NUM_MSK			SHIFT3(0x1f)	
#define	PCIE_STAT_DEV_NUM_BASE			3
/* Request ID (Function Number) */
#define	PCIE_STAT_FUN_NUM_MSK			SHIFT0(0x7)		
#define	PCIE_STAT_FUN_NUM_BASE			0

/*	PCIE_OUR_STAT			0x007C	Our Status Register */
/*		Bit(s) PCIE_OUR_STAT_RSRV_31_26 reserved */
/* DLL Error Status Indication */
#define	PCIE_OUR_STAT_DLL_ERR_MSK			SHIFT24(0x3)	
#define	PCIE_OUR_STAT_DLL_ERR_BASE			24
/* DLL Row Counters Values */
#define	PCIE_OUR_STAT_DLL_ROW_MSK			SHIFT20(0xf)	
#define	PCIE_OUR_STAT_DLL_ROW_BASE			20
/* DLL Column Counters Values */
#define	PCIE_OUR_STAT_DLL_COL_MSK			SHIFT16(0xf)	
#define	PCIE_OUR_STAT_DLL_COL_BASE			16
/*		Bit(s) PCIE_OUR_STAT_RSRV_15_0 reserved */