📄 mvyexhw.h
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/****************************************************************************** * * Name: mvyexhw.h * Project: Yukon Extreme, Common Modules * Version: $Revision: 1.6 $ * Date: $Date: 2008/01/21 09:58:13 $ * Purpose: Defines and Macros for the Yukon Extreme Gigabit Ethernet Adapters * ******************************************************************************//****************************************************************************** * * LICENSE: * (C)Copyright Marvell. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * The information in this file is provided "AS IS" without warranty. * /LICENSE * ******************************************************************************//****************************************************************************** * * This file was automatically generated by reg.pl (Rev. 1.55) using * Yukon_Extreme_Registers_Config.csv * Yukon_Extreme_Registers_Control.csv * Yukon_Extreme_Registers_GMAC.csv * ******************************************************************************/#ifndef __INC_MVYEXHW_H#define __INC_MVYEXHW_H#define PCI_VEN_ID 0x0000 /* 16 bit Vendor ID Register */#define PCI_DEV_ID 0x0002 /* 16 bit Device ID Register */#define PCI_CMD 0x0004 /* 16 bit Command Register */#define PCI_STAT 0x0006 /* 16 bit Status Register *///#define PCI_REV_ID 0x0008 /* 8 bit Revision ID Register */#define PCI_PIF 0x0009 /* 8 bit Programming * Interface * Register, Lower * Byte */#define PCI_SCC 0x000A /* 8 bit Sub-Class Register, * Middle Byte */#define PCI_BCC 0x000B /* 8 bit Base-Class * Register, Upper * Byte */#define PCI_CLS 0x000C /* 8 bit Cache Line Size * Register *///#define PCI_LAT_TIM 0x000D /* 8 bit Latency Timer// * Register// */#define PCI_HDRTYP 0x000E /* 8 bit Header Type Register *///#define PCI_BIST 0x000F /* 8 bit Built-in Self Test// * (BIST) Register// */#define PCI_BAR1_LO 0x0010 /* 32 bit Base Address * Register (1st), * Lower Address */#define PCI_BAR1_HI 0x0014 /* 32 bit Base Address * Register (1st), * Upper Address */#define PCI_BAR2 0x0018 /* 32 bit Base Address * Register (2nd) */#define PCI_SSVEN_ID 0x002C /* 16 bit Subsystem Vendor ID * Register */#define PCI_SSDEV_ID 0x002E /* 16 bit Subsystem ID * Register */#define PCI_ERBAR 0x0030 /* 32 bit Expansion Rom Base * Address Register */#define PCI_NCAP_PTR 0x0034 /* 8 bit New Capabilities * Pointer (New Cap * Ptr) Register */#define PCI_INT_LINE 0x003C /* 8 bit Interrupt Line * Register */#define PCI_INT_PIN 0x003D /* 8 bit Interrupt Pin * Register *///#define PCI_MIN_GNT 0x003E /* 8 bit Min_Gnt Register *///#define PCI_MAX_LAT 0x003F /* 8 bit Max_Lat Register */#define PCI_OUR1 0x0040 /* 32 bit Our Register 1 */#define PCI_OUR2 0x0044 /* 32 bit Our Register 2 *///#define PCI_PM_CAP_ID 0x0048 /* 8 bit Power Management// * Capability ID// * Register (PM Cap// * ID)// */#define PCI_PM_NXT_PTR 0x0049 /* 8 bit Power Management * Next Item Pointer * Register */#define PCI_PM_CAP 0x004A /* 16 bit Power Management * Capabilities * Register */#define PCI_PM_CSR 0x004C /* 16 bit Power Management * Control/Status * Register */#define PCI_PM_DATA 0x004F /* 8 bit Power Management * Data Register *///#define PCI_VPD_CAP_ID 0x0050 /* 8 bit VPD Capability ID// * Register (VPD Cap// * ID)// */#define PCI_VPD_NPTR 0x0051 /* 8 bit VPD Next Item * Pointer Register */#ifdef XXX /* Naming Conflict with Linux */#define PCI_VPD_ADDR 0x0052 /* 16 bit VPD Address Register */#define PCI_VPD_DATA 0x0054 /* 32 bit VPD Data Register */#endif /* XXX */#define PCI_LDR_CTRL 0x0058 /* 32 bit TWSI EEPROM Loader * Control Register *///#define PCI_MSI_CAP_ID 0x005C /* 8 bit MSI Capability ID// * Register (MSI Cap// * ID)// */#define PCI_MSI_NPTR 0x005D /* 8 bit MSI Next Item * Pointer Register *///#define PCI_MSI_CTRL 0x005E /* 16 bit MSI Message Control// * Register// */#define PCI_MSI_ADDR_LO 0x0060 /* 32 bit MSI Message Address * Register, Lower * Address */#define PCI_MSI_ADDR_HI 0x0064 /* 32 bit MSI Message Address * Register, Upper * Address *///#define PCI_MSI_DATA 0x0068 /* 32 bit MSI Message Data// * Register// */#define PCIE_STAT 0x0070 /* 32 bit PCI Express Status * Register */#define PCIE_OUR_STAT 0x007C /* 32 bit Our Status Register */#define PCIE_OUR3 0x0080 /* 32 bit Our Register 3 */#define PCIE_OUR4 0x0084 /* 32 bit Our Register 4 */#define PCIE_OUR5 0x0088 /* 32 bit Our Register 5 */#define PCIE_ER_MASK 0x008C /* 32 bit Error Reporting * Mask Register */#define CONFIG_REG0 0x0090 /* 32 bit Config Register 0 */#define CONFIG_REG1 0x0094 /* 32 bit Config Register 1 */#define PSM_CONFIG_REG0 0x0098 /* 32 bit PSM Config Register * 0 */#define PSM_CONFIG_REG1 0x009C /* 32 bit PSM Config Register * 1 */ /* Yukon-FE+ */#define VPD_CTRL_ADD 0x00A0 /* 32 bit VPD Start End * Address */ /* Yukon-FE+ */#define OTP_LDR_CTRL 0x00A4 /* 32 bit OTP Loader Control * Register */ /* Yukon-FE+ */#define OTP_MEM_CTRL_0 0x00A8 /* 32 bit OTP Memory Control * Register 0 */ /* Yukon-FE+ */#define OTP_MEM_CTRL_1 0x00AC /* 32 bit OTP Memory Control * Register 1 */ /* Yukon-FE+ */#define OTP_MEM_CTRL_2 0x00B0 /* 32 bit OTP Memory Control * Register 2 */ /* Yukon-FE+ */#define OTP_MEM_ST_0 0x00B4 /* 32 bit OTP Memory Status * Register 0 */ /* Yukon-FE+ */#define VPD_CTRL 0x00B8 /* 32 bit EEPROM and OTP * Control Register */ /* Yukon-Supreme */#define FLASH_LDR_CTRL 0x00A4 /* 32 bit Flash Loader */ /* Yukon-Supreme */#define LD_STATUS_0 0x00A8 /* 32 bit LOADER STATUS */ /* Yukon-Supreme */#define VPD_FLASH_CTRL 0x00B8 /* 32 bit EEPROM and Flash * Control Register */ /* Yukon-FE+ */#define OTP_MEM_CTRL_3 0x00BC /* 32 bit LDO Control Register */#define PCIE_CAP_ID 0x00C0 /* 8 bit PE Capability ID * Register (PM Cap * ID) */#define PCIE_NPTR 0x00C1 /* 8 bit PE Next Item * Pointer Register */#define PCIE_CAP 0x00C2 /* 16 bit PE Capabilities * Register */#define DEVICE_CAPABILITIES_REGISTER 0x00C4 /* 32 bit Device Capabilities * Register */#define PCIE_DEVCTRL 0x00C8 /* 16 bit Device Control * Register */#define PCIE_DEVSTAT 0x00CA /* 16 bit Device Status * Register */#define PCIE_LNKCAP 0x00CC /* 32 bit Link Capabilities * Register */#define PCIE_LNKCTRL 0x00D0 /* 16 bit Link Control * Register */#define PCIE_LNKSTAT 0x00D2 /* 16 bit Link Status Register */#define PCIE_DEV_CAP_2 0x00E4 /* 32 bit Device Capabilities * 2 Register */#define PCIE_DEV_CTRL_2 0x00E8 /* 32 bit Device Control 2 * Register */#define PCIE_AE_CAP_HDR 0x0100 /* 32 bit Advanced Error * Reporting * Enhanced * Capability Header * Register */#define PCIE_UE_STAT 0x0104 /* 32 bit Uncorrectable Error * Status Register */#define PCIE_UE_MASK 0x0108 /* 32 bit Uncorrectable Error * Mask Register */#define PCIE_UE_SVRT 0x010C /* 32 bit Uncorrectable Error * Severity Register */#define PCIE_CA_STAT 0x0110 /* 32 bit Correctable Error * Status Register */#define PCIE_CA_MASK 0x0114 /* 32 bit Correctable Error * Mask Register */#define PCIE_AE_CAPCTRL 0x0118 /* 32 bit Advanced Error * Capabilities and * Control Register */#define PCIE_HDRLOG_RNG_LO 0x011C /* Header Log Registers Start */#define PCIE_HDRLOG_RNG_HI 0x0128 /* Header Log Registers End */#define PCIE_DEVSERNUMCAP 0x0130 /* 32 bit Device Serial * Number Enhanced * Capability Header */#define PCIE_SERNUM_LOWDW 0x0134 /* 32 bit Serial Number * Register (Lower * DW) */#define PCIE_SERNUM_UPPDW 0x0138 /* 32 bit Serial Number * Register (Upper * DW) */#define PCIE_PWRBDGT_CAPHDR 0x0140 /* 32 bit Power Budgeting * Enhanced * Capability Header */#define PCIE_PWRBDGT_DATASEL 0x0144 /* 32 bit Power Budgeting * Data Select * Register */#define PCIE_PWRBDGT_DATA 0x0148 /* 32 bit Power Budgeting * Data Register */#define PCIE_PWRBDGT_CAP 0x014C /* 32 bit Power Budgeting * Capability * Register */#define PCIE_TL_CTRL 0x0200 /* 32 bit Transaction Layer * Control Register */#define PCIE_TL_STAT 0x0204 /* 32 bit Transaction Layer * Status Register */#define PCIE_DL_CTRL 0x0208 /* 32 bit Data Link Layer * Control Register */#define PCIE_DL_STAT 0x020C /* 32 bit Data Link Layer * Status Register */#define PCIE_PL_CTRL 0x0210 /* 32 bit PE Physical Layer * Control Register⌨️ 快捷键说明
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