xmac_ii.h

这是Marvell Technology Group Ltd. 4355 (rev 12)网卡在linux下的驱动程序源代码

 */
#define PHY_BCOM_CTRL		0x00	/* 16 bit r/w	PHY Control Register */
#define PHY_BCOM_STAT		0x01	/* 16 bit r/o	PHY Status Register */
#define PHY_BCOM_ID0		0x02	/* 16 bit r/o	PHY ID0 Register */
#define PHY_BCOM_ID1		0x03	/* 16 bit r/o	PHY ID1 Register */
#define PHY_BCOM_AUNE_ADV	0x04	/* 16 bit r/w	Auto-Neg. Advertisement */
#define PHY_BCOM_AUNE_LP	0x05	/* 16 bit r/o	Link Partner Ability Reg */
#define PHY_BCOM_AUNE_EXP	0x06	/* 16 bit r/o	Auto-Neg. Expansion Reg */
#define PHY_BCOM_NEPG		0x07	/* 16 bit r/w	Next Page Register */
#define PHY_BCOM_NEPG_LP	0x08	/* 16 bit r/o	Next Page Link Partner */
	/* Broadcom-specific registers */
#define PHY_BCOM_1000T_CTRL	0x09	/* 16 bit r/w	1000Base-T Control Reg */
#define PHY_BCOM_1000T_STAT	0x0a	/* 16 bit r/o	1000Base-T Status Reg */
	/* 0x0b - 0x0e:		reserved */
#define PHY_BCOM_EXT_STAT	0x0f	/* 16 bit r/o	Extended Status Reg */
#define PHY_BCOM_P_EXT_CTRL	0x10	/* 16 bit r/w	PHY Extended Ctrl Reg */
#define PHY_BCOM_P_EXT_STAT	0x11	/* 16 bit r/o	PHY Extended Stat Reg */
#define PHY_BCOM_RE_CTR		0x12	/* 16 bit r/w	Receive Error Counter */
#define PHY_BCOM_FC_CTR		0x13	/* 16 bit r/w	False Carrier Sense Cnt */
#define PHY_BCOM_RNO_CTR	0x14	/* 16 bit r/w	Receiver NOT_OK Cnt */
	/* 0x15 - 0x17:		reserved */
#define PHY_BCOM_AUX_CTRL	0x18	/* 16 bit r/w	Auxiliary Control Reg */
#define PHY_BCOM_AUX_STAT	0x19	/* 16 bit r/o	Auxiliary Stat Summary */
#define PHY_BCOM_INT_STAT	0x1a	/* 16 bit r/o	Interrupt Status Reg */
#define PHY_BCOM_INT_MASK	0x1b	/* 16 bit r/w	Interrupt Mask Reg */
	/* 0x1c:		reserved */
	/* 0x1d - 0x1f:		test registers */

/*----------------------------------------------------------------------------*/
/*
 * Marvell-PHY Registers, indirect addressed over GMAC
 */
#define PHY_MARV_CTRL		0x00	/* 16 bit r/w	PHY Control Register */
#define PHY_MARV_STAT		0x01	/* 16 bit r/o	PHY Status Register */
#define PHY_MARV_ID0		0x02	/* 16 bit r/o	PHY ID0 Register */
#define PHY_MARV_ID1		0x03	/* 16 bit r/o	PHY ID1 Register */
#define PHY_MARV_AUNE_ADV	0x04	/* 16 bit r/w	Auto-Neg. Advertisement */
#define PHY_MARV_AUNE_LP	0x05	/* 16 bit r/o	Link Partner Ability Reg */
#define PHY_MARV_AUNE_EXP	0x06	/* 16 bit r/o	Auto-Neg. Expansion Reg */
#define PHY_MARV_NEPG		0x07	/* 16 bit r/w	Next Page Register */
#define PHY_MARV_NEPG_LP	0x08	/* 16 bit r/o	Next Page Link Partner */
	/* Marvell-specific registers */
#define PHY_MARV_1000T_CTRL	0x09	/* 16 bit r/w	1000Base-T Control Reg */
#define PHY_MARV_1000T_STAT	0x0a	/* 16 bit r/o	1000Base-T Status Reg */
	/* 0x0b - 0x0e:		reserved */
#define PHY_MARV_EXT_STAT	0x0f	/* 16 bit r/o	Extended Status Reg */
#define PHY_MARV_PHY_CTRL	0x10	/* 16 bit r/w	PHY Specific Control Reg */
#define PHY_MARV_PHY_STAT	0x11	/* 16 bit r/o	PHY Specific Status Reg */
#define PHY_MARV_INT_MASK	0x12	/* 16 bit r/w	Interrupt Mask Reg */
#define PHY_MARV_INT_STAT	0x13	/* 16 bit r/o	Interrupt Status Reg */
#define PHY_MARV_EXT_CTRL	0x14	/* 16 bit r/w	Ext. PHY Specific Ctrl */
#define PHY_MARV_RXE_CNT	0x15	/* 16 bit r/w	Receive Error Counter */
#define PHY_MARV_EXT_ADR	0x16	/* 16 bit r/w	Ext. Ad. for Cable Diag. */
#define PHY_MARV_PORT_IRQ	0x17	/* 16 bit r/o	Port 0 IRQ (88E1111 only) */
#define PHY_MARV_LED_CTRL	0x18	/* 16 bit r/w	LED Control Reg */
#define PHY_MARV_LED_OVER	0x19	/* 16 bit r/w	Manual LED Override Reg */
#define PHY_MARV_EXT_CTRL_2	0x1a	/* 16 bit r/w	Ext. PHY Specific Ctrl 2 */
#define PHY_MARV_EXT_P_STAT	0x1b	/* 16 bit r/w	Ext. PHY Spec. Stat Reg */
#define PHY_MARV_CABLE_DIAG	0x1c	/* 16 bit r/o	Cable Diagnostic Reg */
#define PHY_MARV_PAGE_ADDR	0x1d	/* 16 bit r/w	Extended Page Address Reg */
#define PHY_MARV_PAGE_DATA	0x1e	/* 16 bit r/w	Extended Page Data Reg */

/* for 10/100 Fast Ethernet PHY (88E3082 only) */
#define PHY_MARV_FE_LED_PAR	0x16	/* 16 bit r/w	LED Parallel Select Reg. */
#define PHY_MARV_FE_LED_SER	0x17	/* 16 bit r/w	LED Stream Select S. LED */
#define PHY_MARV_FE_VCT_TX	0x1a	/* 16 bit r/w	VCT Reg. for TXP/N Pins */
#define PHY_MARV_FE_VCT_RX	0x1b	/* 16 bit r/o	VCT Reg. for RXP/N Pins */
#define PHY_MARV_FE_SPEC_2	0x1c	/* 16 bit r/w	Specific Control Reg. 2 */

/* for Yukon-Ultra & Yukon-Extreme PHY only */
#define PHY_MARV_MAC_CTRL	0x15	/* 16 bit r/w	MAC Spec. Ctrl (page 2) */

/*----------------------------------------------------------------------------*/
/*
 * Level One-PHY Registers, indirect addressed over XMAC
 */
#define PHY_LONE_CTRL		0x00	/* 16 bit r/w	PHY Control Register */
#define PHY_LONE_STAT		0x01	/* 16 bit r/o	PHY Status Register */
#define PHY_LONE_ID0		0x02	/* 16 bit r/o	PHY ID0 Register */
#define PHY_LONE_ID1		0x03	/* 16 bit r/o	PHY ID1 Register */
#define PHY_LONE_AUNE_ADV	0x04	/* 16 bit r/w	Auto-Neg. Advertisement */
#define PHY_LONE_AUNE_LP	0x05	/* 16 bit r/o	Link Partner Ability Reg */
#define PHY_LONE_AUNE_EXP	0x06	/* 16 bit r/o	Auto-Neg. Expansion Reg */
#define PHY_LONE_NEPG		0x07	/* 16 bit r/w	Next Page Register */
#define PHY_LONE_NEPG_LP	0x08	/* 16 bit r/o	Next Page Link Partner */
	/* Level One-specific registers */
#define PHY_LONE_1000T_CTRL	0x09	/* 16 bit r/w	1000Base-T Control Reg */
#define PHY_LONE_1000T_STAT	0x0a	/* 16 bit r/o	1000Base-T Status Reg */
	/* 0x0b - 0x0e:		reserved */
#define PHY_LONE_EXT_STAT	0x0f	/* 16 bit r/o	Extended Status Reg */
#define PHY_LONE_PORT_CFG	0x10	/* 16 bit r/w	Port Configuration Reg*/
#define PHY_LONE_Q_STAT		0x11	/* 16 bit r/o	Quick Status Reg */
#define PHY_LONE_INT_ENAB	0x12	/* 16 bit r/w	Interrupt Enable Reg */
#define PHY_LONE_INT_STAT	0x13	/* 16 bit r/o	Interrupt Status Reg */
#define PHY_LONE_LED_CFG	0x14	/* 16 bit r/w	LED Configuration Reg */
#define PHY_LONE_PORT_CTRL	0x15	/* 16 bit r/w	Port Control Reg */
#define PHY_LONE_CIM		0x16	/* 16 bit r/o	CIM Reg */
	/* 0x17 - 0x1c:		reserved */

/*----------------------------------------------------------------------------*/
/*
 * National-PHY Registers, indirect addressed over XMAC
 */
#define PHY_NAT_CTRL		0x00	/* 16 bit r/w	PHY Control Register */
#define PHY_NAT_STAT		0x01	/* 16 bit r/w	PHY Status Register */
#define PHY_NAT_ID0			0x02	/* 16 bit r/o	PHY ID0 Register */
#define PHY_NAT_ID1			0x03	/* 16 bit r/o	PHY ID1 Register */
#define PHY_NAT_AUNE_ADV	0x04	/* 16 bit r/w	Auto-Neg. Advertisement */
#define PHY_NAT_AUNE_LP		0x05	/* 16 bit r/o	Link Partner Ability Reg */
#define PHY_NAT_AUNE_EXP	0x06	/* 16 bit r/o	Auto-Neg. Expansion Reg */
#define PHY_NAT_NEPG		0x07	/* 16 bit r/w	Next Page Register */
#define PHY_NAT_NEPG_LP		0x08	/* 16 bit r/o	Next Page Link Partner Reg */
	/* National-specific registers */
#define PHY_NAT_1000T_CTRL	0x09	/* 16 bit r/w	1000Base-T Control Reg */
#define PHY_NAT_1000T_STAT	0x0a	/* 16 bit r/o	1000Base-T Status Reg */
	/* 0x0b - 0x0e:		reserved */
#define PHY_NAT_EXT_STAT	0x0f	/* 16 bit r/o	Extended Status Register */
#define PHY_NAT_EXT_CTRL1	0x10	/* 16 bit r/o	Extended Control Reg1 */
#define PHY_NAT_Q_STAT1		0x11	/* 16 bit r/o	Quick Status Reg1 */
#define PHY_NAT_10B_OP		0x12	/* 16 bit r/o	10Base-T Operations Reg */
#define PHY_NAT_EXT_CTRL2	0x13	/* 16 bit r/o	Extended Control Reg1 */
#define PHY_NAT_Q_STAT2		0x14	/* 16 bit r/o	Quick Status Reg2 */
	/* 0x15 - 0x18:		reserved */
#define PHY_NAT_PHY_ADDR	0x19	/* 16 bit r/o	PHY Address Register */


/*----------------------------------------------------------------------------*/

/*
 * PHY bit definitions
 * Bits defined as PHY_X_..., PHY_B_..., PHY_L_..., PHY_N_... or PHY_M_... are
 * XMAC/Broadcom/LevelOne/National/Marvell-specific.
 * All other are general.
 */

/*****  PHY_XMAC_CTRL	16 bit r/w	PHY Control Register *****/
/*****  PHY_BCOM_CTRL	16 bit r/w	PHY Control Register *****/
/*****  PHY_MARV_CTRL	16 bit r/w	PHY Status Register *****/
/*****  PHY_LONE_CTRL	16 bit r/w	PHY Control Register *****/
#define PHY_CT_RESET	(1<<15)	/* Bit 15: (sc)	clear all PHY related regs */
#define PHY_CT_LOOP		(1<<14)	/* Bit 14:	enable Loopback over PHY */
#define PHY_CT_SPS_LSB	(1<<13) /* Bit 13:	Speed select, lower bit */
#define PHY_CT_ANE		(1<<12)	/* Bit 12:	Auto-Negotiation Enabled */
#define PHY_CT_PDOWN	(1<<11)	/* Bit 11:	Power Down Mode */
#define PHY_CT_ISOL		(1<<10)	/* Bit 10:	Isolate Mode */
#define PHY_CT_RE_CFG	(1<<9)	/* Bit  9:	(sc) Restart Auto-Negotiation */
#define PHY_CT_DUP_MD	(1<<8)	/* Bit  8:	Duplex Mode */
#define PHY_CT_COL_TST	(1<<7)	/* Bit  7:	Collision Test enabled */
#define PHY_CT_SPS_MSB	(1<<6)	/* Bit  6:	Speed select, upper bit */
								/* Bit  5..0:	reserved */

#define PHY_CT_SP1000	PHY_CT_SPS_MSB	/* enable speed of 1000 Mbps */
#define PHY_CT_SP100	PHY_CT_SPS_LSB	/* enable speed of  100 Mbps */
#define PHY_CT_SP10		(0)				/* enable speed of   10 Mbps */


/*****  PHY_XMAC_STAT	16 bit r/w	PHY Status Register *****/
/*****  PHY_BCOM_STAT	16 bit r/w	PHY Status Register *****/
/*****  PHY_MARV_STAT	16 bit r/w	PHY Status Register *****/
/*****  PHY_LONE_STAT	16 bit r/w	PHY Status Register *****/
								/* Bit 15..9:	reserved */
				/*	(BC/L1) 100/10 Mbps cap bits ignored */
#define PHY_ST_EXT_ST	(1<<8)	/* Bit  8:	Extended Status Present */
								/* Bit  7:	reserved */
#define PHY_ST_PRE_SUP	(1<<6)	/* Bit  6:	Preamble Suppression */
#define PHY_ST_AN_OVER	(1<<5)	/* Bit  5:	Auto-Negotiation Over */
#define PHY_ST_REM_FLT	(1<<4)	/* Bit  4:	Remote Fault Condition Occurred */
#define PHY_ST_AN_CAP	(1<<3)	/* Bit  3:	Auto-Negotiation Capability */
#define PHY_ST_LSYNC	(1<<2)	/* Bit  2:	Link Synchronized */
#define PHY_ST_JAB_DET	(1<<1)	/* Bit  1:	Jabber Detected */
#define PHY_ST_EXT_REG	(1<<0)	/* Bit  0:	Extended Register available */


/*****  PHY_XMAC_ID1		16 bit r/o	PHY ID1 Register */
/*****  PHY_BCOM_ID1		16 bit r/o	PHY ID1 Register */
/*****  PHY_MARV_ID1		16 bit r/o	PHY ID1 Register */
/*****  PHY_LONE_ID1		16 bit r/o	PHY ID1 Register */
#define PHY_I1_OUI_MSK	(0x3f<<10)	/* Bit 15..10:	Organization Unique ID */
#define PHY_I1_MOD_NUM	(0x3f<<4)	/* Bit  9.. 4:	Model Number */
#define PHY_I1_REV_MSK	0xf			/* Bit  3.. 0:	Revision Number */

/* different Broadcom PHY Ids */
#define PHY_BCOM_ID1_A1		0x6041
#define PHY_BCOM_ID1_B2		0x6043
#define PHY_BCOM_ID1_C0		0x6044
#define PHY_BCOM_ID1_C5		0x6047

/* different Marvell PHY Ids */
#define PHY_MARV_ID0_VAL	0x0141		/* Marvell Unique Identifier */

#define PHY_MARV_ID1_B0		0x0C23		/* Yukon      (PHY 88E1040 Rev.C0) */
#define PHY_MARV_ID1_B2		0x0C25		/* Yukon-Plus (PHY 88E1040 Rev.D0) */
#define PHY_MARV_ID1_C2		0x0CC2		/* Yukon-EC   (PHY 88E1111 Rev.B1) */
#define PHY_MARV_ID1_Y2		0x0C91		/* Yukon-XL   (PHY 88E1112 Rev.B0) */
#define PHY_MARV_ID1_FE		0x0C83		/* Yukon-FE   (PHY 88E3082 Rev.A1) */
#define PHY_MARV_ID1_FEP	0x0E60		/* Yukon-FE+  (PHY 88E3016 Rev.A1?) */
#define PHY_MARV_ID1_ECU	0x0CB0		/* Yukon-ECU  (PHY 88E1149 Rev.B2?) */
#define PHY_MARV_ID1_EX		0x0CB1		/* Yukon-Ext. (PHY 88E1149R Rev.?) */


/*****  PHY_XMAC_AUNE_ADV	16 bit r/w	Auto-Negotiation Advertisement *****/
/*****  PHY_XMAC_AUNE_LP	16 bit r/o	Link Partner Ability Reg *****/
#define PHY_AN_NXT_PG	(1<<15)	/* Bit 15:	Request Next Page */
#define PHY_X_AN_ACK	(1<<14)	/* Bit 14:	(ro) Acknowledge Received */
#define PHY_X_AN_RFB	(3<<12)	/* Bit 13..12:	Remote Fault Bits */
								/* Bit 11.. 9:	reserved */
#define PHY_X_AN_PAUSE	(3<<7)	/* Bit  8.. 7:	Pause Bits */
#define PHY_X_AN_HD		(1<<6)	/* Bit  6:	Half Duplex */
#define PHY_X_AN_FD		(1<<5)	/* Bit  5:	Full Duplex */
								/* Bit  4.. 0:	reserved */

/*****  PHY_BCOM_AUNE_ADV	16 bit r/w	Auto-Negotiation Advertisement *****/
/*****  PHY_BCOM_AUNE_LP	16 bit r/o	Link Partner Ability Reg *****/
/*	PHY_AN_NXT_PG		(see XMAC) Bit 15:	Request Next Page */
								/* Bit 14:	reserved */
#define PHY_B_AN_RF		(1<<13)	/* Bit 13:	Remote Fault */
								/* Bit 12:	reserved */
#define PHY_B_AN_ASP	(1<<11)	/* Bit 11:	Asymmetric Pause */
#define PHY_B_AN_PC		(1<<10)	/* Bit 10:	Pause Capable */
								/* Bit  9..5:	100/10 BT cap bits ingnored */
#define PHY_B_AN_SEL	0x1f	/* Bit 4..0:	Selector Field, 00001=Ethernet*/

/*****  PHY_LONE_AUNE_ADV	16 bit r/w	Auto-Negotiation Advertisement *****/
/*****  PHY_LONE_AUNE_LP	16 bit r/o	Link Partner Ability Reg *****/
/*	PHY_AN_NXT_PG		(see XMAC) Bit 15:	Request Next Page */
								/* Bit 14:	reserved */
#define PHY_L_AN_RF		(1<<13)	/* Bit 13:	Remote Fault */
								/* Bit 12:	reserved */
#define PHY_L_AN_ASP	(1<<11)	/* Bit 11:	Asymmetric Pause */
#define PHY_L_AN_PC		(1<<10)	/* Bit 10:	Pause Capable */
								/* Bit  9..5:	100/10 BT cap bits ingnored */
#define PHY_L_AN_SEL	0x1f	/* Bit 4..0:	Selector Field, 00001=Ethernet*/

/*****  PHY_NAT_AUNE_ADV	16 bit r/w	Auto-Negotiation Advertisement *****/
/*****  PHY_NAT_AUNE_LP		16 bit r/o	Link Partner Ability Reg *****/
/*	PHY_AN_NXT_PG		(see XMAC) Bit 15:	Request Next Page */
								/* Bit 14:	reserved */
#define PHY_N_AN_RF		(1<<13)	/* Bit 13:	Remote Fault */
								/* Bit 12:	reserved */
#define PHY_N_AN_100F	(1<<11)	/* Bit 11:	100Base-T2 FD Support */
#define PHY_N_AN_100H	(1<<10)	/* Bit 10:	100Base-T2 HD Support */
								/* Bit  9..5:	100/10 BT cap bits ingnored */
#define PHY_N_AN_SEL	0x1f	/* Bit 4..0:	Selector Field, 00001=Ethernet*/

/* field type definition for PHY_x_AN_SEL */
#define PHY_SEL_TYPE	0x01	/* 00001 = Ethernet */

/*****  PHY_XMAC_AUNE_EXP	16 bit r/o	Auto-Negotiation Expansion Reg *****/
								/* Bit 15..4:	reserved */
#define PHY_ANE_LP_NP	(1<<3)	/* Bit  3:	Link Partner can Next Page */
#define PHY_ANE_LOC_NP	(1<<2)	/* Bit  2:	Local PHY can Next Page */
#define PHY_ANE_RX_PG	(1<<1)	/* Bit  1:	Page Received */