skxmac2.c

这是Marvell Technology Group Ltd. 4355 (rev 12)网卡在linux下的驱动程序源代码

 *	SkMacFlushTxFifo() - Flush the MAC's transmit FIFO
 *
 * Description:
 *	Flush the transmit FIFO of the MAC specified by the index 'Port'
 *
 * Returns:
 *	nothing
 */
void SkMacFlushTxFifo(
SK_AC	*pAC,	/* Adapter Context */
SK_IOC	IoC,	/* I/O Context */
int		Port)	/* Port Index (MAC_1 + n) */
{
	/* no way to flush the FIFO we have to issue a reset */
	/* TBD */

}	/* SkMacFlushTxFifo */


/******************************************************************************
 *
 *	SkMacFlushRxFifo() - Flush the MAC's receive FIFO
 *
 * Description:
 *	Flush the receive FIFO of the MAC specified by the index 'Port'
 *
 * Returns:
 *	nothing
 */
void SkMacFlushRxFifo(
SK_AC	*pAC,	/* Adapter Context */
SK_IOC	IoC,	/* I/O Context */
int		Port)	/* Port Index (MAC_1 + n) */
{
	/* no way to flush the FIFO we have to issue a reset */
	/* TBD */

}	/* SkMacFlushRxFifo */


/******************************************************************************
 *
 *	SkGmSoftRst() - Do a GMAC software reset
 *
 * Description:
 *	The GPHY registers should not be destroyed during this
 *	kind of software reset.
 *
 * Returns:
 *	nothing
 */
static void SkGmSoftRst(
SK_AC	*pAC,	/* Adapter Context */
SK_IOC	IoC,	/* I/O Context */
int		Port)	/* Port Index (MAC_1 + n) */
{
	SK_U16	EmptyHash[4] = { 0x0000, 0x0000, 0x0000, 0x0000 };
	SK_U16	RxCtrl;

	SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
		("SkGmSoftRst: Port %d\n", Port));

	/* reset the statistics module */
	(void)SkGmResetCounter(pAC, IoC, Port);

	/* disable all GMAC IRQs */
	SK_OUT8(IoC, MR_ADDR(Port, GMAC_IRQ_MSK), 0);

	if (pAC->GIni.GP[Port].PState != SK_PRT_RESET) {
		/* disable all PHY IRQs */
		SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_INT_MASK, 0);
	}

	/* clear the Hash Register */
	GM_OUTHASH(IoC, Port, GM_MC_ADDR_H1, EmptyHash);

	/* enable Unicast and Multicast filtering */
	GM_IN16(IoC, Port, GM_RX_CTRL, &RxCtrl);

	GM_OUT16(IoC, Port, GM_RX_CTRL, RxCtrl | GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);

}	/* SkGmSoftRst */


/******************************************************************************
 *
 *	SkGmHardRst() - Do a GMAC hardware reset
 *
 * Description:
 *
 * Returns:
 *	nothing
 */
static void SkGmHardRst(
SK_AC	*pAC,	/* Adapter Context */
SK_IOC	IoC,	/* I/O Context */
int		Port)	/* Port Index (MAC_1 + n) */
{
	SK_U32	DWord;

	SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
		("SkGmHardRst: Port %d\n", Port));

	/* WA code for COMA mode */
	if (pAC->GIni.GIYukonLite &&
		pAC->GIni.GIChipRev >= CHIP_REV_YU_LITE_A3) {

		SK_IN32(IoC, B2_GP_IO, &DWord);

		DWord |= (GP_DIR_9 | GP_IO_9);

		/* set PHY reset */
		SK_OUT32(IoC, B2_GP_IO, DWord);
	}

	/* set GPHY Control reset */
	SK_OUT8(IoC, MR_ADDR(Port, GPHY_CTRL), (SK_U8)GPC_RST_SET);

	if (!pAC->GIni.GIAsfEnabled) {
		/* set GMAC Control reset */
		SK_OUT8(IoC, MR_ADDR(Port, GMAC_CTRL), (SK_U8)GMC_RST_SET);
	}

}	/* SkGmHardRst */


/******************************************************************************
 *
 *	SkGmClearRst() - Release the GPHY & GMAC reset
 *
 * Description:
 *
 * Returns:
 *	nothing
 */
static void SkGmClearRst(
SK_AC	*pAC,	/* Adapter Context */
SK_IOC	IoC,	/* I/O Context */
int		Port)	/* Port Index (MAC_1 + n) */
{
	SK_U32	DWord;
#ifdef SK_DIAG
	SK_U16	PhyId0;
	SK_U16	PhyId1;
	SK_U16	Word;
#endif /* SK_DIAG */

#ifdef DEBUG
	SK_U8	Byte;
#endif /* DEBUG */

	SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
		("SkGmClearRst: Port %d\n", Port));
#ifndef DISABLE_YUKON_I
	/* WA code for COMA mode */
	if (pAC->GIni.GIYukonLite &&
		pAC->GIni.GIChipRev >= CHIP_REV_YU_LITE_A3) {

		SK_IN32(IoC, B2_GP_IO, &DWord);

		DWord |= GP_DIR_9;		/* set to output */
		DWord &= ~GP_IO_9;		/* clear PHY reset (active high) */

		/* clear PHY reset */
		SK_OUT32(IoC, B2_GP_IO, DWord);
	}
#endif /* !DISABLE_YUKON_I */
#ifdef VCPU
	/* set MAC Reset before PHY reset is set */
	SK_OUT8(IoC, MR_ADDR(Port, GMAC_CTRL), (SK_U8)GMC_RST_SET);
#endif /* VCPU */

	if (CHIP_ID_YUKON_2(pAC)) {
		/* set GPHY Control reset */
		SK_OUT8(IoC, MR_ADDR(Port, GPHY_CTRL), (SK_U8)GPC_RST_SET);

		/* release GPHY Control reset */
		SK_OUT8(IoC, MR_ADDR(Port, GPHY_CTRL), (SK_U8)GPC_RST_CLR);

#ifdef DEBUG
		/* additional check for PEX */
		SK_IN8(IoC, GPHY_CTRL, &Byte);

		Byte &= GPC_RST_CLR | GPC_RST_SET;

		if (pAC->GIni.GIPciBus == SK_PEX_BUS && Byte != GPC_RST_CLR) {

			SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR,
				("Error on PEX-bus after GPHY reset (GPHY Ctrl=0x%02X)\n",
				Byte));
		}
#endif /* DEBUG */
	}
#ifndef DISABLE_YUKON_I
	else {
		/* set HWCFG_MODE */
		DWord = GPC_INT_POL | GPC_DIS_FC | GPC_DIS_SLEEP |
			GPC_ENA_XC | GPC_ANEG_ADV_ALL_M | GPC_ENA_PAUSE |
			(pAC->GIni.GICopperType ? GPC_HWCFG_GMII_COP :
			GPC_HWCFG_GMII_FIB);

		/* set GPHY Control reset */
		SK_OUT32(IoC, MR_ADDR(Port, GPHY_CTRL), DWord | GPC_RST_SET);

		/* release GPHY Control reset */
		SK_OUT32(IoC, MR_ADDR(Port, GPHY_CTRL), DWord | GPC_RST_CLR);
	}
#endif /* !DISABLE_YUKON_I */
#if defined(VCPU) && !defined(HASE)
	/* wait for internal initialization of GPHY */
	VCPUprintf(0, "Waiting until PHY %d is ready to initialize\n", Port);
	VCpuWait(10000);
#endif /* VCPU */

	/* clear GMAC Control reset */
	SK_OUT8(IoC, MR_ADDR(Port, GMAC_CTRL), (SK_U8)GMC_RST_CLR);

#if defined(VCPU) && !defined(HASE)
	/* wait for stable GMAC clock */
	VCpuWait(9000);
#endif /* VCPU */

#ifdef SK_DIAG
	if (HW_FEATURE(pAC, HWF_WA_DEV_472) && Port == MAC_2) {

		/* clear GMAC 1 Control reset */
		SK_OUT8(IoC, MR_ADDR(MAC_1, GMAC_CTRL), (SK_U8)GMC_RST_CLR);

		do {
			/* set GMAC 2 Control reset */
			SK_OUT8(IoC, MR_ADDR(MAC_2, GMAC_CTRL), (SK_U8)GMC_RST_SET);

			/* clear GMAC 2 Control reset */
			SK_OUT8(IoC, MR_ADDR(MAC_2, GMAC_CTRL), (SK_U8)GMC_RST_CLR);

			SkGmPhyRead(pAC, IoC, MAC_2, PHY_MARV_ID0, &PhyId0);

			SkGmPhyRead(pAC, IoC, MAC_2, PHY_MARV_ID1, &PhyId1);

			SkGmPhyRead(pAC, IoC, MAC_2, PHY_MARV_INT_MASK, &Word);

		} while (Word != 0 || PhyId0 != PHY_MARV_ID0_VAL ||
				 PhyId1 != PHY_MARV_ID1_Y2);
	}
#endif /* SK_DIAG */

#if defined(VCPU) && !defined(HASE)
	VCpuWait(2000);

	SK_IN32(IoC, MR_ADDR(Port, GPHY_CTRL), &DWord);

	SK_IN32(IoC, B0_ISRC, &DWord);
#endif /* VCPU */

}	/* SkGmClearRst */


/******************************************************************************
 *
 *	SkMacSoftRst() - Do a MAC software reset
 *
 * Description:	calls a MAC software reset routine dep. on board type
 *
 * Returns:
 *	nothing
 */
void SkMacSoftRst(
SK_AC	*pAC,	/* Adapter Context */
SK_IOC	IoC,	/* I/O Context */
int		Port)	/* Port Index (MAC_1 + n) */
{
	/* disable receiver and transmitter */
	SkMacRxTxDisable(pAC, IoC, Port);

	SkGmSoftRst(pAC, IoC, Port);

	/* flush the MAC's Rx and Tx FIFOs */
	SkMacFlushTxFifo(pAC, IoC, Port);

	SkMacFlushRxFifo(pAC, IoC, Port);

	pAC->GIni.GP[Port].PState = SK_PRT_STOP;

}	/* SkMacSoftRst */


/******************************************************************************
 *
 *	SkMacHardRst() - Do a MAC hardware reset
 *
 * Description:	calls a MAC hardware reset routine dep. on board type
 *
 * Returns:
 *	nothing
 */
void SkMacHardRst(
SK_AC	*pAC,	/* Adapter Context */
SK_IOC	IoC,	/* I/O Context */
int		Port)	/* Port Index (MAC_1 + n) */
{
	SkGmHardRst(pAC, IoC, Port);

	pAC->GIni.GP[Port].PHWLinkUp = SK_FALSE;

	pAC->GIni.GP[Port].PState = SK_PRT_RESET;

}	/* SkMacHardRst */

#ifndef SK_SLIM
/******************************************************************************
 *
 *	SkMacClearRst() - Clear the MAC reset
 *
 * Description:	calls a clear MAC reset routine dep. on board type
 *
 * Returns:
 *	nothing
 */
void SkMacClearRst(
SK_AC	*pAC,	/* Adapter Context */
SK_IOC	IoC,	/* I/O Context */
int		Port)	/* Port Index (MAC_1 + n) */
{
	SkGmClearRst(pAC, IoC, Port);

}	/* SkMacClearRst */
#endif /* !SK_SLIM */

/******************************************************************************
 *
 *	SkGmInitMac() - Initialize the GMAC
 *
 * Description:
 *	Initialize the GMAC of the specified port.
 *	The GMAC must be reset or stopped before calling this function.
 *
 * Note:
 *	The GMAC's Rx and Tx state machine is still disabled when returning.
 *
 * Returns:
 *	nothing
 */
void SkGmInitMac(
SK_AC	*pAC,		/* Adapter Context */
SK_IOC	IoC,		/* I/O Context */
int		Port)		/* Port Index (MAC_1 + n) */
{
	SK_GEPORT	*pPrt;
	int			i;
	SK_U16		SWord;
	SK_U32		DWord;

	pPrt = &pAC->GIni.GP[Port];

	SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
		("SkGmInitMac: Port %d, PState = %d, PLinkSpeed = %d\n",
		 Port, pPrt->PState, pPrt->PLinkSpeed));

	if (pPrt->PState == SK_PRT_STOP) {
		/* Verify that the reset bit is cleared */
		SK_IN32(IoC, MR_ADDR(Port, GMAC_CTRL), &DWord);

		if ((DWord & GMC_RST_SET) != 0) {
			/* PState does not match HW state */
			SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
				("SkGmInitMac: PState does not match HW state"));
			/* Correct it */
			pPrt->PState = SK_PRT_RESET;
		}
		else {
			/* enable PHY interrupts */
			SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_INT_MASK,
				(SK_U16)PHY_M_DEF_MSK);
		}
	}

	if (pPrt->PState == SK_PRT_RESET) {

		SkGmHardRst(pAC, IoC, Port);

		SkGmClearRst(pAC, IoC, Port);

#ifndef SK_SLIM
		if (HW_FEATURE(pAC, HWF_FORCE_AUTO_NEG) &&
			pPrt->PLinkModeConf < SK_LMODE_AUTOHALF) {
			/* Force Auto-Negotiation */
			pPrt->PLinkMode = (pPrt->PLinkModeConf == SK_LMODE_FULL) ?
				SK_LMODE_AUTOBOTH : SK_LMODE_AUTOHALF;

			SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
				("SkGmInitMac: Force Auto-Negotiation, PLinkMode = %d",
				pPrt->PLinkMode));
		}
#endif /* !SK_SLIM */

		/* Auto-negotiation ? */
		if (pPrt->PLinkMode == SK_LMODE_HALF ||
			pPrt->PLinkMode == SK_LMODE_FULL) {
			/* Auto-negotiation disabled */

			/* disable auto-update for speed, duplex and flow-control */
			SWord = GM_GPCR_AU_ALL_DIS;

			/* speed settings */
			switch (pPrt->PLinkSpeed) {
			case SK_LSPEED_AUTO:
			case SK_LSPEED_1000MBPS:
				if ((pPrt->PLinkSpeedCap & SK_LSPEED_CAP_1000MBPS) != 0) {

					SWord |= GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100;
				}
				break;
			case SK_LSPEED_100MBPS:
				SWord |= GM_GPCR_SPEED_100;
				break;
			case SK_LSPEED_10MBPS:
				break;
			}

			/* duplex settings */
			if (pPrt->PLinkMode != SK_LMODE_HALF) {
				/* set full duplex */
				SWord |= GM_GPCR_DUP_FULL;
			}

			/* flow-control settings */
			switch (pPrt->PFlowCtrlMode) {
			case SK_FLOW_MODE_NONE:
				/* disable Tx & Rx flow-control */
				SWord |= GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
				break;
			case SK_FLOW_MODE_LOC_SEND:
				/* disable Rx flow-control */
				SWord |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
				break;
			case SK_FLOW_MODE_SYMMETRIC:
			case SK_FLOW_MODE_SYM_OR_REM:
				/* enable Tx & Rx flow-control */
				break;
			}
		}
		else {
			SWord = 0;
		}

		/* setup General Purpose Control Register */
		GM_OUT16(IoC, Port, GM_GP_CTRL, SWord);

		/* dummy read the Interrupt Source Register */
		SK_IN16(IoC, MR_ADDR(Port, GMAC_IRQ_SRC), &SWord);

#ifndef VCPU
		SkGmInitPhyMarv(pAC, IoC, Port, SK_FALSE);
#endif /* !VCPU */
	}

#ifndef VCPU	/* saves some time in co-sim */
	(void)SkGmResetCounter(pAC, IoC, Port);
#endif

	/* setup Transmit Control Register */
#ifndef SK_SLIM
	GM_OUT16(IoC, Port, GM_TX_CTRL, (SK_U16)TX_COL_THR(pPrt->PMacColThres));
#else
	GM_OUT16(IoC, Port, GM_TX_CTRL, (SK_U16)TX_COL_THR(TX_COL_DEF));
#endif
	/* setup Receive Control Register */
	SWord = GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA | GM_RXCR_CRC_DIS;

	GM_OUT16(IoC, Port, GM_RX_CTRL, SWord);

	/* setup Transmit Flow Control Register */
	GM_OUT16(IoC, Port, GM_TX_FLOW_CTRL, 0xffff);

	/* setup Transmit Parameter Register */
#ifdef VCPU
	GM_IN16(IoC, Port, GM_TX_PARAM, &SWord);
#endif /* VCPU */

#ifndef SK_SLIM
	SWord = (SK_U16)(TX_JAM_LEN_VAL(pPrt->PMacJamLen) |
		TX_JAM_IPG_VAL(pPrt->PMacJamIpgVal) |
		TX_IPG_JAM_DATA(pPrt->PMacJamIpgData) |
		TX_BACK_OFF_LIM(pPrt->PMacBackOffLim));
#else
	SWord = (SK_U16)(TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
		TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
		TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
		TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
#endif

	GM_OUT16(IoC, Port, GM_TX_PARAM, SWord);