fenpin.v

可以对输入时钟任意分频(整数或小数),带Quartus II 完整项目文件.

/*
--------------------------------------------------------------------
File Name : fenpin.v
Programmer(s) : woailiushui [e-mail]
Commany : IOEMCT OF TJU
Created : 2006/05/09
Description :  The program for frequency divide
Modified History :
	Modified :
	Programmer :
	Description :
--------------------------------------------------------------------
*/

module fenpin
(
	odde, fraction, clr, clkout, coef_i, xor_clk, out
);

	input odde;
	input fraction;
	input clr;
	input clkout;
	input [7:0] coef_i;
	output xor_clk;
	output out;

    parameter CLR_C = 8'b00000000; 
    parameter INC_C = 8'b00000001; 
    
	wire [7:0]half_coef = (coef_i >> 1);

	reg [7:0]count;
	reg clk_1;
	
	//The terminal frequency
	assign out = (odde && !fraction)?clk_2:clk_1;

    always @(posedge clkout or negedge clr) begin
      if(~clr) begin 
        clk_1 <= 1'b0;
        count <= CLR_C;
      end
      else begin
        //For the fraction divide
        if(fraction) begin
          if(count == half_coef) begin
            clk_1 <= 1'b1;
            count <= count + INC_C;
          end
          else begin
            if(count == coef_i) begin
              count <= CLR_C;
              clk_1 <= 1'b0;
            end
            else 
              count <= count + INC_C;
          end
        end
        else begin
          //For the integer divide 
          if(count == (half_coef - INC_C)) begin
            clk_1 <= 1'b1;
            count <= count + INC_C;
          end
          else begin
            if(count == (coef_i - INC_C)) begin
              count <= CLR_C;
              clk_1 <= 1'b0;
            end
            else 
              count <= count + INC_C;
          end
        end
      end 
    end

	//For the odde divide frequency
	reg [7:0]cnt;
	reg clk_t;

	wire clk_2;

	assign clk_2 = clk_t & clk_1;

	always @(negedge clkout or negedge clr) begin
 	  if(~clr) begin 
 	    cnt <= INC_C;
 	    clk_t <= 1'b0;
      end
 	  else begin
 	    if (odde) begin
  	      if(cnt == half_coef) begin
            clk_t <= 1'b1;
            cnt <= cnt + INC_C; 
          end
        else begin
          if (cnt == coef_i) begin
            clk_t <= 1'b0;
            cnt <= INC_C;
          end 
          else
            cnt <= cnt + INC_C; 
          end
        end  
      end
    end

    //For the fraction divide
    reg xor_clk;
	
    always @(posedge clk_1) begin
      if (fraction)
        xor_clk = !xor_clk;  
      else
        xor_clk = xor_clk;
   end

endmodule