📄 pic18fxx8.h
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static volatile bit RXB1D43 @ ((unsigned)&RXB1D4*8)+3;
static volatile bit RXB1D42 @ ((unsigned)&RXB1D4*8)+2;
static volatile bit RXB1D41 @ ((unsigned)&RXB1D4*8)+1;
static volatile bit RXB1D40 @ ((unsigned)&RXB1D4*8)+0;
// RXB1D3 Register
static volatile bit RXB1D37 @ ((unsigned)&RXB1D3*8)+7;
static volatile bit RXB1D36 @ ((unsigned)&RXB1D3*8)+6;
static volatile bit RXB1D35 @ ((unsigned)&RXB1D3*8)+5;
static volatile bit RXB1D34 @ ((unsigned)&RXB1D3*8)+4;
static volatile bit RXB1D33 @ ((unsigned)&RXB1D3*8)+3;
static volatile bit RXB1D32 @ ((unsigned)&RXB1D3*8)+2;
static volatile bit RXB1D31 @ ((unsigned)&RXB1D3*8)+1;
static volatile bit RXB1D30 @ ((unsigned)&RXB1D3*8)+0;
// RXB1D2 Register
static volatile bit RXB1D27 @ ((unsigned)&RXB1D2*8)+7;
static volatile bit RXB1D26 @ ((unsigned)&RXB1D2*8)+6;
static volatile bit RXB1D25 @ ((unsigned)&RXB1D2*8)+5;
static volatile bit RXB1D24 @ ((unsigned)&RXB1D2*8)+4;
static volatile bit RXB1D23 @ ((unsigned)&RXB1D2*8)+3;
static volatile bit RXB1D22 @ ((unsigned)&RXB1D2*8)+2;
static volatile bit RXB1D21 @ ((unsigned)&RXB1D2*8)+1;
static volatile bit RXB1D20 @ ((unsigned)&RXB1D2*8)+0;
// RXB1D1 Register
static volatile bit RXB1D17 @ ((unsigned)&RXB1D1*8)+7;
static volatile bit RXB1D16 @ ((unsigned)&RXB1D1*8)+6;
static volatile bit RXB1D15 @ ((unsigned)&RXB1D1*8)+5;
static volatile bit RXB1D14 @ ((unsigned)&RXB1D1*8)+4;
static volatile bit RXB1D13 @ ((unsigned)&RXB1D1*8)+3;
static volatile bit RXB1D12 @ ((unsigned)&RXB1D1*8)+2;
static volatile bit RXB1D11 @ ((unsigned)&RXB1D1*8)+1;
static volatile bit RXB1D10 @ ((unsigned)&RXB1D1*8)+0;
// RXB1D0 Register
static volatile bit RXB1D07 @ ((unsigned)&RXB1D0*8)+7;
static volatile bit RXB1D06 @ ((unsigned)&RXB1D0*8)+6;
static volatile bit RXB1D05 @ ((unsigned)&RXB1D0*8)+5;
static volatile bit RXB1D04 @ ((unsigned)&RXB1D0*8)+4;
static volatile bit RXB1D03 @ ((unsigned)&RXB1D0*8)+3;
static volatile bit RXB1D02 @ ((unsigned)&RXB1D0*8)+2;
static volatile bit RXB1D01 @ ((unsigned)&RXB1D0*8)+1;
static volatile bit RXB1D00 @ ((unsigned)&RXB1D0*8)+0;
// RXB1DLC Register
static volatile bit RXB1RXRTR @ ((unsigned)&RXB1DLC*8)+6;
static volatile bit RXB1RB1 @ ((unsigned)&RXB1DLC*8)+5;
static volatile bit RXB1RB0 @ ((unsigned)&RXB1DLC*8)+4;
static volatile bit RXB1DLC3 @ ((unsigned)&RXB1DLC*8)+3;
static volatile bit RXB1DLC2 @ ((unsigned)&RXB1DLC*8)+2;
static volatile bit RXB1DLC1 @ ((unsigned)&RXB1DLC*8)+1;
static volatile bit RXB1DLC0 @ ((unsigned)&RXB1DLC*8)+0;
// RXB1EIDL Register
static volatile bit RXB1EID7 @ ((unsigned)&RXB1EIDL*8)+7;
static volatile bit RXB1EID6 @ ((unsigned)&RXB1EIDL*8)+6;
static volatile bit RXB1EID5 @ ((unsigned)&RXB1EIDL*8)+5;
static volatile bit RXB1EID4 @ ((unsigned)&RXB1EIDL*8)+4;
static volatile bit RXB1EID3 @ ((unsigned)&RXB1EIDL*8)+3;
static volatile bit RXB1EID2 @ ((unsigned)&RXB1EIDL*8)+2;
static volatile bit RXB1EID1 @ ((unsigned)&RXB1EIDL*8)+1;
static volatile bit RXB1EID0 @ ((unsigned)&RXB1EIDL*8)+0;
// RXB1EIDH Register
static volatile bit RXB1EID15 @ ((unsigned)&RXB1EIDH*8)+7;
static volatile bit RXB1EID14 @ ((unsigned)&RXB1EIDH*8)+6;
static volatile bit RXB1EID13 @ ((unsigned)&RXB1EIDH*8)+5;
static volatile bit RXB1EID12 @ ((unsigned)&RXB1EIDH*8)+4;
static volatile bit RXB1EID11 @ ((unsigned)&RXB1EIDH*8)+3;
static volatile bit RXB1EID10 @ ((unsigned)&RXB1EIDH*8)+2;
static volatile bit RXB1EID9 @ ((unsigned)&RXB1EIDH*8)+1;
static volatile bit RXB1EID8 @ ((unsigned)&RXB1EIDH*8)+0;
// RXB1SIDL Register
static volatile bit RXB1SID2 @ ((unsigned)&RXB1SIDL*8)+7;
static volatile bit RXB1SID1 @ ((unsigned)&RXB1SIDL*8)+6;
static volatile bit RXB1SID0 @ ((unsigned)&RXB1SIDL*8)+5;
static volatile bit RXB1SRR @ ((unsigned)&RXB1SIDL*8)+4;
static volatile bit RXB1EXID @ ((unsigned)&RXB1SIDL*8)+3;
static volatile bit RXB1EID17 @ ((unsigned)&RXB1SIDL*8)+1;
static volatile bit RXB1EID16 @ ((unsigned)&RXB1SIDL*8)+0;
// RXB1SIDH Register
static volatile bit RXB1SID10 @ ((unsigned)&RXB1SIDH*8)+7;
static volatile bit RXB1SID9 @ ((unsigned)&RXB1SIDH*8)+6;
static volatile bit RXB1SID8 @ ((unsigned)&RXB1SIDH*8)+5;
static volatile bit RXB1SID7 @ ((unsigned)&RXB1SIDH*8)+4;
static volatile bit RXB1SID6 @ ((unsigned)&RXB1SIDH*8)+3;
static volatile bit RXB1SID5 @ ((unsigned)&RXB1SIDH*8)+2;
static volatile bit RXB1SID4 @ ((unsigned)&RXB1SIDH*8)+1;
static volatile bit RXB1SID3 @ ((unsigned)&RXB1SIDH*8)+0;
// RXB1CON Register
static volatile bit RXB1FUL @ ((unsigned)&RXB1CON*8)+7; // recieve full status
static bit RXB1M1 @ ((unsigned)&RXB1CON*8)+6; // RX buffer mode
static bit RXB1M0 @ ((unsigned)&RXB1CON*8)+5;
static volatile bit RXB1RTRRO @ ((unsigned)&RXB1CON*8)+3; // RX remote transmit request
static volatile bit RXB1FILHIT2 @ ((unsigned)&RXB1CON*8)+2; // filter hit bits
static volatile bit RXB1FILHIT1 @ ((unsigned)&RXB1CON*8)+1;
static volatile bit RXB1FILHIT0 @ ((unsigned)&RXB1CON*8)+0;
// CANSTATRO2 Register
static volatile bit OPMODE22 @ ((unsigned)&CANSTATRO2*8)+7;
static volatile bit OPMODE21 @ ((unsigned)&CANSTATRO2*8)+6;
static volatile bit OPMODE20 @ ((unsigned)&CANSTATRO2*8)+5;
static volatile bit ICODE22 @ ((unsigned)&CANSTATRO2*8)+3;
static volatile bit ICODE21 @ ((unsigned)&CANSTATRO2*8)+2;
static volatile bit ICODE20 @ ((unsigned)&CANSTATRO2*8)+1;
// TXB0D7 Register
static bit TXB0D77 @ ((unsigned)&TXB0D7*8)+7;
static bit TXB0D76 @ ((unsigned)&TXB0D7*8)+6;
static bit TXB0D75 @ ((unsigned)&TXB0D7*8)+5;
static bit TXB0D74 @ ((unsigned)&TXB0D7*8)+4;
static bit TXB0D73 @ ((unsigned)&TXB0D7*8)+3;
static bit TXB0D72 @ ((unsigned)&TXB0D7*8)+2;
static bit TXB0D71 @ ((unsigned)&TXB0D7*8)+1;
static bit TXB0D70 @ ((unsigned)&TXB0D7*8)+0;
// TXB0D6 Register
static bit TXB0D67 @ ((unsigned)&TXB0D6*8)+7;
static bit TXB0D66 @ ((unsigned)&TXB0D6*8)+6;
static bit TXB0D65 @ ((unsigned)&TXB0D6*8)+5;
static bit TXB0D64 @ ((unsigned)&TXB0D6*8)+4;
static bit TXB0D63 @ ((unsigned)&TXB0D6*8)+3;
static bit TXB0D62 @ ((unsigned)&TXB0D6*8)+2;
static bit TXB0D61 @ ((unsigned)&TXB0D6*8)+1;
static bit TXB0D60 @ ((unsigned)&TXB0D6*8)+0;
// TXB0D5 Register
static bit TXB0D57 @ ((unsigned)&TXB0D5*8)+7;
static bit TXB0D56 @ ((unsigned)&TXB0D5*8)+6;
static bit TXB0D55 @ ((unsigned)&TXB0D5*8)+5;
static bit TXB0D54 @ ((unsigned)&TXB0D5*8)+4;
static bit TXB0D53 @ ((unsigned)&TXB0D5*8)+3;
static bit TXB0D52 @ ((unsigned)&TXB0D5*8)+2;
static bit TXB0D51 @ ((unsigned)&TXB0D5*8)+1;
static bit TXB0D50 @ ((unsigned)&TXB0D5*8)+0;
// TXB0D4 Register
static bit TXB0D47 @ ((unsigned)&TXB0D4*8)+7;
static bit TXB0D46 @ ((unsigned)&TXB0D4*8)+6;
static bit TXB0D45 @ ((unsigned)&TXB0D4*8)+5;
static bit TXB0D44 @ ((unsigned)&TXB0D4*8)+4;
static bit TXB0D43 @ ((unsigned)&TXB0D4*8)+3;
static bit TXB0D42 @ ((unsigned)&TXB0D4*8)+2;
static bit TXB0D41 @ ((unsigned)&TXB0D4*8)+1;
static bit TXB0D40 @ ((unsigned)&TXB0D4*8)+0;
// TXB0D3 Register
static bit TXB0D37 @ ((unsigned)&TXB0D3*8)+7;
static bit TXB0D36 @ ((unsigned)&TXB0D3*8)+6;
static bit TXB0D35 @ ((unsigned)&TXB0D3*8)+5;
static bit TXB0D34 @ ((unsigned)&TXB0D3*8)+4;
static bit TXB0D33 @ ((unsigned)&TXB0D3*8)+3;
static bit TXB0D32 @ ((unsigned)&TXB0D3*8)+2;
static bit TXB0D31 @ ((unsigned)&TXB0D3*8)+1;
static bit TXB0D30 @ ((unsigned)&TXB0D3*8)+0;
// TXB0D2 Register
static bit TXB0D27 @ ((unsigned)&TXB0D2*8)+7;
static bit TXB0D26 @ ((unsigned)&TXB0D2*8)+6;
static bit TXB0D25 @ ((unsigned)&TXB0D2*8)+5;
static bit TXB0D24 @ ((unsigned)&TXB0D2*8)+4;
static bit TXB0D23 @ ((unsigned)&TXB0D2*8)+3;
static bit TXB0D22 @ ((unsigned)&TXB0D2*8)+2;
static bit TXB0D21 @ ((unsigned)&TXB0D2*8)+1;
static bit TXB0D20 @ ((unsigned)&TXB0D2*8)+0;
// TXB0D1 Register
static bit TXB0D17 @ ((unsigned)&TXB0D1*8)+7;
static bit TXB0D16 @ ((unsigned)&TXB0D1*8)+6;
static bit TXB0D15 @ ((unsigned)&TXB0D1*8)+5;
static bit TXB0D14 @ ((unsigned)&TXB0D1*8)+4;
static bit TXB0D13 @ ((unsigned)&TXB0D1*8)+3;
static bit TXB0D12 @ ((unsigned)&TXB0D1*8)+2;
static bit TXB0D11 @ ((unsigned)&TXB0D1*8)+1;
static bit TXB0D10 @ ((unsigned)&TXB0D1*8)+0;
// TXB0D0 Register
static bit TXB0D07 @ ((unsigned)&TXB0D0*8)+7;
static bit TXB0D06 @ ((unsigned)&TXB0D0*8)+6;
static bit TXB0D05 @ ((unsigned)&TXB0D0*8)+5;
static bit TXB0D04 @ ((unsigned)&TXB0D0*8)+4;
static bit TXB0D03 @ ((unsigned)&TXB0D0*8)+3;
static bit TXB0D02 @ ((unsigned)&TXB0D0*8)+2;
static bit TXB0D01 @ ((unsigned)&TXB0D0*8)+1;
static bit TXB0D00 @ ((unsigned)&TXB0D0*8)+0;
// TXB0DLC Register
static bit TXB0RTR @ ((unsigned)&TXB0DLC*8)+6; // TX frame remote transmission request
static bit TXB0DLC3 @ ((unsigned)&TXB0DLC*8)+3; // data length code bits
static bit TXB0DLC2 @ ((unsigned)&TXB0DLC*8)+2;
static bit TXB0DLC1 @ ((unsigned)&TXB0DLC*8)+1;
static bit TXB0DLC0 @ ((unsigned)&TXB0DLC*8)+0;
// TXB0EIDL Register
static bit TXB0EID7 @ ((unsigned)&TXB0EIDL*8)+7; // extended identifier bits
static bit TXB0EID6 @ ((unsigned)&TXB0EIDL*8)+6;
static bit TXB0EID5 @ ((unsigned)&TXB0EIDL*8)+5;
static bit TXB0EID4 @ ((unsigned)&TXB0EIDL*8)+4;
static bit TXB0EID3 @ ((unsigned)&TXB0EIDL*8)+3;
static bit TXB0EID2 @ ((unsigned)&TXB0EIDL*8)+2;
static bit TXB0EID1 @ ((unsigned)&TXB0EIDL*8)+1;
static bit TXB0EID0 @ ((unsigned)&TXB0EIDL*8)+0;
// TXB0EIDH Register
static bit TXB0EID15 @ ((unsigned)&TXB0EIDH*8)+7; // extended identifier bits
static bit TXB0EID14 @ ((unsigned)&TXB0EIDH*8)+6;
static bit TXB0EID13 @ ((unsigned)&TXB0EIDH*8)+5;
static bit TXB0EID12 @ ((unsigned)&TXB0EIDH*8)+4;
static bit TXB0EID11 @ ((unsigned)&TXB0EIDH*8)+3;
static bit TXB0EID10 @ ((unsigned)&TXB0EIDH*8)+2;
static bit TXB0EID9 @ ((unsigned)&TXB0EIDH*8)+1;
static bit TXB0EID8 @ ((unsigned)&TXB0EIDH*8)+0;
// TXB0SIDL Register
static bit TXB0SID2 @ ((unsigned)&TXB0SIDL*8)+7; // standard identifier bits
static bit TXB0SID1 @ ((unsigned)&TXB0SIDL*8)+6;
static bit TXB0SID0 @ ((unsigned)&TXB0SIDL*8)+5;
static bit TXB0EXIDE @ ((unsigned)&TXB0SIDL*8)+3; // extended identifier enable
static bit TXB0EID17 @ ((unsigned)&TXB0SIDL*8)+1; // extended identifier bits
static bit TXB0EID16 @ ((unsigned)&TXB0SIDL*8)+0;
// TXB0SIDH Register
static bit TXB0SID10 @ ((unsigned)&TXB0SIDH*8)+7; // stanadard identifier bits
static bit TXB0SID9 @ ((unsigned)&TXB0SIDH*8)+6;
static bit TXB0SID8 @ ((unsigned)&TXB0SIDH*8)+5;
static bit TXB0SID7 @ ((unsigned)&TXB0SIDH*8)+4;
static bit TXB0SID6 @ ((unsigned)&TXB0SIDH*8)+3;
static bit TXB0SID5 @ ((unsigned)&TXB0SIDH*8)+2;
static bit TXB0SID4 @ ((unsigned)&TXB0SIDH*8)+1;
static bit TXB0SID3 @ ((unsigned)&TXB0SIDH*8)+0;
// TXB0CON Register
static volatile bit TXB0ABT @ ((unsigned)&TXB0CON*8)+6; // TX abort status
static volatile bit TXB0LARB @ ((unsigned)&TXB0CON*8)+5; // TX lost arbitration status
static volatile bit TXB0ERR @ ((unsigned)&TXB0CON*8)+4; // TX error detect
static volatile bit TXB0REQ @ ((unsigned)&TXB0CON*8)+3; // TX request status
static bit TXB0PRI1 @ ((unsigned)&TXB0CON*8)+1; // TX priority bits
static bit TXB0PRI0 @ ((unsigned)&TXB0CON*8)+0;
// CANSTATRO3 Register
static volatile bit OPMODE32 @ ((unsigned)&CANSTATRO3*8)+7;
static volatile bit OPMODE⌨️ 快捷键说明
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