pic18fxx8.h

使用微芯公司的PIC8F458单片机

static		near bit 	TXB2IP	@ ((unsigned)&IPR3*8)+4;	// CAN TX buffer 2 interrupt priority
static		near bit 	TXB1IP	@ ((unsigned)&IPR3*8)+3;	// CAN TX buffer 1 interrupt priority
static		near bit 	TXB0IP	@ ((unsigned)&IPR3*8)+2;	// CAN TX buffer 0 interrupt priority
static		near bit 	RXB1IP	@ ((unsigned)&IPR3*8)+1;	// CAN RX buffer 1 interrupt priority
static		near bit 	RXB0IP	@ ((unsigned)&IPR3*8)+0;	// CAN RX buffer 0 interrupt priority	     

// PIR3 Register
static volatile	near bit	IRXIF	@ ((unsigned)&PIR3*8)+7;	// CAN invalid rec. message interrupt flag
static volatile	near bit	WAKIF	@ ((unsigned)&PIR3*8)+6;	// CANbus activity wake-up interrupt flag
static volatile	near bit	ERRIF	@ ((unsigned)&PIR3*8)+5;	// CANbus error interrupt flag
static volatile	near bit	TXB2IF	@ ((unsigned)&PIR3*8)+4;	// CAN TX buffer 2 interrupt flag
static volatile	near bit	TXB1IF	@ ((unsigned)&PIR3*8)+3;	// CAN TX buffer 1 interrupt flag
static volatile	near bit	TXB0IF	@ ((unsigned)&PIR3*8)+2;	// CAN TX buffer 0 interrupt flag
static volatile	near bit	RXB1IF	@ ((unsigned)&PIR3*8)+1;	// CAN RX buffer 1 interrupt flag
static volatile	near bit	RXB0IF	@ ((unsigned)&PIR3*8)+0;	// CAN RX buffer 0 interrupt flag		

// PIE3 Register
static		near bit 	IRXIE  	@ ((unsigned)&PIE3*8)+7;	// CAN invalid rec. message interrupt enable
static		near bit 	WAKIE  	@ ((unsigned)&PIE3*8)+6;	// CANbus activity wake-up interrupt enable
static		near bit 	ERRIE  	@ ((unsigned)&PIE3*8)+5;	// CANbus error interrupt enable
static		near bit 	TXB2IE	@ ((unsigned)&PIE3*8)+4;	// CAN TX buffer 2 interrupt enable
static		near bit 	TXB1IE	@ ((unsigned)&PIE3*8)+3;	// CAN TX buffer 1 interrupt enable
static		near bit 	TXB0IE	@ ((unsigned)&PIE3*8)+2;	// CAN TX buffer 0 interrupt enable
static		near bit 	RXB1IE	@ ((unsigned)&PIE3*8)+1;	// CAN RX buffer 1 interrupt enable
static		near bit 	RXB0IE	@ ((unsigned)&PIE3*8)+0;	// CAN RX buffer 0 interrupt enable	     

// IPR2 Register
static		near bit 	CMIP	@ ((unsigned)&IPR2*8)+6;	// comparator interrupt priority		
static		near bit 	EEIP	@ ((unsigned)&IPR2*8)+4;	// EEPROM write interrupt priority
static		near bit 	BCLIP	@ ((unsigned)&IPR2*8)+3;	// bus collision interrupt priority
static		near bit 	LVDIP	@ ((unsigned)&IPR2*8)+2;	// low voltage detect interrupt priority
static		near bit 	TMR3IP	@ ((unsigned)&IPR2*8)+1;	// TMR3 overflow interrupt priority
#if defined(_18F448) || defined(_18F458)
static		near bit 	ECCP1IP	@ ((unsigned)&IPR2*8)+0;	// ECCP1 interrupt priority
#endif

// PIR2 Register
static volatile	near bit	CMIF 	@ ((unsigned)&PIR2*8)+6;	// comparator interrupt flag		
static volatile	near bit	EEIF 	@ ((unsigned)&PIR2*8)+4;	// EEPROM write interrupt flag
static volatile	near bit	BCLIF 	@ ((unsigned)&PIR2*8)+3;	// bus collision interrupt flag
static volatile	near bit	LVDIF 	@ ((unsigned)&PIR2*8)+2;	// low voltage detect interrupt flag
static volatile	near bit	TMR3IF 	@ ((unsigned)&PIR2*8)+1;	// TMR3 overflow interrupt flag
#if defined(_18F448) || defined(_18F458)
static volatile	near bit	ECCP1IF	@ ((unsigned)&PIR2*8)+0;	// ECCP1 interrupt flag
#endif

// PIE2 Register
static		near bit 	CMIE 	@ ((unsigned)&PIE2*8)+6;	// comparator interrupt enable		
static		near bit 	EEIE 	@ ((unsigned)&PIE2*8)+4;	// EEPROM write interrupt enable
static		near bit 	BCLIE 	@ ((unsigned)&PIE2*8)+3;	// bus collision interrupt enable
static		near bit 	LVDIE 	@ ((unsigned)&PIE2*8)+2;	// low voltage detect interrupt enable
static		near bit 	TMR3IE 	@ ((unsigned)&PIE2*8)+1;	// TMR3 overflow interrupt enable
#if defined(_18F448) || defined(_18F458)
static		near bit 	ECCP1IE	@ ((unsigned)&PIE2*8)+0;	// ECCP1 interrupt enable
#endif

// IPR1 Register
#if defined(_18F448) || defined(_18F458)
static		near bit 	PSPIP	@ ((unsigned)&IPR1*8)+7;	// para. slave port rd/wr interrupt priority
#endif
static		near bit 	ADIP	@ ((unsigned)&IPR1*8)+6;	// AD conv. interrupt priority
static		near bit 	RCIP	@ ((unsigned)&IPR1*8)+5;	// USART RX interrupt priority
static		near bit 	TXIP	@ ((unsigned)&IPR1*8)+4;	// USART TX interrupt priority
static		near bit 	SSPIP	@ ((unsigned)&IPR1*8)+3;	// master SSP interrupt priority
static		near bit 	CCP1IP	@ ((unsigned)&IPR1*8)+2;	// CCP1 interrupt priority
static		near bit 	TMR2IP	@ ((unsigned)&IPR1*8)+1;	// TMR2 - PR2 match interrupt priority
static		near bit 	TMR1IP	@ ((unsigned)&IPR1*8)+0;	// TMR1 overflow interrupt priority

// PIR1 Register
#if defined(_18F448) || defined(_18F458)
static volatile	near bit	PSPIF  	@ ((unsigned)&PIR1*8)+7;	// para. slave port rd/wr interrupt flag
#endif
static volatile	near bit	ADIF  	@ ((unsigned)&PIR1*8)+6;	// AD conv. interrupt flag
static volatile	near bit	RCIF  	@ ((unsigned)&PIR1*8)+5;	// USART RX interrupt flag
static volatile	near bit	TXIF  	@ ((unsigned)&PIR1*8)+4;	// USART TX interrupt flag
static volatile	near bit	SSPIF  	@ ((unsigned)&PIR1*8)+3;	// master SSP interrupt flag
static volatile	near bit	CCP1IF	@ ((unsigned)&PIR1*8)+2;	// CCP1 interrupt flag
static volatile	near bit	TMR2IF	@ ((unsigned)&PIR1*8)+1;	// TMR2 - PR2 match interrupt flag
static volatile	near bit	TMR1IF	@ ((unsigned)&PIR1*8)+0;	// TMR1 overflow interrupt flag

// PIE1 Register
#if defined(_18F448) || defined(_18F458)
static		near bit 	PSPIE  	@ ((unsigned)&PIE1*8)+7;	// para. slave port rd/wr interrupt enable
#endif
static		near bit 	ADIE  	@ ((unsigned)&PIE1*8)+6;	// AD conv. interrupt enable
static		near bit 	RCIE  	@ ((unsigned)&PIE1*8)+5;	// USART RX interrupt enable
static		near bit 	TXIE  	@ ((unsigned)&PIE1*8)+4;	// USART TX interrupt enable
static		near bit 	SSPIE  	@ ((unsigned)&PIE1*8)+3;	// master SSP interrupt enable
static		near bit 	CCP1IE	@ ((unsigned)&PIE1*8)+2;	// CCP1 interrupt enable
static		near bit 	TMR2IE	@ ((unsigned)&PIE1*8)+1;	// TMR2 - PR2 match interrupt enable
static		near bit 	TMR1IE	@ ((unsigned)&PIE1*8)+0;	// TMR1 overflow interrupt enable

#if defined(_18F448) || defined(_18F458)
// TRISE Register
static volatile	near bit	IBF	@ ((unsigned)&TRISE*8)+7;	// input buffer full status
static volatile	near bit	OBF	@ ((unsigned)&TRISE*8)+6;	// output buffer full status
static volatile	near bit	IBOV	@ ((unsigned)&TRISE*8)+5;	// input buffer overflow
static		near bit	PSPMODE	@ ((unsigned)&TRISE*8)+4;	// parallel slave port mode select
static volatile near bit	TRISE2	@ ((unsigned)&TRISE*8)+2;	// port E data direction
static volatile near bit	TRISE1	@ ((unsigned)&TRISE*8)+1;
static volatile near bit	TRISE0	@ ((unsigned)&TRISE*8)+0;

// TRISD Register
static volatile near bit 	TRISD7	@ ((unsigned)&TRISD*8)+7;	// port D data direction
static volatile near bit 	TRISD6	@ ((unsigned)&TRISD*8)+6;
static volatile near bit 	TRISD5	@ ((unsigned)&TRISD*8)+5;
static volatile near bit 	TRISD4	@ ((unsigned)&TRISD*8)+4;
static volatile near bit 	TRISD3	@ ((unsigned)&TRISD*8)+3;
static volatile near bit 	TRISD2	@ ((unsigned)&TRISD*8)+2;
static volatile near bit 	TRISD1	@ ((unsigned)&TRISD*8)+1;
static volatile near bit 	TRISD0	@ ((unsigned)&TRISD*8)+0;
#endif

// TRISC Register
static volatile near bit 	TRISC7	@ ((unsigned)&TRISC*8)+7;	// port C data direction
static volatile near bit 	TRISC6	@ ((unsigned)&TRISC*8)+6;
static volatile near bit 	TRISC5	@ ((unsigned)&TRISC*8)+5;
static volatile near bit 	TRISC4	@ ((unsigned)&TRISC*8)+4;
static volatile near bit 	TRISC3	@ ((unsigned)&TRISC*8)+3;
static volatile near bit 	TRISC2	@ ((unsigned)&TRISC*8)+2;
static volatile near bit 	TRISC1	@ ((unsigned)&TRISC*8)+1;
static volatile near bit 	TRISC0	@ ((unsigned)&TRISC*8)+0;

// TRISB Register
static volatile near bit 	TRISB7	@ ((unsigned)&TRISB*8)+7;	// port B data direction
static volatile near bit 	TRISB6	@ ((unsigned)&TRISB*8)+6;
static volatile near bit 	TRISB5	@ ((unsigned)&TRISB*8)+5;
static volatile near bit 	TRISB4	@ ((unsigned)&TRISB*8)+4;
static volatile near bit 	TRISB3	@ ((unsigned)&TRISB*8)+3;
static volatile near bit 	TRISB2	@ ((unsigned)&TRISB*8)+2;
static volatile near bit 	TRISB1	@ ((unsigned)&TRISB*8)+1;
static volatile near bit 	TRISB0	@ ((unsigned)&TRISB*8)+0;

// TRISA Register
static volatile near bit 	TRISA7	@ ((unsigned)&TRISA*8)+7;	// port A data direction
static volatile near bit 	TRISA6	@ ((unsigned)&TRISA*8)+6;
static volatile near bit 	TRISA5	@ ((unsigned)&TRISA*8)+5;
static volatile near bit 	TRISA4	@ ((unsigned)&TRISA*8)+4;
static volatile near bit 	TRISA3	@ ((unsigned)&TRISA*8)+3;
static volatile near bit 	TRISA2	@ ((unsigned)&TRISA*8)+2;
static volatile near bit 	TRISA1	@ ((unsigned)&TRISA*8)+1;
static volatile near bit 	TRISA0	@ ((unsigned)&TRISA*8)+0;

#if defined(_18F448) || defined(_18F458)
// LATE Register
static volatile near bit	LATE2	@ ((unsigned)&LATE*8)+2;	// port E data latch
static volatile near bit	LATE1	@ ((unsigned)&LATE*8)+1;
static volatile near bit	LATE0	@ ((unsigned)&LATE*8)+0;

// LATD Register
static volatile near bit 	LATD7	@ ((unsigned)&LATD*8)+7;	// port D data latch
static volatile near bit 	LATD6	@ ((unsigned)&LATD*8)+6;
static volatile near bit 	LATD5	@ ((unsigned)&LATD*8)+5;
static volatile near bit 	LATD4	@ ((unsigned)&LATD*8)+4;
static volatile near bit 	LATD3	@ ((unsigned)&LATD*8)+3;
static volatile near bit 	LATD2	@ ((unsigned)&LATD*8)+2;
static volatile near bit 	LATD1	@ ((unsigned)&LATD*8)+1;
static volatile near bit 	LATD0	@ ((unsigned)&LATD*8)+0;
#endif

// LATC Register
static volatile near bit 	LATC7	@ ((unsigned)&LATC*8)+7;	// port C data latch
static volatile near bit 	LATC6	@ ((unsigned)&LATC*8)+6;
static volatile near bit 	LATC5	@ ((unsigned)&LATC*8)+5;
static volatile near bit 	LATC4	@ ((unsigned)&LATC*8)+4;
static volatile near bit 	LATC3	@ ((unsigned)&LATC*8)+3;
static volatile near bit 	LATC2	@ ((unsigned)&LATC*8)+2;
static volatile near bit 	LATC1	@ ((unsigned)&LATC*8)+1;
static volatile near bit 	LATC0	@ ((unsigned)&LATC*8)+0;

// LATB Register
static volatile near bit 	LATB7	@ ((unsigned)&LATB*8)+7;	// port B data latch
static volatile near bit 	LATB6	@ ((unsigned)&LATB*8)+6;
static volatile near bit 	LATB5	@ ((unsigned)&LATB*8)+5;
static volatile near bit 	LATB4	@ ((unsigned)&LATB*8)+4;
static volatile near bit 	LATB3	@ ((unsigned)&LATB*8)+3;
static volatile near bit 	LATB2	@ ((unsigned)&LATB*8)+2;
static volatile near bit 	LATB1	@ ((unsigned)&LATB*8)+1;
static volatile near bit 	LATB0	@ ((unsigned)&LATB*8)+0;

// LATA Register
static volatile near bit 	LATA7	@ ((unsigned)&LATA*8)+7;	// port A data latch
static volatile near bit 	LATA6	@ ((unsigned)&LATA*8)+6;
static volatile near bit 	LATA5	@ ((unsigned)&LATA*8)+5;
static volatile near bit 	LATA4	@ ((unsigned)&LATA*8)+4;
static volatile near bit 	LATA3	@ ((unsigned)&LATA*8)+3;
static volatile near bit 	LATA2	@ ((unsigned)&LATA*8)+2;
static volatile near bit 	LATA1	@ ((unsigned)&LATA*8)+1;
static volatile near bit 	LATA0	@ ((unsigned)&LATA*8)+0;

#if defined(_18F448) || defined(_18F458)
// PORTE Register
static volatile	near bit	RE2	@ ((unsigned)&PORTE*8)+2;
static volatile	near bit	RE1	@ ((unsigned)&PORTE*8)+1;
static volatile	near bit	RE0	@ ((unsigned)&PORTE*8)+0;

// PORTD Register
static volatile	near bit	RD7	@ ((unsigned)&PORTD*8)+7;
static volatile	near bit	RD6	@ ((unsigned)&PORTD*8)+6;
static volatile	near bit	RD5	@ ((unsigned)&PORTD*8)+5;
static volatile	near bit	RD4	@ ((unsigned)&PORTD*8)+4;
static volatile	near bit	RD3	@ ((unsigned)&PORTD*8)+3;
static volatile	near bit	RD2	@ ((unsigned)&PORTD*8)+2;
static volatile	near bit	RD1	@ ((unsigned)&PORTD*8)+1;
static volatile	near bit	RD0	@ ((unsigned)&PORTD*8)+0;
#endif

// PORTC Register
static volatile	near bit	RC7	@ ((unsigned)&PORTC*8)+7;
static volatile	near bit	RC6	@ ((unsigned)&PORTC*8)+6;
static volatile	near bit	RC5	@ ((unsigned)&PORTC*8)+5;
static volatile	near bit	RC4	@ ((unsigned)&PORTC*8)+4;
static volatile	near bit	RC3	@ ((unsigned)&PORTC*8)+3;
static volatile	near bit	RC2	@ ((unsigned)&PORTC*8)+2;
static volatile	near bit	RC1	@ ((unsigned)&PORTC*8)+1;
static volatile	near bit	RC0	@ ((unsigned)&PORTC*8)+0;

// PORTB Register
static volatile	near bit	RB7	@ ((unsigned)&PORTB*8)+7;
static volatile	near bit	RB6	@ ((unsigned)&PORTB*8)+6;
static volatile	near bit	RB5	@ ((unsigned)&PORTB*8)+5;
static volatile	near bit	RB4	@ ((unsigned)&PORTB*8)+4;
static volatile	near bit	RB3	@ ((unsigned)&PORTB*8)+3;
static volatile	near bit	RB2	@ ((unsigned)&PORTB*8)+2;
static volatile	near bit	RB1	@ ((unsigned)&PORTB*8)+1;
static volatile	near bit	RB0	@ ((unsigned)&PORTB*8)+0;

// PORTA Register
static volatile	near bit	RA7	@ ((unsigned)&PORTA*8)+7;
static volatile	near bit	RA6	@ ((unsigned)&PORTA*8)+6;
static volatile	near bit	RA5	@ ((unsigned)&PORTA*8)+5;
static volatile	near bit	RA4	@ ((unsigned)&PORTA*8)+4;
static volatile	near bit	RA3	@ ((unsigned)&PORTA*8)+3;
static volatile	near bit	RA2	@ ((unsigned)&PORTA*8)+2;
static volatile	near bit	RA1	@ ((unsigned)&PORTA*8)+1;
static volatile	near bit	RA0	@ ((unsigned)&PORTA*8)+0;

// TXERRCNT Register
static volatile	near bit	TEC7	@ ((unsigned)&TXERRCNT*8)+7;	// TX error count bits
static volatile	near bit	TEC6	@ ((unsigned)&TXERRCNT*8)+6;
static volatile	near bit	TEC5	@ ((unsigned)&TXERRCNT*8)+5;
static volatile	near bit	TEC4	@ ((unsigned)&TXERRCNT*8)+4;
static volatile	near bit	TEC3	@ ((unsigned)&TXERRCNT*8)+3;
static volatile	near bit	TEC2	@ ((unsigned)&TXERRCNT*8)+2;
static volatile	near bit	TEC1	@ ((unsigned)&TXERRCNT*8)+1;
static volatile	near bit	TEC0	@ ((unsigned)&TXERRCNT*8)+0;