📄 pic18fxx8.h
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static unsigned char RXF0EIDH @ 0xF02;
static unsigned char RXF0SIDL @ 0xF01;
static unsigned char RXF0SIDH @ 0xF00;
//Defining individual bits
// STKPTR Register
static volatile near bit STKFUL @ ((unsigned)&STKPTR*8)+7; // stack full flag
static volatile near bit STKUNF @ ((unsigned)&STKPTR*8)+6; // stack underflow flag
// INTCON Register
static near bit GIE @ ((unsigned)&INTCON*8)+7; // global interrupt enable
static near bit GIEH @ ((unsigned)&INTCON*8)+7; // enable high priority interrupts
static near bit PEIE @ ((unsigned)&INTCON*8)+6; // peripheral interrupt enable
static near bit GIEL @ ((unsigned)&INTCON*8)+6; // enable low priority peripheral interrupts
static near bit TMR0IE @ ((unsigned)&INTCON*8)+5; // TMR0 overflow interrupt enable
static near bit INT0IE @ ((unsigned)&INTCON*8)+4; // external interrupt 0 enable
static near bit RBIE @ ((unsigned)&INTCON*8)+3; // RB port change interrupt enable
static volatile near bit TMR0IF @ ((unsigned)&INTCON*8)+2; // TMR0 overflow interrupt flag
static volatile near bit INT0IF @ ((unsigned)&INTCON*8)+1; // external interrupt 0 flag
static volatile near bit RBIF @ ((unsigned)&INTCON*8)+0; // RB port change interrupt flag
// INTCON2 Register
static near bit RBPU @ ((unsigned)&INTCON2*8)+7; // port B pull-up enable
static near bit INTEDG0 @ ((unsigned)&INTCON2*8)+6; // external interrupt 0 edge select
static near bit INTEDG1 @ ((unsigned)&INTCON2*8)+5; // external interrupt 1 edge select
static near bit INTEDG2 @ ((unsigned)&INTCON2*8)+4; // external interrupt 2 edge select
static near bit TMR0IP @ ((unsigned)&INTCON2*8)+2; // TMR0 overflow interrupt priority
static near bit RBIP @ ((unsigned)&INTCON2*8)+0; // RB port change interrupt priority
// INTCON3 Register
static near bit INT2IP @ ((unsigned)&INTCON3*8)+7; // external interrupt 2 priority
static near bit INT1IP @ ((unsigned)&INTCON3*8)+6; // external interrupt 1 priority
static near bit INT2IE @ ((unsigned)&INTCON3*8)+4; // external interrupt 2 enable
static near bit INT1IE @ ((unsigned)&INTCON3*8)+3; // external interrupt 1 enable
static volatile near bit INT2IF @ ((unsigned)&INTCON3*8)+1; // external interrupt 2 flag
static volatile near bit INT1IF @ ((unsigned)&INTCON3*8)+0; // external interrupt 1 flag
// STATUS Register
static volatile near bit NEGATIVE @ ((unsigned)&STATUS*8)+4; // negative result
static volatile near bit OV @ ((unsigned)&STATUS*8)+3; // overflow status
static volatile near bit ZERO @ ((unsigned)&STATUS*8)+2; // zero result
static volatile near bit DC @ ((unsigned)&STATUS*8)+1; // digit carry
static volatile near bit CARRY @ ((unsigned)&STATUS*8)+0; // carry/borrow
// T0CON Register
static near bit TMR0ON @ ((unsigned)&T0CON*8)+7; // TMR0 on/off
static near bit T08BIT @ ((unsigned)&T0CON*8)+6; // 8/16 bit select
static near bit T0CS @ ((unsigned)&T0CON*8)+5; // TMR0 Source Select
static near bit T0SE @ ((unsigned)&T0CON*8)+4; // TMR0 Source Edge Select
static near bit PSA @ ((unsigned)&T0CON*8)+3; // Prescaler Assignment
static near bit T0PS2 @ ((unsigned)&T0CON*8)+2; // Prescaler
static near bit T0PS1 @ ((unsigned)&T0CON*8)+1;
static near bit T0PS0 @ ((unsigned)&T0CON*8)+0;
// OSCCON Register
static near bit SCS @ ((unsigned)&OSCCON*8)+0; // system clock switch bit
// LVDCON Register
static volatile near bit IRVST @ ((unsigned)&LVDCON*8)+5; // input reference voltage stable status
static near bit LVDEN @ ((unsigned)&LVDCON*8)+4; // low voltage detect enable
static near bit LVDL3 @ ((unsigned)&LVDCON*8)+3; // low voltage detection limits
static near bit LVDL2 @ ((unsigned)&LVDCON*8)+2;
static near bit LVDL1 @ ((unsigned)&LVDCON*8)+1;
static near bit LVDL0 @ ((unsigned)&LVDCON*8)+0;
// WDTCON Register
static near bit SWDTEN @ ((unsigned)&WDTCON*8)+0; // software watchdog timer enable
// RCON Register
static near bit IPEN @ ((unsigned)&RCON*8)+7; // interrupt priority enable
static volatile near bit RI @ ((unsigned)&RCON*8)+4; // RESET instruction status
static volatile near bit TO @ ((unsigned)&RCON*8)+3; // watchdog timeout flag
static volatile near bit PD @ ((unsigned)&RCON*8)+2; // power-down detection
static volatile near bit POR @ ((unsigned)&RCON*8)+1; // power-on reset status
static volatile near bit BOR @ ((unsigned)&RCON*8)+0; // brown-our reset status
// T1CON Register
static near bit RD16 @ ((unsigned)&T1CON*8)+7; // 16 Bit Read/Write Enable
static near bit T1RD16 @ ((unsigned)&T1CON*8)+7; // 16 Bit Read/Write Enable
static near bit T1CKPS1 @ ((unsigned)&T1CON*8)+5; // Prescaler
static near bit T1CKPS0 @ ((unsigned)&T1CON*8)+4;
static near bit T1OSCEN @ ((unsigned)&T1CON*8)+3; // Oscillator Enable
static near bit T1SYNC @ ((unsigned)&T1CON*8)+2; // Sync Selct
static near bit TMR1CS @ ((unsigned)&T1CON*8)+1; // TMR Clock Source Select
static near bit TMR1ON @ ((unsigned)&T1CON*8)+0; // TMR on/off
// T2CON Register
static near bit TOUTPS3 @ ((unsigned)&T2CON*8)+6; // Postscale
static near bit TOUTPS2 @ ((unsigned)&T2CON*8)+5;
static near bit TOUTPS1 @ ((unsigned)&T2CON*8)+4;
static near bit TOUTPS0 @ ((unsigned)&T2CON*8)+3;
static near bit TMR2ON @ ((unsigned)&T2CON*8)+2; // TMR2 On/Off
static near bit T2CKPS1 @ ((unsigned)&T2CON*8)+1; // Prescale
static near bit T2CKPS0 @ ((unsigned)&T2CON*8)+0;
// SSPSTAT Register
static volatile near bit SMP @ ((unsigned)&SSPSTAT*8)+7; // Sample Bit
static near bit CKE @ ((unsigned)&SSPSTAT*8)+6; // SPI Clk Edge Select
static volatile near bit DA @ ((unsigned)&SSPSTAT*8)+5; // Data/Address Bit
static volatile near bit STOP @ ((unsigned)&SSPSTAT*8)+4; // STOP Bit detected
static volatile near bit START @ ((unsigned)&SSPSTAT*8)+3; // START Bit detected
static volatile near bit RW @ ((unsigned)&SSPSTAT*8)+2; // Read/Write bit Information
static volatile near bit UA @ ((unsigned)&SSPSTAT*8)+1; // Update Adress
static volatile near bit BF @ ((unsigned)&SSPSTAT*8)+0; // Buffer Full Status bit
// SSPCON1 Register
static volatile near bit WCOL @ ((unsigned)&SSPCON1*8)+7; // write collision detect
static volatile near bit SSPOV @ ((unsigned)&SSPCON1*8)+6; // recieve overflow indicator
static near bit SSPEN @ ((unsigned)&SSPCON1*8)+5; // SSP enable
static near bit CKP @ ((unsigned)&SSPCON1*8)+4; // clock polarity select
static near bit SSPM3 @ ((unsigned)&SSPCON1*8)+3; // SSP mode select
static near bit SSPM2 @ ((unsigned)&SSPCON1*8)+2;
static near bit SSPM1 @ ((unsigned)&SSPCON1*8)+1;
static near bit SSPM0 @ ((unsigned)&SSPCON1*8)+0;
// SSPCON2 Register
static near bit GCEN @ ((unsigned)&SSPCON2*8)+7; // general call enable
static volatile near bit ACKSTAT @ ((unsigned)&SSPCON2*8)+6; // acknowledge status bit
static volatile near bit ACKDT @ ((unsigned)&SSPCON2*8)+5; // acknowledge data bit
static volatile near bit ACKEN @ ((unsigned)&SSPCON2*8)+4; // acknowledge sequence enable
static near bit RCEN @ ((unsigned)&SSPCON2*8)+3; // recieve enable bit
static volatile near bit PEN @ ((unsigned)&SSPCON2*8)+2; // STOP condition enable
static volatile near bit RSEN @ ((unsigned)&SSPCON2*8)+1; // repeated START enable
static volatile near bit SEN @ ((unsigned)&SSPCON2*8)+0; // START condition enable
// ADCON0 Register
static near bit ADCS1 @ ((unsigned)&ADCON0*8)+7; // AD conv. clock select bits
static near bit ADCS0 @ ((unsigned)&ADCON0*8)+6;
static near bit CHS2 @ ((unsigned)&ADCON0*8)+5; // channel select
static near bit CHS1 @ ((unsigned)&ADCON0*8)+4;
static near bit CHS0 @ ((unsigned)&ADCON0*8)+3;
static volatile near bit GODONE @ ((unsigned)&ADCON0*8)+2; // AD conversion status
static near bit ADON @ ((unsigned)&ADCON0*8)+0; // AD on status
// ADCON1 Register
static near bit ADFM @ ((unsigned)&ADCON1*8)+7; // AD result format
static near bit ADCS2 @ ((unsigned)&ADCON1*8)+6; // AD conv. clock select bits
static near bit PCFG3 @ ((unsigned)&ADCON1*8)+3; // AD port config bits
static near bit PCFG2 @ ((unsigned)&ADCON1*8)+2;
static near bit PCFG1 @ ((unsigned)&ADCON1*8)+1;
static near bit PCFG0 @ ((unsigned)&ADCON1*8)+0;
// CCP1CON Register
static volatile near bit DC1B1 @ ((unsigned)&CCP1CON*8)+5; // Duty Cycle Bits 1 & 0
static volatile near bit DC1B0 @ ((unsigned)&CCP1CON*8)+4;
static near bit CCP1M3 @ ((unsigned)&CCP1CON*8)+3; // Mode Select Bits
static near bit CCP1M2 @ ((unsigned)&CCP1CON*8)+2;
static near bit CCP1M1 @ ((unsigned)&CCP1CON*8)+1;
static near bit CCP1M0 @ ((unsigned)&CCP1CON*8)+0;
#if defined(_18F448) || defined(_18F458)
// ECCP1CON Register
static near bit EPWM1M1 @ ((unsigned)&ECCP1CON*8)+7; // PWM output config bits
static near bit EPWM1M0 @ ((unsigned)&ECCP1CON*8)+6;
static volatile near bit EDC1B1 @ ((unsigned)&ECCP1CON*8)+5; // PWM duty cycle LSBs
static volatile near bit EDC1B0 @ ((unsigned)&ECCP1CON*8)+4;
static near bit ECCP1M3 @ ((unsigned)&ECCP1CON*8)+3; // EEPC1 mode select bits
static near bit ECCP1M2 @ ((unsigned)&ECCP1CON*8)+2;
static near bit ECCP1M1 @ ((unsigned)&ECCP1CON*8)+1;
static near bit ECCP1M0 @ ((unsigned)&ECCP1CON*8)+0;
// ECCP1DEL Register
static near bit EPDC7 @ ((unsigned)&ECCP1DEL*8)+7; // PWM delay
static near bit EPDC6 @ ((unsigned)&ECCP1DEL*8)+6;
static near bit EPDC5 @ ((unsigned)&ECCP1DEL*8)+5;
static near bit EPDC4 @ ((unsigned)&ECCP1DEL*8)+4;
static near bit EPDC3 @ ((unsigned)&ECCP1DEL*8)+3;
static near bit EPDC2 @ ((unsigned)&ECCP1DEL*8)+2;
static near bit EPDC1 @ ((unsigned)&ECCP1DEL*8)+1;
static near bit EPDC0 @ ((unsigned)&ECCP1DEL*8)+0;
// ECCPAS Register
static volatile near bit ECCPASE @ ((unsigned)&ECCPAS*8)+7; // ECCP auto-shutdown event status
static near bit ECCPAS2 @ ((unsigned)&ECCPAS*8)+6; // EECP auto-shutdown bits
static near bit ECCPAS1 @ ((unsigned)&ECCPAS*8)+5;
static near bit ECCPAS0 @ ((unsigned)&ECCPAS*8)+4;
static near bit PSSAC1 @ ((unsigned)&ECCPAS*8)+3; // pin A & C auto-shutdown control
static near bit PSSAC0 @ ((unsigned)&ECCPAS*8)+2;
static near bit PCCBD1 @ ((unsigned)&ECCPAS*8)+1; // pin B & D auto-shutdown control
static near bit PCCBD0 @ ((unsigned)&ECCPAS*8)+0;
// CVRCON Register
static near bit CVREN @ ((unsigned)&CVRCON*8)+7; // comparator voltage reference enable
static near bit CVROE @ ((unsigned)&CVRCON*8)+6; // comparator VREF output enable
static near bit CVRR @ ((unsigned)&CVRCON*8)+5; // comparator VREF range select
static near bit CVRSS @ ((unsigned)&CVRCON*8)+4; // comparator VREF source select
static near bit CVR3 @ ((unsigned)&CVRCON*8)+3; // comparator VREF value selection
static near bit CVR2 @ ((unsigned)&CVRCON*8)+2;
static near bit CVR1 @ ((unsigned)&CVRCON*8)+1;
static near bit CVR0 @ ((unsigned)&CVRCON*8)+0;
// CMCON Comparator module register
static volatile near bit C2OUT @ ((unsigned)&CMCON*8)+7; // comparator 2 output
static volatile near bit C1OUT @ ((unsigned)&CMCON*8)+6; // comparator 1 output
static near bit C2INV @ ((unsigned)&CMCON*8)+5; // select to invert comp2 output
static near bit C1INV @ ((unsigned)&CMCON*8)+4; // select to invert comp1 output
static near bit CIS @ ((unsigned)&CMCON*8)+3; // comp input switch bit
static near bit CM2 @ ((unsigned)&CMCON*8)+2; // comp mode select bits
static near bit CM1 @ ((unsigned)&CMCON*8)+1;
static near bit CM0 @ ((unsigned)&CMCON*8)+0;
#endif
// T3CON Register
static near bit T3RD16 @ ((unsigned)&T3CON*8)+7; // 16-Bit Read/Write select
static near bit T3ECCP1 @ ((unsigned)&T3CON*8)+6; // TMR3 & TMR1 CCPx Enable
static near bit T3CKPS1 @ ((unsigned)&T3CON*8)+5; // Prescaler
static near bit T3CKPS0 @ ((unsigned)&T3CON*8)+4;
static near bit T3CCP1 @ ((unsigned)&T3CON*8)+3; // TMR3 & TMR1 CCPx Enable
static near bit T3SYNC @ ((unsigned)&T3CON*8)+2; // Sync Select
static near bit TMR3CS @ ((unsigned)&T3CON*8)+1; // TMR3 source Select
static near bit TMR3ON @ ((unsigned)&T3CON*8)+0; // TMR3 on/off
// TXSTA Register
static near bit CSRC @ ((unsigned)&TXSTA*8)+7; // CLK source select
static near bit TX9 @ ((unsigned)&TXSTA*8)+6; // 8/9 bit TX data select
static near bit TXEN @ ((unsigned)&TXSTA*8)+5; // transmit enable bit
static near bit SYNC @ ((unsigned)&TXSTA*8)+4; // USART mode select
static near bit BRGH @ ((unsigned)&TXSTA*8)+2; // high baud rate select
static volatile near bit TRMT @ ((unsigned)&TXSTA*8)+1; // TX shift reg. status bit
static near bit TX9D @ ((unsigned)&TXSTA*8)+0; // 9th Bit of TX data
// RCSTA Register
static near bit SPEN @ ((unsigned)&RCSTA*8)+7; // serial port enable
static near bit RX9 @ ((unsigned)&RCSTA*8)+6; // 8/9 bit data reception
static near bit SREN @ ((unsigned)&RCSTA*8)+5; // single recieve enable
static near bit CREN @ ((unsigned)&RCSTA*8)+4; // continuous recieve enable
static near bit ADDEN @ ((unsigned)&RCSTA*8)+3; // address detect enable
static volatile near bit FERR @ ((unsigned)&RCSTA*8)+2; // framing error
static volatile near bit OERR @ ((unsigned)&RCSTA*8)+1; // overrun error
static volatile near bit RX9D @ ((unsigned)&RCSTA*8)+0; // 9th Bit of RX data
// EECON1 Register
static near bit EEPGD @ ((unsigned)&EECON1*8)+7; // FLASH/EEPROM select
static near bit EEFS @ ((unsigned)&EECON1*8)+6; // access config regs./access FLASH-EEPROM
// alternate definition
static near bit CFGS @ ((unsigned)&EECON1*8)+6; //Config./Calibration Select
static volatile near bit FREE @ ((unsigned)&EECON1*8)+4; // FLASH row erase enable
static volatile near bit WRERR @ ((unsigned)&EECON1*8)+3; // write error flag
static near bit WREN @ ((unsigned)&EECON1*8)+2; // write enable
static volatile near bit WR @ ((unsigned)&EECON1*8)+1; // write control
static volatile near bit RD @ ((unsigned)&EECON1*8)+0; // read control
// IPR3 Register
static near bit IRXIP @ ((unsigned)&IPR3*8)+7; // CAN invalid rec. message interrupt priority
static near bit WAKIP @ ((unsigned)&IPR3*8)+6; // CANbus activity wake-up interrupt priority
static near bit ERRIP @ ((unsigned)&IPR3*8)+5; // CANbus error interrupt priority
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