tqm8xx.c

来自「最新版的u-boot,2008-10-18发布」· C语言 代码 · 共 616 行 · 第 1/2 页

			 * invalidate bank
			 */
			memctl->memc_br2 = 0;

			/* adjust refresh rate depending on SDRAM type, one bank */
			reg = memctl->memc_mptpr;
			reg >>= 1;			/* reduce to CFG_MPTPR_1BK_8K / _4K */
			memctl->memc_mptpr = reg;
		}

	} else {					/* SDRAM Bank 0 is bigger - map first   */

		memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
		memctl->memc_br2 =
				(CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;

		if (size_b1 > 0) {
			/*
			 * Position Bank 1 immediately above Bank 0
			 */
			memctl->memc_or3 =
					((-size_b1) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
			memctl->memc_br3 =
					((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V)
					+ size_b0;
		} else {
			unsigned long reg;

#ifndef	CONFIG_CAN_DRIVER
			/*
			 * No bank 1
			 *
			 * invalidate bank
			 */
			memctl->memc_br3 = 0;
#endif							/* CONFIG_CAN_DRIVER */

			/* adjust refresh rate depending on SDRAM type, one bank */
			reg = memctl->memc_mptpr;
			reg >>= 1;			/* reduce to CFG_MPTPR_1BK_8K / _4K */
			memctl->memc_mptpr = reg;
		}
	}

	udelay (10000);

#ifdef	CONFIG_CAN_DRIVER
	/* UPM initialization for CAN @ CLKOUT <= 66 MHz */

	/* Initialize OR3 / BR3 */
	memctl->memc_or3 = CFG_OR3_CAN;
	memctl->memc_br3 = CFG_BR3_CAN;

	/* Initialize MBMR */
	memctl->memc_mbmr = MBMR_GPL_B4DIS;	/* GPL_B4 ouput line Disable */

	/* Initialize UPMB for CAN: single read */
	memctl->memc_mdr = 0xFFFFCC04;
	memctl->memc_mcr = 0x0100 | UPMB;

	memctl->memc_mdr = 0x0FFFD004;
	memctl->memc_mcr = 0x0101 | UPMB;

	memctl->memc_mdr = 0x0FFFC000;
	memctl->memc_mcr = 0x0102 | UPMB;

	memctl->memc_mdr = 0x3FFFC004;
	memctl->memc_mcr = 0x0103 | UPMB;

	memctl->memc_mdr = 0xFFFFDC07;
	memctl->memc_mcr = 0x0104 | UPMB;

	/* Initialize UPMB for CAN: single write */
	memctl->memc_mdr = 0xFFFCCC04;
	memctl->memc_mcr = 0x0118 | UPMB;

	memctl->memc_mdr = 0xCFFCDC04;
	memctl->memc_mcr = 0x0119 | UPMB;

	memctl->memc_mdr = 0x3FFCC000;
	memctl->memc_mcr = 0x011A | UPMB;

	memctl->memc_mdr = 0xFFFCC004;
	memctl->memc_mcr = 0x011B | UPMB;

	memctl->memc_mdr = 0xFFFDC405;
	memctl->memc_mcr = 0x011C | UPMB;
#endif							/* CONFIG_CAN_DRIVER */

#ifdef	CONFIG_ISP1362_USB
	/* Initialize OR5 / BR5 */
	memctl->memc_or5 = CFG_OR5_ISP1362;
	memctl->memc_br5 = CFG_BR5_ISP1362;
#endif							/* CONFIG_ISP1362_USB */
	return (size_b0 + size_b1);
}

/* ------------------------------------------------------------------------- */

/*
 * Check memory range for valid RAM. A simple memory test determines
 * the actually available RAM size between addresses `base' and
 * `base + maxsize'. Some (not all) hardware errors are detected:
 * - short between address lines
 * - short between data lines
 */

static long int dram_size (long int mamr_value, long int *base, long int maxsize)
{
	volatile immap_t *immap = (immap_t *) CFG_IMMR;
	volatile memctl8xx_t *memctl = &immap->im_memctl;

	memctl->memc_mamr = mamr_value;

	return (get_ram_size(base, maxsize));
}

/* ------------------------------------------------------------------------- */

#ifdef CONFIG_PS2MULT

#ifdef CONFIG_HMI10
#define BASE_BAUD ( 1843200 / 16 )
struct serial_state rs_table[] = {
	{ BASE_BAUD, 4,  (void*)0xec140000 },
	{ BASE_BAUD, 2,  (void*)0xec150000 },
	{ BASE_BAUD, 6,  (void*)0xec160000 },
	{ BASE_BAUD, 10, (void*)0xec170000 },
};

#ifdef CONFIG_BOARD_EARLY_INIT_R
int board_early_init_r (void)
{
	ps2mult_early_init();
	return (0);
}
#endif
#endif /* CONFIG_HMI10 */

#endif /* CONFIG_PS2MULT */


#ifdef CONFIG_MISC_INIT_R
int misc_init_r (void)
{
	volatile immap_t *immap = (immap_t *) CFG_IMMR;
	volatile memctl8xx_t *memctl = &immap->im_memctl;

#ifdef	CFG_OR_TIMING_FLASH_AT_50MHZ
	int scy, trlx, flash_or_timing, clk_diff;

	scy = (CFG_OR_TIMING_FLASH_AT_50MHZ & OR_SCY_MSK) >> 4;
	if (CFG_OR_TIMING_FLASH_AT_50MHZ & OR_TRLX) {
		trlx = OR_TRLX;
		scy *= 2;
	} else {
		trlx = 0;
	}

	/*
	 * We assume that each 10MHz of bus clock require 1-clk SCY
	 * adjustment.
	 */
	clk_diff = (gd->bus_clk / 1000000) - 50;

	/*
	 * We need proper rounding here. This is what the "+5" and "-5"
	 * are here for.
	 */
	if (clk_diff >= 0)
		scy += (clk_diff + 5) / 10;
	else
		scy += (clk_diff - 5) / 10;

	/*
	 * For bus frequencies above 50MHz, we want to use relaxed timing
	 * (OR_TRLX).
	 */
	if (gd->bus_clk >= 50000000)
		trlx = OR_TRLX;
	else
		trlx = 0;

	if (trlx)
		scy /= 2;

	if (scy > 0xf)
		scy = 0xf;
	if (scy < 1)
		scy = 1;

	flash_or_timing = (scy << 4) | trlx |
		(CFG_OR_TIMING_FLASH_AT_50MHZ & ~(OR_TRLX | OR_SCY_MSK));

	memctl->memc_or0 =
		flash_or_timing | (-flash_info[0].size & OR_AM_MSK);
#else
	memctl->memc_or0 =
		CFG_OR_TIMING_FLASH | (-flash_info[0].size & OR_AM_MSK);
#endif
	memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V;

	debug ("## BR0: 0x%08x    OR0: 0x%08x\n",
	       memctl->memc_br0, memctl->memc_or0);

	if (flash_info[1].size) {
#ifdef	CFG_OR_TIMING_FLASH_AT_50MHZ
		memctl->memc_or1 = flash_or_timing |
			(-flash_info[1].size & 0xFFFF8000);
#else
		memctl->memc_or1 = CFG_OR_TIMING_FLASH |
			(-flash_info[1].size & 0xFFFF8000);
#endif
		memctl->memc_br1 =
			((CFG_FLASH_BASE +
			  flash_info[0].
			  size) & BR_BA_MSK) | BR_MS_GPCM | BR_V;

		debug ("## BR1: 0x%08x    OR1: 0x%08x\n",
		       memctl->memc_br1, memctl->memc_or1);
	} else {
		memctl->memc_br1 = 0;	/* invalidate bank */

		debug ("## DISABLE BR1: 0x%08x    OR1: 0x%08x\n",
		       memctl->memc_br1, memctl->memc_or1);
	}

# ifdef CONFIG_IDE_LED
	/* Configure PA15 as output port */
	immap->im_ioport.iop_padir |= 0x0001;
	immap->im_ioport.iop_paodr |= 0x0001;
	immap->im_ioport.iop_papar &= ~0x0001;
	immap->im_ioport.iop_padat &= ~0x0001;	/* turn it off */
# endif

#ifdef CONFIG_NSCU
	/* wake up ethernet module */
	immap->im_ioport.iop_pcpar &= ~0x0004;	/* GPIO pin      */
	immap->im_ioport.iop_pcdir |= 0x0004;	/* output        */
	immap->im_ioport.iop_pcso &= ~0x0004;	/* for clarity   */
	immap->im_ioport.iop_pcdat |= 0x0004;	/* enable        */
#endif /* CONFIG_NSCU */

	return (0);
}
#endif	/* CONFIG_MISC_INIT_R */


# ifdef CONFIG_IDE_LED
void ide_led (uchar led, uchar status)
{
	volatile immap_t *immap = (immap_t *) CFG_IMMR;

	/* We have one led for both pcmcia slots */
	if (status) {				/* led on */
		immap->im_ioport.iop_padat |= 0x0001;
	} else {
		immap->im_ioport.iop_padat &= ~0x0001;
	}
}
# endif

/* ---------------------------------------------------------------------------- */
/* TK885D specific initializaion						*/
/* ---------------------------------------------------------------------------- */
#ifdef CONFIG_TK885D
#include <miiphy.h>
int last_stage_init(void)
{
	const unsigned char phy[] = {CONFIG_FEC1_PHY, CONFIG_FEC2_PHY};
	unsigned short reg;
	int ret, i = 100;
	char *s;

	mii_init();
	/* Without this delay 0xff is read from the UART buffer later in
	 * abortboot() and autoboot is aborted */
	udelay(10000);
	while (tstc() && i--)
		(void)getc();

	/* Check if auto-negotiation is prohibited */
	s = getenv("phy_auto_nego");

	if (!s || !strcmp(s, "on"))
		/* Nothing to do - autonegotiation by default */
		return 0;

	for (i = 0; i < 2; i++) {
		ret = miiphy_read("FEC ETHERNET", phy[i], PHY_BMCR, &reg);
		if (ret) {
			printf("Cannot read BMCR on PHY %d\n", phy[i]);
			return 0;
		}
		/* Auto-negotiation off, hard set full duplex, 100Mbps */
		ret = miiphy_write("FEC ETHERNET", phy[i],
				   PHY_BMCR, (reg | PHY_BMCR_100MB |
					      PHY_BMCR_DPLX) & ~PHY_BMCR_AUTON);
		if (ret) {
			printf("Cannot write BMCR on PHY %d\n", phy[i]);
			return 0;
		}
	}

	return 0;
}
#endif