lowlevel_init.s

来自「最新版的u-boot,2008-10-18发布」· S 代码 · 共 318 行

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/* * Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA */#include <config.h>#include <version.h>#include <asm/processor.h>.macro	write32, addr, data	mov.l \addr ,r1	mov.l \data ,r0	mov.l r0, @r1.endm.macro	write16, addr, data	mov.l \addr ,r1	mov.l \data ,r0	mov.w r0, @r1.endm.macro	write8, addr, data	mov.l \addr ,r1	mov.l \data ,r0	mov.b r0, @r1.endm.macro	wait_timer, time	mov.l	\time ,r31:	nop	tst	r3, r3	bf/s	1b	dt	r3.endm#include <asm/processor.h>	.global	lowlevel_init	.text	.align	2lowlevel_init:	wait_timer	WAIT_200US	wait_timer	WAIT_200US	/*------- LBSC -------*/	write32 MMSELR_A,	MMSELR_D	/*------- DBSC2 -------*/	write32 DBSC2_DBCONF_A,	DBSC2_DBCONF_D	write32 DBSC2_DBTR0_A,	DBSC2_DBTR0_D	write32 DBSC2_DBTR1_A,	DBSC2_DBTR1_D	write32 DBSC2_DBTR2_A,	DBSC2_DBTR2_D	write32 DBSC2_DBFREQ_A,	DBSC2_DBFREQ_D1	write32 DBSC2_DBFREQ_A,	DBSC2_DBFREQ_D2	wait_timer	WAIT_200US	write32 DBSC2_DBDICODTOCD_A,	DBSC2_DBDICODTOCD_D	write32 DBSC2_DBCMDCNT_A,	DBSC2_DBCMDCNT_D_CKE_H	wait_timer	WAIT_200US	write32 DBSC2_DBCMDCNT_A,	DBSC2_DBCMDCNT_D_PALL	write32 DBSC2_DBMRCNT_A,	DBSC2_DBMRCNT_D_EMRS2	write32 DBSC2_DBMRCNT_A,	DBSC2_DBMRCNT_D_EMRS3	write32 DBSC2_DBMRCNT_A,	DBSC2_DBMRCNT_D_EMRS1_1	write32 DBSC2_DBMRCNT_A,	DBSC2_DBMRCNT_D_MRS_1	write32 DBSC2_DBCMDCNT_A,	DBSC2_DBCMDCNT_D_PALL	write32 DBSC2_DBCMDCNT_A,	DBSC2_DBCMDCNT_D_REF	write32 DBSC2_DBCMDCNT_A,	DBSC2_DBCMDCNT_D_REF	write32 DBSC2_DBMRCNT_A,	DBSC2_DBMRCNT_D_MRS_2	wait_timer	WAIT_200US	write32 DBSC2_DBMRCNT_A,	DBSC2_DBMRCNT_D_EMRS1_2	write32 DBSC2_DBMRCNT_A,	DBSC2_DBMRCNT_D_EMRS1_1	write32 DBSC2_DBEN_A,		DBSC2_DBEN_D	write32 DBSC2_DBRFCNT1_A,	DBSC2_DBRFCNT1_D	write32 DBSC2_DBRFCNT2_A,	DBSC2_DBRFCNT2_D	write32 DBSC2_DBRFCNT0_A,	DBSC2_DBRFCNT0_D	wait_timer	WAIT_200US	/*------- GPIO -------*/	write16 PACR_A,	PACR_D	write16 PBCR_A,	PBCR_D	write16 PCCR_A,	PCCR_D	write16 PDCR_A,	PDCR_D	write16 PECR_A,	PECR_D	write16 PFCR_A,	PFCR_D	write16 PGCR_A,	PGCR_D	write16 PHCR_A,	PHCR_D	write16 PJCR_A,	PJCR_D	write16 PKCR_A,	PKCR_D	write16 PLCR_A,	PLCR_D	write16 PMCR_A,	PMCR_D	write16 PNCR_A,	PNCR_D	write16 PPCR_A,	PPCR_D	write16 PQCR_A,	PQCR_D	write16 PRCR_A,	PRCR_D	write8	PEPUPR_A,	PEPUPR_D	write8	PHPUPR_A,	PHPUPR_D	write8	PJPUPR_A,	PJPUPR_D	write8	PKPUPR_A,	PKPUPR_D	write8	PLPUPR_A,	PLPUPR_D	write8	PMPUPR_A,	PMPUPR_D	write8	PNPUPR_A,	PNPUPR_D	write16	PPUPR1_A,	PPUPR1_D	write16	PPUPR2_A,	PPUPR2_D	write16	P1MSELR_A,	P1MSELR_D	write16	P2MSELR_A,	P2MSELR_D	/*------- LBSC -------*/	write32	BCR_A,		BCR_D	write32	CS0BCR_A,	CS0BCR_D	write32	CS0WCR_A,	CS0WCR_D	write32	CS1BCR_A,	CS1BCR_D	write32	CS1WCR_A,	CS1WCR_D	write32	CS4BCR_A,	CS4BCR_D	write32	CS4WCR_A,	CS4WCR_D	mov.l	PASCR_A, r0	mov.l	@r0, r2	mov.l	PASCR_32BIT_MODE, r1	tst	r1, r2	bt	lbsc_29bit	write32	CS2BCR_A,	CS_USB_BCR_D	write32	CS2WCR_A,	CS_USB_WCR_D	write32	CS3BCR_A,	CS_SD_BCR_D	write32	CS3WCR_A,	CS_SD_WCR_D	write32	CS5BCR_A,	CS_I2C_BCR_D	write32	CS5WCR_A,	CS_I2C_WCR_D	write32	CS6BCR_A,	CS0BCR_D	write32	CS6WCR_A,	CS0WCR_D	bra	lbsc_end	 noplbsc_29bit:	write32	CS5BCR_A,	CS_USB_BCR_D	write32	CS5WCR_A,	CS_USB_WCR_D	write32	CS6BCR_A,	CS_SD_BCR_D	write32	CS6WCR_A,	CS_SD_WCR_Dlbsc_end:	write32	CCR_A,	CCR_D	rts	nop	.align 4/*------- LBSC -------*/MMSELR_A:	.long	0xfc400020MMSELR_D:	.long	0xa5a50002/*------- DBSC2 -------*/#define DBSC2_BASE	0xfe800000DBSC2_DBSTATE_A:	.long	DBSC2_BASE + 0x0cDBSC2_DBEN_A:		.long	DBSC2_BASE + 0x10DBSC2_DBCMDCNT_A:	.long	DBSC2_BASE + 0x14DBSC2_DBCONF_A:		.long	DBSC2_BASE + 0x20DBSC2_DBTR0_A:		.long	DBSC2_BASE + 0x30DBSC2_DBTR1_A:		.long	DBSC2_BASE + 0x34DBSC2_DBTR2_A:		.long	DBSC2_BASE + 0x38DBSC2_DBRFCNT0_A:	.long	DBSC2_BASE + 0x40DBSC2_DBRFCNT1_A:	.long	DBSC2_BASE + 0x44DBSC2_DBRFCNT2_A:	.long	DBSC2_BASE + 0x48DBSC2_DBRFSTS_A:	.long	DBSC2_BASE + 0x4cDBSC2_DBFREQ_A:		.long	DBSC2_BASE + 0x50DBSC2_DBDICODTOCD_A:	.long	DBSC2_BASE + 0x54DBSC2_DBMRCNT_A:	.long	DBSC2_BASE + 0x60DDR_DUMMY_ACCESS_A:	.long	0x40000000DBSC2_DBCONF_D:		.long	0x00630002DBSC2_DBTR0_D:		.long	0x050b1f04DBSC2_DBTR1_D:		.long	0x00040204DBSC2_DBTR2_D:		.long	0x02100308DBSC2_DBFREQ_D1:	.long	0x00000000DBSC2_DBFREQ_D2:	.long	0x00000100DBSC2_DBDICODTOCD_D:	.long	0x000f0907DBSC2_DBCMDCNT_D_CKE_H:	.long	0x00000003DBSC2_DBCMDCNT_D_PALL:	.long	0x00000002DBSC2_DBCMDCNT_D_REF:	.long	0x00000004DBSC2_DBMRCNT_D_EMRS2:	.long	0x00020000DBSC2_DBMRCNT_D_EMRS3:	.long	0x00030000DBSC2_DBMRCNT_D_EMRS1_1:	.long	0x00010006DBSC2_DBMRCNT_D_EMRS1_2:	.long	0x00010386DBSC2_DBMRCNT_D_MRS_1:	.long	0x00000952DBSC2_DBMRCNT_D_MRS_2:	.long	0x00000852DBSC2_DBEN_D:		.long	0x00000001DBSC2_DBPDCNT0_D3:	.long	0x00000080DBSC2_DBRFCNT1_D:	.long	0x00000926DBSC2_DBRFCNT2_D:	.long	0x00fe00feDBSC2_DBRFCNT0_D:	.long	0x00010000WAIT_200US:	.long	33333/*------- GPIO -------*/#define GPIO_BASE	0xffe70000PACR_A:		.long	GPIO_BASE + 0x00PBCR_A:		.long	GPIO_BASE + 0x02PCCR_A:		.long	GPIO_BASE + 0x04PDCR_A:		.long	GPIO_BASE + 0x06PECR_A:		.long	GPIO_BASE + 0x08PFCR_A:		.long	GPIO_BASE + 0x0aPGCR_A:		.long	GPIO_BASE + 0x0cPHCR_A:		.long	GPIO_BASE + 0x0ePJCR_A:		.long	GPIO_BASE + 0x10PKCR_A:		.long	GPIO_BASE + 0x12PLCR_A:		.long	GPIO_BASE + 0x14PMCR_A:		.long	GPIO_BASE + 0x16PNCR_A:		.long	GPIO_BASE + 0x18PPCR_A:		.long	GPIO_BASE + 0x1aPQCR_A:		.long	GPIO_BASE + 0x1cPRCR_A:		.long	GPIO_BASE + 0x1ePEPUPR_A:	.long	GPIO_BASE + 0x48PHPUPR_A:	.long	GPIO_BASE + 0x4ePJPUPR_A:	.long	GPIO_BASE + 0x50PKPUPR_A:	.long	GPIO_BASE + 0x52PLPUPR_A:	.long	GPIO_BASE + 0x54PMPUPR_A:	.long	GPIO_BASE + 0x56PNPUPR_A:	.long	GPIO_BASE + 0x58PPUPR1_A:	.long	GPIO_BASE + 0x60PPUPR2_A:	.long	GPIO_BASE + 0x62P1MSELR_A:	.long	GPIO_BASE + 0x80P2MSELR_A:	.long	GPIO_BASE + 0x82PACR_D:		.long	0x0000PBCR_D:		.long	0x0000PCCR_D:		.long	0x0000PDCR_D:		.long	0x0000PECR_D:		.long	0x0000PFCR_D:		.long	0x0000PGCR_D:		.long	0x0000PHCR_D:		.long	0x00c0PJCR_D:		.long	0xc3fcPKCR_D:		.long	0x03ffPLCR_D:		.long	0x0000PMCR_D:		.long	0xffffPNCR_D:		.long	0xf0c3PPCR_D:		.long	0x0000PQCR_D:		.long	0x0000PRCR_D:		.long	0x0000PEPUPR_D:	.long	0xffPHPUPR_D:	.long	0x00PJPUPR_D:	.long	0x00PKPUPR_D:	.long	0x00PLPUPR_D:	.long	0x00PMPUPR_D:	.long	0xfcPNPUPR_D:	.long	0x00PPUPR1_D:	.long	0xffbfPPUPR2_D:	.long	0xff00P1MSELR_D:	.long	0x3780P2MSELR_D:	.long	0x0000/*------- LBSC -------*/PASCR_A:		.long	0xff000070PASCR_32BIT_MODE:	.long	0x80000000	/* check booting mode */BCR_A:		.long	BCRCS0BCR_A:	.long	CS0BCRCS0WCR_A:	.long	CS0WCRCS1BCR_A:	.long	CS1BCRCS1WCR_A:	.long	CS1WCRCS2BCR_A:	.long	CS2BCRCS2WCR_A:	.long	CS2WCRCS3BCR_A:	.long	CS3BCRCS3WCR_A:	.long	CS3WCRCS4BCR_A:	.long	CS4BCRCS4WCR_A:	.long	CS4WCRCS5BCR_A:	.long	CS5BCRCS5WCR_A:	.long	CS5WCRCS6BCR_A:	.long	CS6BCRCS6WCR_A:	.long	CS6WCRBCR_D:		.long	0x80000003CS0BCR_D:	.long	0x22222340CS0WCR_D:	.long	0x00111118CS1BCR_D:	.long	0x11111100CS1WCR_D:	.long	0x33333303CS4BCR_D:	.long	0x11111300CS4WCR_D:	.long	0x00101012/* USB setting : 32bit mode = CS2, 29bit mode = CS5 */CS_USB_BCR_D:	.long	0x11111200CS_USB_WCR_D:	.long	0x00020004/* SD setting  : 32bit mode = CS3, 29bit mode = CS6 */CS_SD_BCR_D:	.long	0x00000300CS_SD_WCR_D:	.long	0x00030108/* I2C setting : 32bit mode = CS5, 29bit mode = CS1(already setting) */CS_I2C_BCR_D:	.long	0x11111100CS_I2C_WCR_D:	.long	0x00000003CCR_A:		.long	0xff00001cCCR_D:		.long	0x0000090b

lowlevel_init.s - 源码说明

本页面展示了「最新版的u-boot,2008-10-18发布」中的 lowlevel_init.s 源码文件，采用 S 编程语言编写，共 318 行代码。您可以在线阅读完整代码内容，也可以返回资源详情页下载完整源码包进行本地学习和开发。

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