start.s

来自「最新版的u-boot,2008-10-18发布」· S 代码 · 共 633 行 · 第 1/2 页

	/* Transfer serial boot header to sram */
asm_dspi_rd_loop1:
	move.l	#0x80020000, %d2
	jsr	asm_dspi_wr_status
	jsr	asm_dspi_rd_status

	move.b	%d1, (%a0)		/* read, copy to dst */

	add.l	#1, %a0			/* inc dst by 1 */
	sub.l	#1, %d4			/* dec cnt by 1 */
	bne	asm_dspi_rd_loop1

	/* Transfer u-boot from serial flash to memory */
asm_dspi_rd_loop2:
	move.l	#0x80020000, %d2
	jsr	asm_dspi_wr_status
	jsr	asm_dspi_rd_status

	move.b	%d1, (%a4)		/* read, copy to dst */

	add.l	#1, %a4			/* inc dst by 1 */
	sub.l	#1, %d5			/* dec cnt by 1 */
	bne	asm_dspi_rd_loop2

	move.l	#0x00020000, %d2	/* Terminate */
	jsr	asm_dspi_wr_status
	jsr	asm_dspi_rd_status

	/* jump to memory and execute */
	move.l	#(TEXT_BASE + 0x400), %a0
	jmp	(%a0)

asm_dspi_wr_status:
	move.l	(%a1), %d0		/* status */
	and.l	#0x0000F000, %d0
	cmp.l	#0x00003000, %d0
	bgt	asm_dspi_wr_status

	move.l	%d2, (%a2)
	rts

asm_dspi_rd_status:
	move.l	(%a1), %d0		/* status */
	and.l	#0x000000F0, %d0
	lsr.l	#4, %d0
	cmp.l	#0, %d0
	beq	asm_dspi_rd_status

	move.b	(%a3), %d1
	rts
#endif			/* CONFIG_CF_SBF */

	.text
	. = 0x400
	.globl	_start
_start:
	nop
	nop
	move.w #0x2700,%sr		/* Mask off Interrupt */

	/* Set vector base register at the beginning of the Flash */
#if defined(CONFIG_CF_SBF)
	move.l	#TEXT_BASE, %d0
	movec	%d0, %VBR
#else
	move.l	#CFG_FLASH_BASE, %d0
	movec	%d0, %VBR

	move.l	#(CFG_INIT_RAM_ADDR + CFG_INIT_RAM_CTRL), %d0
	movec	%d0, %RAMBAR1
#endif

	/* initialize general use internal ram */
	move.l #0, %d0
	move.l #(CACR_STATUS), %a1	/* CACR */
	move.l #(ICACHE_STATUS), %a2	/* icache */
	move.l #(DCACHE_STATUS), %a3	/* dcache */
	move.l %d0, (%a1)
	move.l %d0, (%a2)
	move.l %d0, (%a3)

	/* invalidate and disable cache */
	move.l	#0x01004100, %d0	/* Invalidate cache cmd */
	movec	%d0, %CACR		/* Invalidate cache */
	move.l	#0, %d0
	movec	%d0, %ACR0
	movec	%d0, %ACR1
	movec	%d0, %ACR2
	movec	%d0, %ACR3

	/* set stackpointer to end of internal ram to get some stackspace for
	   the first c-code */
	move.l	#(CFG_INIT_RAM_ADDR + CFG_INIT_SP_OFFSET), %sp
	clr.l %sp@-

	move.l #__got_start, %a5	/* put relocation table address to a5 */

	bsr cpu_init_f			/* run low-level CPU init code (from flash) */
	bsr board_init_f		/* run low-level board init code (from flash) */

	/* board_init_f() does not return */

/*------------------------------------------------------------------------------*/

/*
 * void relocate_code (addr_sp, gd, addr_moni)
 *
 * This "function" does not return, instead it continues in RAM
 * after relocating the monitor code.
 *
 * r3 = dest
 * r4 = src
 * r5 = length in bytes
 * r6 = cachelinesize
 */
	.globl	relocate_code
relocate_code:
	link.w %a6,#0
	move.l 8(%a6), %sp		/* set new stack pointer */

	move.l 12(%a6), %d0		/* Save copy of Global Data pointer */
	move.l 16(%a6), %a0		/* Save copy of Destination Address */

	move.l #CFG_MONITOR_BASE, %a1
	move.l #__init_end, %a2
	move.l %a0, %a3

	/* copy the code to RAM */
1:
	move.l (%a1)+, (%a3)+
	cmp.l  %a1,%a2
	bgt.s	 1b

/*
 * We are done. Do not return, instead branch to second part of board
 * initialization, now running from RAM.
 */
	move.l	%a0, %a1
	add.l	#(in_ram - CFG_MONITOR_BASE), %a1
	jmp	(%a1)

in_ram:

clear_bss:
	/*
	 * Now clear BSS segment
	 */
	move.l	%a0, %a1
	add.l	#(_sbss - CFG_MONITOR_BASE),%a1
	move.l	%a0, %d1
	add.l	#(_ebss - CFG_MONITOR_BASE),%d1
6:
	clr.l	(%a1)+
	cmp.l	%a1,%d1
	bgt.s	6b

	/*
	 * fix got table in RAM
	 */
	move.l	%a0, %a1
	add.l	#(__got_start - CFG_MONITOR_BASE),%a1
	move.l	%a1,%a5			/* * fix got pointer register a5 */

	move.l	%a0, %a2
	add.l	#(__got_end - CFG_MONITOR_BASE),%a2

7:
	move.l	(%a1),%d1
	sub.l	#_start,%d1
	add.l	%a0,%d1
	move.l	%d1,(%a1)+
	cmp.l	%a2, %a1
	bne	7b

	/* calculate relative jump to board_init_r in ram */
	move.l %a0, %a1
	add.l #(board_init_r - CFG_MONITOR_BASE), %a1

	/* set parameters for board_init_r */
	move.l %a0,-(%sp)		/* dest_addr */
	move.l %d0,-(%sp)		/* gd */
	jsr	(%a1)

/*------------------------------------------------------------------------------*/
/* exception code */
	.globl _fault
_fault:
	bra _fault
	.globl	_exc_handler

_exc_handler:
	SAVE_ALL
	movel	%sp,%sp@-
	bsr exc_handler
	addql	#4,%sp
	RESTORE_ALL

	.globl	_int_handler
_int_handler:
	SAVE_ALL
	movel	%sp,%sp@-
	bsr int_handler
	addql	#4,%sp
	RESTORE_ALL

/*------------------------------------------------------------------------------*/
/* cache functions */
	.globl	icache_enable
icache_enable:
	move.l #(CACR_STATUS), %a1	/* read CACR Status */
	move.l	(%a1), %d1

	move.l	#0x00040100, %d0	/* Invalidate icache */
	movec	%d0, %CACR

	move.l	#(CFG_SDRAM_BASE + 0x1c000), %d0	/* Setup icache */
	movec	%d0, %ACR2

	move.l	#0x04088020, %d0	/* Enable bcache and icache */
	movec	%d0, %CACR

	move.l #(ICACHE_STATUS), %a1
	moveq	#1, %d0
	move.l	%d0, (%a1)
	rts

	.globl	icache_disable
icache_disable:
	move.l #(CACR_STATUS), %a1	/* read CACR Status */
	move.l	(%a1), %d0

	move.l	#0xFFF77BFF, %d0
	or.l	#0x00040100, %d0	/* Setup cache mask */
	movec	%d0, %CACR		/* Invalidate icache */
	clr.l	%d0
	movec	%d0, %ACR2
	movec	%d0, %ACR3

	move.l #(ICACHE_STATUS), %a1
	moveq	#0, %d0
	move.l	%d0, (%a1)
	rts

	.globl	icache_status
icache_status:
	move.l #(ICACHE_STATUS), %a1
	move.l	(%a1), %d0
	rts

	.globl	icache_invalid
icache_invalid:
	move.l #(CACR_STATUS), %a1	/* read CACR Status */
	move.l	(%a1), %d0

	move.l	#0x00040100, %d0	/* Invalidate icache */
	movec	%d0, %CACR		/* Enable and invalidate cache */
	rts

	.globl	dcache_enable
dcache_enable:
	move.l #(CACR_STATUS), %a1	/* read CACR Status */
	move.l	(%a1), %d1

	move.l	#0x01040100, %d0
	movec	%d0, %CACR		/* Invalidate dcache */

	move.l	#0x80088020, %d0	/* Enable bcache and icache */
	movec	%d0, %CACR

	move.l #(DCACHE_STATUS), %a1
	moveq	#1, %d0
	move.l	%d0, (%a1)
	rts

	.globl	dcache_disable
dcache_disable:
	move.l #(CACR_STATUS), %a1	/* read CACR Status */
	move.l	(%a1), %d0

	and.l	#0x7FFFFFFF, %d0
	or.l	#0x01000000, %d0	/* Setup cache mask */
	movec	%d0, %CACR		/* Disable dcache */
	clr.l	%d0
	movec	%d0, %ACR0
	movec	%d0, %ACR1

	move.l #(DCACHE_STATUS), %a1
	moveq	#0, %d0
	move.l	%d0, (%a1)
	rts

	.globl	dcache_invalid
dcache_invalid:
	move.l #(CACR_STATUS), %a1	/* read CACR Status */
	move.l	(%a1), %d0

	move.l	#0x81088020, %d0	/* Setup cache mask */
	movec	%d0, %CACR		/* Enable and invalidate cache */
	rts

	.globl	dcache_status
dcache_status:
	move.l #(DCACHE_STATUS), %a1
	move.l	(%a1), %d0
	rts

/*------------------------------------------------------------------------------*/

	.globl	version_string
version_string:
	.ascii U_BOOT_VERSION
	.ascii " (", __DATE__, " - ", __TIME__, ")"
	.ascii CONFIG_IDENT_STRING, "\0"
	.align 4