speed.c

来自「最新版的u-boot,2008-10-18发布」· C语言 代码 · 共 1,231 行 · 第 1/3 页

	 */
	sysInfo->pllPciDiv = (pllmr0 & PLLMR0_PCI_TO_PLB_MASK) + 1;

	/*
	 * Determine EXTBUS_DIV.
	 */
	sysInfo->pllExtBusDiv = ((pllmr0 & PLLMR0_EXB_TO_PLB_MASK) >> 8) + 2;

	/*
	 * Determine OPB_DIV.
	 */
	sysInfo->pllOpbDiv = ((pllmr0 & PLLMR0_OPB_TO_PLB_MASK) >> 12) + 1;

	/*
	 * Determine the M factor
	 */
	m = sysInfo->pllFbkDiv * sysInfo->pllFwdDivB;

	/*
	 * Determine VCO clock frequency
	 */
	sysInfo->freqVCOHz = (1000000000000LL * (unsigned long long)m) /
		(unsigned long long)sysClkPeriodPs;

	/*
	 * Determine CPU clock frequency
	 */
	pllmr0_ccdv = ((pllmr0 & PLLMR0_CPU_DIV_MASK) >> 20) + 1;
	if (pllmr1 & PLLMR1_SSCS_MASK) {
		/*
		 * This is true if FWDVA == FWDVB:
		 * sysInfo->freqProcessor = (CONFIG_SYS_CLK_FREQ * sysInfo->pllFbkDiv)
		 *	/ pllmr0_ccdv;
		 */
		sysInfo->freqProcessor = (CONFIG_SYS_CLK_FREQ * sysInfo->pllFbkDiv * sysInfo->pllFwdDivB)
			/ sysInfo->pllFwdDiv / pllmr0_ccdv;
	} else {
		sysInfo->freqProcessor = CONFIG_SYS_CLK_FREQ / pllmr0_ccdv;
	}

	/*
	 * Determine PLB clock frequency
	 */
	sysInfo->freqPLB = sysInfo->freqProcessor / sysInfo->pllPlbDiv;

	sysInfo->freqEBC = sysInfo->freqPLB / sysInfo->pllExtBusDiv;

	sysInfo->freqUART = sysInfo->freqProcessor * pllmr0_ccdv;
}


/********************************************
 * get_OPB_freq
 * return OPB bus freq in Hz
 *********************************************/
ulong get_OPB_freq (void)
{
	ulong val = 0;

	PPC4xx_SYS_INFO sys_info;

	get_sys_info (&sys_info);
	val = sys_info.freqPLB / sys_info.pllOpbDiv;

	return val;
}


/********************************************
 * get_PCI_freq
 * return PCI bus freq in Hz
 *********************************************/
ulong get_PCI_freq (void)
{
	ulong val;
	PPC4xx_SYS_INFO sys_info;

	get_sys_info (&sys_info);
	val = sys_info.freqPLB / sys_info.pllPciDiv;
	return val;
}

#elif defined(CONFIG_405EZ)
void get_sys_info (PPC4xx_SYS_INFO * sysInfo)
{
	unsigned long cpr_plld;
	unsigned long cpr_pllc;
	unsigned long cpr_primad;
	unsigned long sysClkPeriodPs = ONE_BILLION / (CONFIG_SYS_CLK_FREQ/1000);
	unsigned long primad_cpudv;
	unsigned long m;

	/*
	 * Read PLL Mode registers
	 */
	mfcpr(cprplld, cpr_plld);
	mfcpr(cprpllc, cpr_pllc);

	/*
	 * Determine forward divider A
	 */
	sysInfo->pllFwdDiv = ((cpr_plld & PLLD_FWDVA_MASK) >> 16);

	/*
	 * Determine forward divider B
	 */
	sysInfo->pllFwdDivB = ((cpr_plld & PLLD_FWDVB_MASK) >> 8);
	if (sysInfo->pllFwdDivB == 0)
		sysInfo->pllFwdDivB = 8;

	/*
	 * Determine FBK_DIV.
	 */
	sysInfo->pllFbkDiv = ((cpr_plld & PLLD_FBDV_MASK) >> 24);
	if (sysInfo->pllFbkDiv == 0)
		sysInfo->pllFbkDiv = 256;

	/*
	 * Read CPR_PRIMAD register
	 */
	mfcpr(cprprimad, cpr_primad);

	/*
	 * Determine PLB_DIV.
	 */
	sysInfo->pllPlbDiv = ((cpr_primad & PRIMAD_PLBDV_MASK) >> 16);
	if (sysInfo->pllPlbDiv == 0)
		sysInfo->pllPlbDiv = 16;

	/*
	 * Determine EXTBUS_DIV.
	 */
	sysInfo->pllExtBusDiv = (cpr_primad & PRIMAD_EBCDV_MASK);
	if (sysInfo->pllExtBusDiv == 0)
		sysInfo->pllExtBusDiv = 16;

	/*
	 * Determine OPB_DIV.
	 */
	sysInfo->pllOpbDiv = ((cpr_primad & PRIMAD_OPBDV_MASK) >> 8);
	if (sysInfo->pllOpbDiv == 0)
		sysInfo->pllOpbDiv = 16;

	/*
	 * Determine the M factor
	 */
	if (cpr_pllc & PLLC_SRC_MASK)
		m = sysInfo->pllFbkDiv * sysInfo->pllFwdDivB;
	else
		m = sysInfo->pllFbkDiv * sysInfo->pllFwdDiv;

	/*
	 * Determine VCO clock frequency
	 */
	sysInfo->freqVCOHz = (1000000000000LL * (unsigned long long)m) /
		(unsigned long long)sysClkPeriodPs;

	/*
	 * Determine CPU clock frequency
	 */
	primad_cpudv = ((cpr_primad & PRIMAD_CPUDV_MASK) >> 24);
	if (primad_cpudv == 0)
		primad_cpudv = 16;

	sysInfo->freqProcessor = (CONFIG_SYS_CLK_FREQ * m) /
		sysInfo->pllFwdDiv / primad_cpudv;

	/*
	 * Determine PLB clock frequency
	 */
	sysInfo->freqPLB = (CONFIG_SYS_CLK_FREQ * m) /
		sysInfo->pllFwdDiv / sysInfo->pllPlbDiv;

	sysInfo->freqEBC = (CONFIG_SYS_CLK_FREQ * sysInfo->pllFbkDiv) /
		sysInfo->pllExtBusDiv;

	sysInfo->freqUART = sysInfo->freqVCOHz;
}

/********************************************
 * get_OPB_freq
 * return OPB bus freq in Hz
 *********************************************/
ulong get_OPB_freq (void)
{
	ulong val = 0;

	PPC4xx_SYS_INFO sys_info;

	get_sys_info (&sys_info);
	val = (CONFIG_SYS_CLK_FREQ * sys_info.pllFbkDiv) / sys_info.pllOpbDiv;

	return val;
}

#elif defined(CONFIG_405EX)

/*
 * TODO: We need to get the CPR registers and calculate these values correctly!!!!
 *   We need the specs!!!!
 */
static unsigned char get_fbdv(unsigned char index)
{
	unsigned char ret = 0;
	/* This is table should be 256 bytes.
	 * Only take first 52 values.
	 */
	unsigned char fbdv_tb[] = {
		0x00, 0xff, 0x7f, 0xfd,
		0x7a, 0xf5, 0x6a, 0xd5,
		0x2a, 0xd4, 0x29, 0xd3,
		0x26, 0xcc, 0x19, 0xb3,
		0x67, 0xce, 0x1d, 0xbb,
		0x77, 0xee, 0x5d, 0xba,
		0x74, 0xe9, 0x52, 0xa5,
		0x4b, 0x96, 0x2c, 0xd8,
		0x31, 0xe3, 0x46, 0x8d,
		0x1b, 0xb7, 0x6f, 0xde,
		0x3d, 0xfb, 0x76, 0xed,
		0x5a, 0xb5, 0x6b, 0xd6,
		0x2d, 0xdb, 0x36, 0xec,

	};

	if ((index & 0x7f) == 0)
		return 1;
	while (ret < sizeof (fbdv_tb)) {
		if (fbdv_tb[ret] == index)
			break;
		ret++;
	}
	ret++;

	return ret;
}

#define PLL_FBK_PLL_LOCAL	0
#define PLL_FBK_CPU		1
#define PLL_FBK_PERCLK		5

void get_sys_info (sys_info_t * sysInfo)
{
	unsigned long sysClkPeriodPs = ONE_BILLION / (CONFIG_SYS_CLK_FREQ / 1000);
	unsigned long m = 1;
	unsigned int  tmp;
	unsigned char fwdva[16] = {
		1, 2, 14, 9, 4, 11, 16, 13,
		12, 5, 6, 15, 10, 7, 8, 3,
	};
	unsigned char sel, cpudv0, plb2xDiv;

	mfcpr(cpr0_plld, tmp);

	/*
	 * Determine forward divider A
	 */
	sysInfo->pllFwdDiv = fwdva[((tmp >> 16) & 0x0f)];	/* FWDVA */

	/*
	 * Determine FBK_DIV.
	 */
	sysInfo->pllFbkDiv = get_fbdv(((tmp >> 24) & 0x0ff)); /* FBDV */

	/*
	 * Determine PLBDV0
	 */
	sysInfo->pllPlbDiv = 2;

	/*
	 * Determine PERDV0
	 */
	mfcpr(cpr0_perd, tmp);
	tmp = (tmp >> 24) & 0x03;
	sysInfo->pllExtBusDiv = (tmp == 0) ? 4 : tmp;

	/*
	 * Determine OPBDV0
	 */
	mfcpr(cpr0_opbd, tmp);
	tmp = (tmp >> 24) & 0x03;
	sysInfo->pllOpbDiv = (tmp == 0) ? 4 : tmp;

	/* Determine PLB2XDV0 */
	mfcpr(cpr0_plbd, tmp);
	tmp = (tmp >> 16) & 0x07;
	plb2xDiv = (tmp == 0) ? 8 : tmp;

	/* Determine CPUDV0 */
	mfcpr(cpr0_cpud, tmp);
	tmp = (tmp >> 24) & 0x07;
	cpudv0 = (tmp == 0) ? 8 : tmp;

	/* Determine SEL(5:7) in CPR0_PLLC */
	mfcpr(cpr0_pllc, tmp);
	sel = (tmp >> 24) & 0x07;

	/*
	 * Determine the M factor
	 * PLL local: M = FBDV
	 * CPU clock: M = FBDV * FWDVA * CPUDV0
	 * PerClk	: M = FBDV * FWDVA * PLB2XDV0 * PLBDV0(2) * OPBDV0 * PERDV0
	 *
	 */
	switch (sel) {
	case PLL_FBK_CPU:
		m = sysInfo->pllFwdDiv * cpudv0;
		break;
	case PLL_FBK_PERCLK:
		m = sysInfo->pllFwdDiv * plb2xDiv * 2
			* sysInfo->pllOpbDiv * sysInfo->pllExtBusDiv;
		break;
	case PLL_FBK_PLL_LOCAL:
		break;
	default:
		printf("%s unknown m\n", __FUNCTION__);
		return;

	}
	m *= sysInfo->pllFbkDiv;

	/*
	 * Determine VCO clock frequency
	 */
	sysInfo->freqVCOHz = (1000000000000LL * (unsigned long long)m) /
		(unsigned long long)sysClkPeriodPs;

	/*
	 * Determine CPU clock frequency
	 */
	sysInfo->freqProcessor = sysInfo->freqVCOHz / (sysInfo->pllFwdDiv * cpudv0);

	/*
	 * Determine PLB clock frequency, ddr1x should be the same
	 */
	sysInfo->freqPLB = sysInfo->freqVCOHz / (sysInfo->pllFwdDiv * plb2xDiv * 2);
	sysInfo->freqOPB = sysInfo->freqPLB/sysInfo->pllOpbDiv;
	sysInfo->freqDDR = sysInfo->freqPLB;
	sysInfo->freqEBC = sysInfo->freqOPB / sysInfo->pllExtBusDiv;
	sysInfo->freqUART = sysInfo->freqPLB;
}

/********************************************
 * get_OPB_freq
 * return OPB bus freq in Hz
 *********************************************/
ulong get_OPB_freq (void)
{
	ulong val = 0;

	PPC4xx_SYS_INFO sys_info;

	get_sys_info (&sys_info);
	val = sys_info.freqPLB / sys_info.pllOpbDiv;

	return val;
}

#endif

int get_clocks (void)
{
#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
    defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
    defined(CONFIG_405EX) || defined(CONFIG_405) || \
    defined(CONFIG_440)
	sys_info_t sys_info;

	get_sys_info (&sys_info);
	gd->cpu_clk = sys_info.freqProcessor;
	gd->bus_clk = sys_info.freqPLB;

#endif	/* defined(CONFIG_405GP) || defined(CONFIG_405CR) */

#ifdef CONFIG_IOP480
	gd->cpu_clk = 66000000;
	gd->bus_clk = 66000000;
#endif
	return (0);
}


/********************************************
 * get_bus_freq
 * return PLB bus freq in Hz
 *********************************************/
ulong get_bus_freq (ulong dummy)
{
	ulong val;

#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
    defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
    defined(CONFIG_405EX) || defined(CONFIG_405) || \
    defined(CONFIG_440)
	sys_info_t sys_info;

	get_sys_info (&sys_info);
	val = sys_info.freqPLB;

#elif defined(CONFIG_IOP480)

	val = 66;

#else
# error get_bus_freq() not implemented
#endif

	return val;
}