speed.c

来自「最新版的u-boot,2008-10-18发布」· C语言 代码 · 共 1,231 行 · 第 1/3 页

ulong get_PCI_freq (void)
{
	sys_info_t sys_info;
	get_sys_info (&sys_info);
	return sys_info.freqPCI;
}

#elif !defined(CONFIG_440GX) && !defined(CONFIG_440SP) && !defined(CONFIG_440SPE) \
	&& !defined(CONFIG_XILINX_440)
void get_sys_info (sys_info_t * sysInfo)
{
	unsigned long strp0;
	unsigned long temp;
	unsigned long m;

	/* Extract configured divisors */
	strp0 = mfdcr( cpc0_strp0 );
	sysInfo->pllFwdDivA = 8 - ((strp0 & PLLSYS0_FWD_DIV_A_MASK) >> 15);
	sysInfo->pllFwdDivB = 8 - ((strp0 & PLLSYS0_FWD_DIV_B_MASK) >> 12);
	temp = (strp0 & PLLSYS0_FB_DIV_MASK) >> 18;
	sysInfo->pllFbkDiv = temp ? temp : 16;
	sysInfo->pllOpbDiv = 1 + ((strp0 & PLLSYS0_OPB_DIV_MASK) >> 10);
	sysInfo->pllExtBusDiv = 1 + ((strp0 & PLLSYS0_EPB_DIV_MASK) >> 8);

	/* Calculate 'M' based on feedback source */
	if( strp0 & PLLSYS0_EXTSL_MASK )
		m = sysInfo->pllExtBusDiv * sysInfo->pllOpbDiv * sysInfo->pllFwdDivB;
	else
		m = sysInfo->pllFbkDiv * sysInfo->pllFwdDivA;

	/* Now calculate the individual clocks */
	sysInfo->freqVCOMhz = (m * CONFIG_SYS_CLK_FREQ) + (m>>1);
	sysInfo->freqProcessor = sysInfo->freqVCOMhz/sysInfo->pllFwdDivA;
	sysInfo->freqPLB = sysInfo->freqVCOMhz/sysInfo->pllFwdDivB;
	if( get_pvr() == PVR_440GP_RB ) /* Rev B divs an extra 2 -- geez! */
		sysInfo->freqPLB >>= 1;
	sysInfo->freqOPB = sysInfo->freqPLB/sysInfo->pllOpbDiv;
	sysInfo->freqEBC = sysInfo->freqOPB/sysInfo->pllExtBusDiv;
	sysInfo->freqUART = sysInfo->freqPLB;
}
#else

#if !defined(CONFIG_XILINX_440)
void get_sys_info (sys_info_t * sysInfo)
{
	unsigned long strp0;
	unsigned long strp1;
	unsigned long temp;
	unsigned long temp1;
	unsigned long lfdiv;
	unsigned long m;
	unsigned long prbdv0;

#if defined(CONFIG_YUCCA)
	unsigned long sys_freq;
	unsigned long sys_per=0;
	unsigned long msr;
	unsigned long pci_clock_per;
	unsigned long sdr_ddrpll;

	/*-------------------------------------------------------------------------+
	 | Get the system clock period.
	 +-------------------------------------------------------------------------*/
	sys_per = determine_sysper();

	msr = (mfmsr () & ~(MSR_EE));	/* disable interrupts */

	/*-------------------------------------------------------------------------+
	 | Calculate the system clock speed from the period.
	 +-------------------------------------------------------------------------*/
	sys_freq = (ONE_BILLION / sys_per) * 1000;
#endif

	/* Extract configured divisors */
	mfsdr( sdr_sdstp0,strp0 );
	mfsdr( sdr_sdstp1,strp1 );

	temp = ((strp0 & PLLSYS0_FWD_DIV_A_MASK) >> 8);
	sysInfo->pllFwdDivA = temp ? temp : 16 ;
	temp = ((strp0 & PLLSYS0_FWD_DIV_B_MASK) >> 5);
	sysInfo->pllFwdDivB = temp ? temp: 8 ;
	temp = (strp0 & PLLSYS0_FB_DIV_MASK) >> 12;
	sysInfo->pllFbkDiv = temp ? temp : 32;
	temp = (strp0 & PLLSYS0_OPB_DIV_MASK);
	sysInfo->pllOpbDiv = temp ? temp : 4;
	temp = (strp1 & PLLSYS1_PERCLK_DIV_MASK) >> 24;
	sysInfo->pllExtBusDiv = temp ? temp : 4;
	prbdv0 = (strp0 >> 2) & 0x7;

	/* Calculate 'M' based on feedback source */
	temp = (strp0 & PLLSYS0_SEL_MASK) >> 27;
	temp1 = (strp1 & PLLSYS1_LF_DIV_MASK) >> 26;
	lfdiv = temp1 ? temp1 : 64;
	if (temp == 0) { /* PLL output */
		/* Figure which pll to use */
		temp = (strp0 & PLLSYS0_SRC_MASK) >> 30;
		if (!temp)
			m = sysInfo->pllFbkDiv * lfdiv * sysInfo->pllFwdDivA;
		else
			m = sysInfo->pllFbkDiv * lfdiv * sysInfo->pllFwdDivB;
	}
	else if (temp == 1) /* CPU output */
		m = sysInfo->pllFbkDiv * sysInfo->pllFwdDivA;
	else /* PerClk */
		m = sysInfo->pllExtBusDiv * sysInfo->pllOpbDiv * sysInfo->pllFwdDivB;

	/* Now calculate the individual clocks */
#if defined(CONFIG_YUCCA)
	sysInfo->freqVCOMhz = (m * sys_freq) ;
#else
	sysInfo->freqVCOMhz = (m * CONFIG_SYS_CLK_FREQ) + (m >> 1);
#endif
	sysInfo->freqProcessor = sysInfo->freqVCOMhz/sysInfo->pllFwdDivA;
	sysInfo->freqPLB = sysInfo->freqVCOMhz/sysInfo->pllFwdDivB/prbdv0;
	sysInfo->freqOPB = sysInfo->freqPLB/sysInfo->pllOpbDiv;
	sysInfo->freqEBC = sysInfo->freqOPB/sysInfo->pllExtBusDiv;

#if defined(CONFIG_YUCCA)
	/* Determine PCI Clock Period */
	pci_clock_per = determine_pci_clock_per();
	sysInfo->freqPCI = (ONE_BILLION/pci_clock_per) * 1000;
	mfsdr(sdr_ddr0, sdr_ddrpll);
	sysInfo->freqDDR = ((sysInfo->freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
#endif

	sysInfo->freqUART = sysInfo->freqPLB;
}

#endif
#endif /* CONFIG_XILINX_440 */

#if defined(CONFIG_YUCCA)
unsigned long determine_sysper(void)
{
	unsigned int fpga_clocking_reg;
	unsigned int master_clock_selection;
	unsigned long master_clock_per = 0;
	unsigned long fb_div_selection;
	unsigned int vco_div_reg_value;
	unsigned long vco_div_selection;
	unsigned long sys_per = 0;
	int extClkVal;

	/*-------------------------------------------------------------------------+
	 | Read FPGA reg 0 and reg 1 to get FPGA reg information
	 +-------------------------------------------------------------------------*/
	fpga_clocking_reg = in16(FPGA_REG16);


	/* Determine Master Clock Source Selection */
	master_clock_selection = fpga_clocking_reg & FPGA_REG16_MASTER_CLK_MASK;

	switch(master_clock_selection) {
		case FPGA_REG16_MASTER_CLK_66_66:
			master_clock_per = PERIOD_66_66MHZ;
			break;
		case FPGA_REG16_MASTER_CLK_50:
			master_clock_per = PERIOD_50_00MHZ;
			break;
		case FPGA_REG16_MASTER_CLK_33_33:
			master_clock_per = PERIOD_33_33MHZ;
			break;
		case FPGA_REG16_MASTER_CLK_25:
			master_clock_per = PERIOD_25_00MHZ;
			break;
		case FPGA_REG16_MASTER_CLK_EXT:
			if ((extClkVal==EXTCLK_33_33)
					&& (extClkVal==EXTCLK_50)
					&& (extClkVal==EXTCLK_66_66)
					&& (extClkVal==EXTCLK_83)) {
				/* calculate master clock period from external clock value */
				master_clock_per=(ONE_BILLION/extClkVal) * 1000;
			} else {
				/* Unsupported */
				DEBUGF ("%s[%d] *** master clock selection failed ***\n", __FUNCTION__,__LINE__);
				hang();
			}
			break;
		default:
			/* Unsupported */
			DEBUGF ("%s[%d] *** master clock selection failed ***\n", __FUNCTION__,__LINE__);
			hang();
			break;
	}

	/* Determine FB divisors values */
	if ((fpga_clocking_reg & FPGA_REG16_FB1_DIV_MASK) == FPGA_REG16_FB1_DIV_LOW) {
		if ((fpga_clocking_reg & FPGA_REG16_FB2_DIV_MASK) == FPGA_REG16_FB2_DIV_LOW)
			fb_div_selection = FPGA_FB_DIV_6;
		else
			fb_div_selection = FPGA_FB_DIV_12;
	} else {
		if ((fpga_clocking_reg & FPGA_REG16_FB2_DIV_MASK) == FPGA_REG16_FB2_DIV_LOW)
			fb_div_selection = FPGA_FB_DIV_10;
		else
			fb_div_selection = FPGA_FB_DIV_20;
	}

	/* Determine VCO divisors values */
	vco_div_reg_value = fpga_clocking_reg & FPGA_REG16_VCO_DIV_MASK;

	switch(vco_div_reg_value) {
		case FPGA_REG16_VCO_DIV_4:
			vco_div_selection = FPGA_VCO_DIV_4;
			break;
		case FPGA_REG16_VCO_DIV_6:
			vco_div_selection = FPGA_VCO_DIV_6;
			break;
		case FPGA_REG16_VCO_DIV_8:
			vco_div_selection = FPGA_VCO_DIV_8;
			break;
		case FPGA_REG16_VCO_DIV_10:
		default:
			vco_div_selection = FPGA_VCO_DIV_10;
			break;
	}

	if (master_clock_selection == FPGA_REG16_MASTER_CLK_EXT) {
		switch(master_clock_per) {
			case PERIOD_25_00MHZ:
				if (fb_div_selection == FPGA_FB_DIV_12) {
					if (vco_div_selection == FPGA_VCO_DIV_4)
						sys_per = PERIOD_75_00MHZ;
					if (vco_div_selection == FPGA_VCO_DIV_6)
						sys_per = PERIOD_50_00MHZ;
				}
				break;
			case PERIOD_33_33MHZ:
				if (fb_div_selection == FPGA_FB_DIV_6) {
					if (vco_div_selection == FPGA_VCO_DIV_4)
						sys_per = PERIOD_50_00MHZ;
					if (vco_div_selection == FPGA_VCO_DIV_6)
						sys_per = PERIOD_33_33MHZ;
				}
				if (fb_div_selection == FPGA_FB_DIV_10) {
					if (vco_div_selection == FPGA_VCO_DIV_4)
						sys_per = PERIOD_83_33MHZ;
					if (vco_div_selection == FPGA_VCO_DIV_10)
						sys_per = PERIOD_33_33MHZ;
				}
				if (fb_div_selection == FPGA_FB_DIV_12) {
					if (vco_div_selection == FPGA_VCO_DIV_4)
						sys_per = PERIOD_100_00MHZ;
					if (vco_div_selection == FPGA_VCO_DIV_6)
						sys_per = PERIOD_66_66MHZ;
					if (vco_div_selection == FPGA_VCO_DIV_8)
						sys_per = PERIOD_50_00MHZ;
				}
				break;
			case PERIOD_50_00MHZ:
				if (fb_div_selection == FPGA_FB_DIV_6) {
					if (vco_div_selection == FPGA_VCO_DIV_4)
						sys_per = PERIOD_75_00MHZ;
					if (vco_div_selection == FPGA_VCO_DIV_6)
						sys_per = PERIOD_50_00MHZ;
				}
				if (fb_div_selection == FPGA_FB_DIV_10) {
					if (vco_div_selection == FPGA_VCO_DIV_6)
						sys_per = PERIOD_83_33MHZ;
					if (vco_div_selection == FPGA_VCO_DIV_10)
						sys_per = PERIOD_50_00MHZ;
				}
				if (fb_div_selection == FPGA_FB_DIV_12) {
					if (vco_div_selection == FPGA_VCO_DIV_6)
						sys_per = PERIOD_100_00MHZ;
					if (vco_div_selection == FPGA_VCO_DIV_8)
						sys_per = PERIOD_75_00MHZ;
				}
				break;
			case PERIOD_66_66MHZ:
				if (fb_div_selection == FPGA_FB_DIV_6) {
					if (vco_div_selection == FPGA_VCO_DIV_4)
						sys_per = PERIOD_100_00MHZ;
					if (vco_div_selection == FPGA_VCO_DIV_6)
						sys_per = PERIOD_66_66MHZ;
					if (vco_div_selection == FPGA_VCO_DIV_8)
						sys_per = PERIOD_50_00MHZ;
				}
				if (fb_div_selection == FPGA_FB_DIV_10) {
					if (vco_div_selection == FPGA_VCO_DIV_8)
						sys_per = PERIOD_83_33MHZ;
					if (vco_div_selection == FPGA_VCO_DIV_10)
						sys_per = PERIOD_66_66MHZ;
				}
				if (fb_div_selection == FPGA_FB_DIV_12) {
					if (vco_div_selection == FPGA_VCO_DIV_8)
						sys_per = PERIOD_100_00MHZ;
				}
				break;
			default:
				break;
		}

		if (sys_per == 0) {
			/* Other combinations are not supported */
			DEBUGF ("%s[%d] *** sys period compute failed ***\n", __FUNCTION__,__LINE__);
			hang();
		}
	} else {
		/* calcul system clock without cheking */
		/* if engineering option clock no check is selected */
		/* sys_per = master_clock_per * vco_div_selection / fb_div_selection */
		sys_per = (master_clock_per/fb_div_selection) * vco_div_selection;
	}

	return(sys_per);
}

/*-------------------------------------------------------------------------+
| determine_pci_clock_per.
+-------------------------------------------------------------------------*/
unsigned long determine_pci_clock_per(void)
{
	unsigned long pci_clock_selection,  pci_period;

	/*-------------------------------------------------------------------------+
	 | Read FPGA reg 6 to get PCI 0 FPGA reg information
	 +-------------------------------------------------------------------------*/
	pci_clock_selection = in16(FPGA_REG16);	/* was reg6 averifier */


	pci_clock_selection = pci_clock_selection & FPGA_REG16_PCI0_CLK_MASK;

	switch (pci_clock_selection) {
		case FPGA_REG16_PCI0_CLK_133_33:
			pci_period = PERIOD_133_33MHZ;
			break;
		case FPGA_REG16_PCI0_CLK_100:
			pci_period = PERIOD_100_00MHZ;
			break;
		case FPGA_REG16_PCI0_CLK_66_66:
			pci_period = PERIOD_66_66MHZ;
			break;
		default:
			pci_period = PERIOD_33_33MHZ;;
			break;
	}

	return(pci_period);
}
#endif

ulong get_OPB_freq (void)
{

	sys_info_t sys_info;
	get_sys_info (&sys_info);
	return sys_info.freqOPB;
}

#elif defined(CONFIG_XILINX_405)
extern void get_sys_info (sys_info_t * sysInfo);
extern ulong get_PCI_freq (void);

#elif defined(CONFIG_AP1000)
void get_sys_info (sys_info_t * sysInfo)
{
	sysInfo->freqProcessor = 240 * 1000 * 1000;
	sysInfo->freqPLB = 80 * 1000 * 1000;
	sysInfo->freqPCI = 33 * 1000 * 1000;
}

#elif defined(CONFIG_405)

void get_sys_info (sys_info_t * sysInfo)
{
	sysInfo->freqVCOMhz=3125000;
	sysInfo->freqProcessor=12*1000*1000;
	sysInfo->freqPLB=50*1000*1000;
	sysInfo->freqPCI=66*1000*1000;
}

#elif defined(CONFIG_405EP)
void get_sys_info (PPC4xx_SYS_INFO * sysInfo)
{
	unsigned long pllmr0;
	unsigned long pllmr1;
	unsigned long sysClkPeriodPs = ONE_BILLION / (CONFIG_SYS_CLK_FREQ / 1000);
	unsigned long m;
	unsigned long pllmr0_ccdv;

	/*
	 * Read PLL Mode registers
	 */
	pllmr0 = mfdcr (cpc0_pllmr0);
	pllmr1 = mfdcr (cpc0_pllmr1);

	/*
	 * Determine forward divider A
	 */
	sysInfo->pllFwdDiv = 8 - ((pllmr1 & PLLMR1_FWDVA_MASK) >> 16);

	/*
	 * Determine forward divider B (should be equal to A)
	 */
	sysInfo->pllFwdDivB = 8 - ((pllmr1 & PLLMR1_FWDVB_MASK) >> 12);

	/*
	 * Determine FBK_DIV.
	 */
	sysInfo->pllFbkDiv = ((pllmr1 & PLLMR1_FBMUL_MASK) >> 20);
	if (sysInfo->pllFbkDiv == 0)
		sysInfo->pllFbkDiv = 16;

	/*
	 * Determine PLB_DIV.
	 */
	sysInfo->pllPlbDiv = ((pllmr0 & PLLMR0_CPU_TO_PLB_MASK) >> 16) + 1;

	/*
	 * Determine PCI_DIV.