4xx_enet.c

来自「最新版的u-boot,2008-10-18发布」· C语言 代码 · 共 2,136 行 · 第 1/5 页

		zmiifer |= ZMII_FER_RMII << ZMII_FER_V(2);
		zmiifer |= ZMII_FER_RMII << ZMII_FER_V(3);
		bis->bi_phymode[0] = BI_PHYMODE_ZMII;
		bis->bi_phymode[1] = BI_PHYMODE_ZMII;
		bis->bi_phymode[2] = BI_PHYMODE_ZMII;
		bis->bi_phymode[3] = BI_PHYMODE_ZMII;
		break;
	case 2:
		zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0);
		zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1);
		zmiifer |= ZMII_FER_SMII << ZMII_FER_V(2);
		zmiifer |= ZMII_FER_SMII << ZMII_FER_V(3);
		bis->bi_phymode[0] = BI_PHYMODE_ZMII;
		bis->bi_phymode[1] = BI_PHYMODE_ZMII;
		bis->bi_phymode[2] = BI_PHYMODE_ZMII;
		bis->bi_phymode[3] = BI_PHYMODE_ZMII;
		break;
	case 3:
		zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0);
		rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2);
		bis->bi_phymode[0] = BI_PHYMODE_ZMII;
		bis->bi_phymode[1] = BI_PHYMODE_NONE;
		bis->bi_phymode[2] = BI_PHYMODE_RGMII;
		bis->bi_phymode[3] = BI_PHYMODE_NONE;
		break;
	case 4:
		zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0);
		zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1);
		rmiifer |= RGMII_FER_RGMII << RGMII_FER_V (2);
		rmiifer |= RGMII_FER_RGMII << RGMII_FER_V (3);
		bis->bi_phymode[0] = BI_PHYMODE_ZMII;
		bis->bi_phymode[1] = BI_PHYMODE_ZMII;
		bis->bi_phymode[2] = BI_PHYMODE_RGMII;
		bis->bi_phymode[3] = BI_PHYMODE_RGMII;
		break;
	case 5:
		zmiifer |= ZMII_FER_SMII << ZMII_FER_V (0);
		zmiifer |= ZMII_FER_SMII << ZMII_FER_V (1);
		zmiifer |= ZMII_FER_SMII << ZMII_FER_V (2);
		rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(3);
		bis->bi_phymode[0] = BI_PHYMODE_ZMII;
		bis->bi_phymode[1] = BI_PHYMODE_ZMII;
		bis->bi_phymode[2] = BI_PHYMODE_ZMII;
		bis->bi_phymode[3] = BI_PHYMODE_RGMII;
		break;
	case 6:
		zmiifer |= ZMII_FER_SMII << ZMII_FER_V (0);
		zmiifer |= ZMII_FER_SMII << ZMII_FER_V (1);
		rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2);
		bis->bi_phymode[0] = BI_PHYMODE_ZMII;
		bis->bi_phymode[1] = BI_PHYMODE_ZMII;
		bis->bi_phymode[2] = BI_PHYMODE_RGMII;
		break;
	case 0:
	default:
		zmiifer = ZMII_FER_MII << ZMII_FER_V(devnum);
		rmiifer = 0x0;
		bis->bi_phymode[0] = BI_PHYMODE_ZMII;
		bis->bi_phymode[1] = BI_PHYMODE_ZMII;
		bis->bi_phymode[2] = BI_PHYMODE_ZMII;
		bis->bi_phymode[3] = BI_PHYMODE_ZMII;
		break;
	}

	/* Ensure we setup mdio for this devnum and ONLY this devnum */
	zmiifer |= (ZMII_FER_MDI) << ZMII_FER_V(devnum);

	out_be32((void *)ZMII_FER, zmiifer);
	out_be32((void *)RGMII_FER, rmiifer);

	return ((int)pfc1);
}
#endif	/* CONFIG_440_GX */

#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
{
	unsigned long zmiifer=0x0;
	unsigned long pfc1;

	mfsdr(sdr_pfc1, pfc1);
	pfc1 &= SDR0_PFC1_SELECT_MASK;

	switch (pfc1) {
	case SDR0_PFC1_SELECT_CONFIG_2:
		/* 1 x GMII port */
		out_be32((void *)ZMII_FER, 0x00);
		out_be32((void *)RGMII_FER, 0x00000037);
		bis->bi_phymode[0] = BI_PHYMODE_GMII;
		bis->bi_phymode[1] = BI_PHYMODE_NONE;
		break;
	case SDR0_PFC1_SELECT_CONFIG_4:
		/* 2 x RGMII ports */
		out_be32((void *)ZMII_FER, 0x00);
		out_be32((void *)RGMII_FER, 0x00000055);
		bis->bi_phymode[0] = BI_PHYMODE_RGMII;
		bis->bi_phymode[1] = BI_PHYMODE_RGMII;
		break;
	case SDR0_PFC1_SELECT_CONFIG_6:
		/* 2 x SMII ports */
		out_be32((void *)ZMII_FER,
			 ((ZMII_FER_SMII) << ZMII_FER_V(0)) |
			 ((ZMII_FER_SMII) << ZMII_FER_V(1)));
		out_be32((void *)RGMII_FER, 0x00000000);
		bis->bi_phymode[0] = BI_PHYMODE_SMII;
		bis->bi_phymode[1] = BI_PHYMODE_SMII;
		break;
	case SDR0_PFC1_SELECT_CONFIG_1_2:
		/* only 1 x MII supported */
		out_be32((void *)ZMII_FER, (ZMII_FER_MII) << ZMII_FER_V(0));
		out_be32((void *)RGMII_FER, 0x00000000);
		bis->bi_phymode[0] = BI_PHYMODE_MII;
		bis->bi_phymode[1] = BI_PHYMODE_NONE;
		break;
	default:
		break;
	}

	/* Ensure we setup mdio for this devnum and ONLY this devnum */
	zmiifer = in_be32((void *)ZMII_FER);
	zmiifer |= (ZMII_FER_MDI) << ZMII_FER_V(devnum);
	out_be32((void *)ZMII_FER, zmiifer);

	return ((int)0x0);
}
#endif	/* CONFIG_440EPX */

#if defined(CONFIG_405EX)
int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
{
	u32 rgmiifer = 0;

	/*
	 * The 405EX(r)'s RGMII bridge can operate in one of several
	 * modes, only one of which (2 x RGMII) allows the
	 * simultaneous use of both EMACs on the 405EX.
	 */

	switch (CONFIG_EMAC_PHY_MODE) {

	case EMAC_PHY_MODE_NONE:
		/* No ports */
		rgmiifer |= RGMII_FER_DIS	<< 0;
		rgmiifer |= RGMII_FER_DIS	<< 4;
		out_be32((void *)RGMII_FER, rgmiifer);
		bis->bi_phymode[0] = BI_PHYMODE_NONE;
		bis->bi_phymode[1] = BI_PHYMODE_NONE;
		break;
	case EMAC_PHY_MODE_NONE_RGMII:
		/* 1 x RGMII port on channel 0 */
		rgmiifer |= RGMII_FER_RGMII	<< 0;
		rgmiifer |= RGMII_FER_DIS	<< 4;
		out_be32((void *)RGMII_FER, rgmiifer);
		bis->bi_phymode[0] = BI_PHYMODE_RGMII;
		bis->bi_phymode[1] = BI_PHYMODE_NONE;
		break;
	case EMAC_PHY_MODE_RGMII_NONE:
		/* 1 x RGMII port on channel 1 */
		rgmiifer |= RGMII_FER_DIS	<< 0;
		rgmiifer |= RGMII_FER_RGMII	<< 4;
		out_be32((void *)RGMII_FER, rgmiifer);
		bis->bi_phymode[0] = BI_PHYMODE_NONE;
		bis->bi_phymode[1] = BI_PHYMODE_RGMII;
		break;
	case EMAC_PHY_MODE_RGMII_RGMII:
		/* 2 x RGMII ports */
		rgmiifer |= RGMII_FER_RGMII	<< 0;
		rgmiifer |= RGMII_FER_RGMII	<< 4;
		out_be32((void *)RGMII_FER, rgmiifer);
		bis->bi_phymode[0] = BI_PHYMODE_RGMII;
		bis->bi_phymode[1] = BI_PHYMODE_RGMII;
		break;
	case EMAC_PHY_MODE_NONE_GMII:
		/* 1 x GMII port on channel 0 */
		rgmiifer |= RGMII_FER_GMII	<< 0;
		rgmiifer |= RGMII_FER_DIS	<< 4;
		out_be32((void *)RGMII_FER, rgmiifer);
		bis->bi_phymode[0] = BI_PHYMODE_GMII;
		bis->bi_phymode[1] = BI_PHYMODE_NONE;
		break;
	case EMAC_PHY_MODE_NONE_MII:
		/* 1 x MII port on channel 0 */
		rgmiifer |= RGMII_FER_MII	<< 0;
		rgmiifer |= RGMII_FER_DIS	<< 4;
		out_be32((void *)RGMII_FER, rgmiifer);
		bis->bi_phymode[0] = BI_PHYMODE_MII;
		bis->bi_phymode[1] = BI_PHYMODE_NONE;
		break;
	case EMAC_PHY_MODE_GMII_NONE:
		/* 1 x GMII port on channel 1 */
		rgmiifer |= RGMII_FER_DIS	<< 0;
		rgmiifer |= RGMII_FER_GMII	<< 4;
		out_be32((void *)RGMII_FER, rgmiifer);
		bis->bi_phymode[0] = BI_PHYMODE_NONE;
		bis->bi_phymode[1] = BI_PHYMODE_GMII;
		break;
	case EMAC_PHY_MODE_MII_NONE:
		/* 1 x MII port on channel 1 */
		rgmiifer |= RGMII_FER_DIS	<< 0;
		rgmiifer |= RGMII_FER_MII	<< 4;
		out_be32((void *)RGMII_FER, rgmiifer);
		bis->bi_phymode[0] = BI_PHYMODE_NONE;
		bis->bi_phymode[1] = BI_PHYMODE_MII;
		break;
	default:
		break;
	}

	/* Ensure we setup mdio for this devnum and ONLY this devnum */
	rgmiifer = in_be32((void *)RGMII_FER);
	rgmiifer |= (1 << (19-devnum));
	out_be32((void *)RGMII_FER, rgmiifer);

	return ((int)0x0);
}
#endif  /* CONFIG_405EX */

#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
{
	u32 eth_cfg;
	u32 zmiifer;		/* ZMII0_FER reg. */
	u32 rmiifer;		/* RGMII0_FER reg. Bridge 0 */
	u32 rmiifer1;		/* RGMII0_FER reg. Bridge 1 */
	int mode;

	zmiifer  = 0;
	rmiifer  = 0;
	rmiifer1 = 0;

#if defined(CONFIG_460EX)
	mode = 9;
	mfsdr(SDR0_ETH_CFG, eth_cfg);
	if (((eth_cfg & SDR0_ETH_CFG_SGMII0_ENABLE) > 0) &&
	    ((eth_cfg & SDR0_ETH_CFG_SGMII1_ENABLE) > 0))
		mode = 11; /* config SGMII */
#else
	mode = 10;
	mfsdr(SDR0_ETH_CFG, eth_cfg);
	if (((eth_cfg & SDR0_ETH_CFG_SGMII0_ENABLE) > 0) &&
	    ((eth_cfg & SDR0_ETH_CFG_SGMII1_ENABLE) > 0) &&
	    ((eth_cfg & SDR0_ETH_CFG_SGMII2_ENABLE) > 0))
		mode = 12; /* config SGMII */
#endif

	/* TODO:
	 * NOTE: 460GT has 2 RGMII bridge cores:
	 *		emac0 ------ RGMII0_BASE
	 *		           |
	 *		emac1 -----+
	 *
	 *		emac2 ------ RGMII1_BASE
	 *		           |
	 *		emac3 -----+
	 *
	 *	460EX has 1 RGMII bridge core:
	 *	and RGMII1_BASE is disabled
	 *		emac0 ------ RGMII0_BASE
	 *		           |
	 *		emac1 -----+
	 */

	/*
	 * Right now only 2*RGMII is supported. Please extend when needed.
	 * sr - 2008-02-19
	 * Add SGMII support.
	 * vg - 2008-07-28
	 */
	switch (mode) {
	case 1:
		/* 1 MII - 460EX */
		/* GMC0 EMAC4_0, ZMII Bridge */
		zmiifer |= ZMII_FER_MII << ZMII_FER_V(0);
		bis->bi_phymode[0] = BI_PHYMODE_MII;
		bis->bi_phymode[1] = BI_PHYMODE_NONE;
		bis->bi_phymode[2] = BI_PHYMODE_NONE;
		bis->bi_phymode[3] = BI_PHYMODE_NONE;
		break;
	case 2:
		/* 2 MII - 460GT */
		/* GMC0 EMAC4_0, GMC1 EMAC4_2, ZMII Bridge */
		zmiifer |= ZMII_FER_MII << ZMII_FER_V(0);
		zmiifer |= ZMII_FER_MII << ZMII_FER_V(2);
		bis->bi_phymode[0] = BI_PHYMODE_MII;
		bis->bi_phymode[1] = BI_PHYMODE_NONE;
		bis->bi_phymode[2] = BI_PHYMODE_MII;
		bis->bi_phymode[3] = BI_PHYMODE_NONE;
		break;
	case 3:
		/* 2 RMII - 460EX */
		/* GMC0 EMAC4_0, GMC0 EMAC4_1, ZMII Bridge */
		zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0);
		zmiifer |= ZMII_FER_RMII << ZMII_FER_V(1);
		bis->bi_phymode[0] = BI_PHYMODE_RMII;
		bis->bi_phymode[1] = BI_PHYMODE_RMII;
		bis->bi_phymode[2] = BI_PHYMODE_NONE;
		bis->bi_phymode[3] = BI_PHYMODE_NONE;
		break;
	case 4:
		/* 4 RMII - 460GT */
		/* GMC0 EMAC4_0, GMC0 EMAC4_1, GMC1 EMAC4_2, GMC1, EMAC4_3 */
		/* ZMII Bridge */
		zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0);
		zmiifer |= ZMII_FER_RMII << ZMII_FER_V(1);
		zmiifer |= ZMII_FER_RMII << ZMII_FER_V(2);
		zmiifer |= ZMII_FER_RMII << ZMII_FER_V(3);
		bis->bi_phymode[0] = BI_PHYMODE_RMII;
		bis->bi_phymode[1] = BI_PHYMODE_RMII;
		bis->bi_phymode[2] = BI_PHYMODE_RMII;
		bis->bi_phymode[3] = BI_PHYMODE_RMII;
		break;
	case 5:
		/* 2 SMII - 460EX */
		/* GMC0 EMAC4_0, GMC0 EMAC4_1, ZMII Bridge */
		zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0);
		zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1);
		bis->bi_phymode[0] = BI_PHYMODE_SMII;
		bis->bi_phymode[1] = BI_PHYMODE_SMII;
		bis->bi_phymode[2] = BI_PHYMODE_NONE;
		bis->bi_phymode[3] = BI_PHYMODE_NONE;
		break;
	case 6:
		/* 4 SMII - 460GT */
		/* GMC0 EMAC4_0, GMC0 EMAC4_1, GMC0 EMAC4_3, GMC0 EMAC4_3 */
		/* ZMII Bridge */
		zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0);
		zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1);
		zmiifer |= ZMII_FER_SMII << ZMII_FER_V(2);
		zmiifer |= ZMII_FER_SMII << ZMII_FER_V(3);
		bis->bi_phymode[0] = BI_PHYMODE_SMII;
		bis->bi_phymode[1] = BI_PHYMODE_SMII;
		bis->bi_phymode[2] = BI_PHYMODE_SMII;
		bis->bi_phymode[3] = BI_PHYMODE_SMII;
		break;
	case 7:
		/* This is the default mode that we want for board bringup - Maple */
		/* 1 GMII - 460EX */
		/* GMC0 EMAC4_0, RGMII Bridge 0 */
		rmiifer |= RGMII_FER_MDIO(0);

		if (devnum == 0) {
			rmiifer |= RGMII_FER_GMII << RGMII_FER_V(2); /* CH0CFG - EMAC0 */
			bis->bi_phymode[0] = BI_PHYMODE_GMII;
			bis->bi_phymode[1] = BI_PHYMODE_NONE;
			bis->bi_phymode[2] = BI_PHYMODE_NONE;
			bis->bi_phymode[3] = BI_PHYMODE_NONE;
		} else {
			rmiifer |= RGMII_FER_GMII << RGMII_FER_V(3); /* CH1CFG - EMAC1 */
			bis->bi_phymode[0] = BI_PHYMODE_NONE;
			bis->bi_phymode[1] = BI_PHYMODE_GMII;
			bis->bi_phymode[2] = BI_PHYMODE_NONE;
			bis->bi_phymode[3] = BI_PHYMODE_NONE;
		}
		break;
	case 8:
		/* 2 GMII - 460GT */
		/* GMC0 EMAC4_0, RGMII Bridge 0 */
		/* GMC1 EMAC4_2, RGMII Bridge 1 */
		rmiifer |= RGMII_FER_GMII << RGMII_FER_V(2);	/* CH0CFG - EMAC0 */
		rmiifer1 |= RGMII_FER_GMII << RGMII_FER_V(2);	/* CH0CFG - EMAC2 */
		rmiifer |= RGMII_FER_MDIO(0);			/* enable MDIO - EMAC0 */
		rmiifer1 |= RGMII_FER_MDIO(0);			/* enable MDIO - EMAC2 */

		bis->bi_phymode[0] = BI_PHYMODE_GMII;
		bis->bi_phymode[1] = BI_PHYMODE_NONE;
		bis->bi_phymode[2] = BI_PHYMODE_GMII;
		bis->bi_phymode[3] = BI_PHYMODE_NONE;
		break;
	case 9:
		/* 2 RGMII - 460EX */
		/* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */
		rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2);
		rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(3);
		rmiifer |= RGMII_FER_MDIO(0);			/* enable MDIO - EMAC0 */

		bis->bi_phymode[0] = BI_PHYMODE_RGMII;
		bis->bi_phymode[1] = BI_PHYMODE_RGMII;
		bis->bi_phymode[2] = BI_PHYMODE_NONE;
		bis->bi_phymode[3] = BI_PHYMODE_NONE;
		break;
	case 10:
		/* 4 RGMII - 460GT */
		/* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */
		/* GMC1 EMAC4_2, GMC1 EMAC4_3, RGMII Bridge 1 */
		rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2);
		rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(3);
		rmiifer1 |= RGMII_FER_RGMII << RGMII_FER_V(2);
		rmiifer1 |= RGMII_FER_RGMII << RGMII_FER_V(3);
		bis->bi_phymode[0] = BI_PHYMODE_RGMII;
		bis->bi_phymode[1] = BI_PHYMODE_RGMII;
		bis->bi_phymode[2] = BI_PHYMODE_RGMII;
		bis->bi_phymode[3] = BI_PHYMODE_RGMII;
		break;
	case 11:
		/* 2 SGMII - 460EX */
		bis->bi_phymode[0] = BI_PHYMODE_SGMII;
		bis->bi_phymode[1] = BI_PHYMODE_SGMII;
		bis->bi_phymode[2] = BI_PHYMODE_NONE;
		bis->bi_phymode[3] = BI_PHYMODE_NONE;
		break;
	case 12:
		/* 3 SGMII - 460GT */
		bis->bi_phymode[0] = BI_PHYMODE_SGMII;
		bis->bi_phymode[1] = BI_PHYMODE_SGMII;
		bis->bi_phymode[2] = BI_PHYMODE_SGMII;
		bis->bi_phymode[3] = BI_PHYMODE_NONE;
		break;
	default:
		break;
	}

	/* Set EMAC for MDIO */
	mfsdr(SDR0_ETH_CFG, eth_cfg);
	eth_cfg |= SDR0_ETH_CFG_MDIO_SEL_EMAC0;
	mtsdr(SDR0_ETH_CFG, eth_cfg);

	out_be32((void *)RGMII_FER, rmiifer);
#if defined(CONFIG_460GT)
	out_be32((void *)RGMII_FER + RGMII1_BASE_OFFSET, rmiifer1);
#endif

	/* bypass the TAHOE0/TAHOE1 cores for U-Boot */
	mfsdr(SDR0_ETH_CFG, eth_cfg);
	eth_cfg |= (SDR0_ETH_CFG_TAHOE0_BYPASS | SDR0_ETH_CFG_TAHOE1_BYPASS);
	mtsdr(SDR0_ETH_CFG, eth_cfg);

	return 0;
}