cpu_init.c

来自「最新版的u-boot,2008-10-18发布」· C语言 代码 · 共 670 行 · 第 1/2 页

/*
 * (C) Copyright 2003
 * Josef Baumgartner <[e-mail]>
 *
 * MCF5282 additionals
 * (C) Copyright 2005
 * BuS Elektronik GmbH & Co. KG <[e-mail]>
 *
 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
 * TsiChung Liew ([e-mail])
 * Hayden Fraser ([e-mail])
 *
 * MCF5275 additions
 * Copyright (C) 2008 Arthur Shipkowski ([e-mail])
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <watchdog.h>
#include <asm/immap.h>

#if defined(CONFIG_M5253)
/*
 * Breath some life into the CPU...
 *
 * Set up the memory map,
 * initialize a bunch of registers,
 * initialize the UPM's
 */
void cpu_init_f(void)
{
	mbar_writeByte(MCFSIM_MPARK, 0x40);	/* 5249 Internal Core takes priority over DMA */
	mbar_writeByte(MCFSIM_SYPCR, 0x00);
	mbar_writeByte(MCFSIM_SWIVR, 0x0f);
	mbar_writeByte(MCFSIM_SWSR, 0x00);
	mbar_writeByte(MCFSIM_SWDICR, 0x00);
	mbar_writeByte(MCFSIM_TIMER1ICR, 0x00);
	mbar_writeByte(MCFSIM_TIMER2ICR, 0x88);
	mbar_writeByte(MCFSIM_I2CICR, 0x00);
	mbar_writeByte(MCFSIM_UART1ICR, 0x00);
	mbar_writeByte(MCFSIM_UART2ICR, 0x00);
	mbar_writeByte(MCFSIM_ICR6, 0x00);
	mbar_writeByte(MCFSIM_ICR7, 0x00);
	mbar_writeByte(MCFSIM_ICR8, 0x00);
	mbar_writeByte(MCFSIM_ICR9, 0x00);
	mbar_writeByte(MCFSIM_QSPIICR, 0x00);

	mbar2_writeLong(MCFSIM_GPIO_INT_EN, 0x00000080);
	mbar2_writeByte(MCFSIM_INTBASE, 0x40);	/* Base interrupts at 64 */
	mbar2_writeByte(MCFSIM_SPURVEC, 0x00);

	/*mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); */ /* Enable a 1 cycle pre-drive cycle on CS1 */

	/*
	 *  Setup chip selects...
	 */

	mbar_writeShort(MCFSIM_CSAR1, CFG_CSAR1);
	mbar_writeShort(MCFSIM_CSCR1, CFG_CSCR1);
	mbar_writeLong(MCFSIM_CSMR1, CFG_CSMR1);

	mbar_writeShort(MCFSIM_CSAR0, CFG_CSAR0);
	mbar_writeShort(MCFSIM_CSCR0, CFG_CSCR0);
	mbar_writeLong(MCFSIM_CSMR0, CFG_CSMR0);

#ifdef CONFIG_FSL_I2C
	CFG_I2C_PINMUX_REG = CFG_I2C_PINMUX_REG & CFG_I2C_PINMUX_CLR;
	CFG_I2C_PINMUX_REG |= CFG_I2C_PINMUX_SET;
#ifdef CFG_I2C2_OFFSET
	CFG_I2C2_PINMUX_REG &= CFG_I2C2_PINMUX_CLR;
	CFG_I2C2_PINMUX_REG |= CFG_I2C2_PINMUX_SET;
#endif
#endif

	/* enable instruction cache now */
	icache_enable();
}

/*initialize higher level parts of CPU like timers */
int cpu_init_r(void)
{
	return (0);
}

void uart_port_conf(void)
{
	/* Setup Ports: */
	switch (CFG_UART_PORT) {
	case 0:
		break;
	case 1:
		break;
	case 2:
		break;
	}
}
#endif				/* #if defined(CONFIG_M5253) */

#if defined(CONFIG_M5271)
void cpu_init_f(void)
{
#ifndef CONFIG_WATCHDOG
	/* Disable the watchdog if we aren't using it */
	mbar_writeShort(MCF_WTM_WCR, 0);
#endif

	/* Set clockspeed to 100MHz */
	mbar_writeShort(MCF_FMPLL_SYNCR,
			MCF_FMPLL_SYNCR_MFD(0) | MCF_FMPLL_SYNCR_RFD(0));
	while (!mbar_readByte(MCF_FMPLL_SYNSR) & MCF_FMPLL_SYNSR_LOCK) ;
}

/*
 * initialize higher level parts of CPU like timers
 */
int cpu_init_r(void)
{
	return (0);
}

void uart_port_conf(void)
{
	/* Setup Ports: */
	switch (CFG_UART_PORT) {
	case 0:
		mbar_writeShort(MCF_GPIO_PAR_UART, MCF_GPIO_PAR_UART_U0TXD |
				MCF_GPIO_PAR_UART_U0RXD);
		break;
	case 1:
		mbar_writeShort(MCF_GPIO_PAR_UART,
				MCF_GPIO_PAR_UART_U1RXD_UART1 |
				MCF_GPIO_PAR_UART_U1TXD_UART1);
		break;
	case 2:
		mbar_writeShort(MCF_GPIO_PAR_UART, 0x3000);
		break;
	}
}
#endif

#if defined(CONFIG_M5272)
/*
 * Breath some life into the CPU...
 *
 * Set up the memory map,
 * initialize a bunch of registers,
 * initialize the UPM's
 */
void cpu_init_f(void)
{
	/* if we come from RAM we assume the CPU is
	 * already initialized.
	 */
#ifndef CONFIG_MONITOR_IS_IN_RAM
	volatile sysctrl_t *sysctrl = (sysctrl_t *) (CFG_MBAR);
	volatile gpio_t *gpio = (gpio_t *) (MMAP_GPIO);
	volatile csctrl_t *csctrl = (csctrl_t *) (MMAP_FBCS);

	sysctrl->sc_scr = CFG_SCR;
	sysctrl->sc_spr = CFG_SPR;

	/* Setup Ports: */
	gpio->gpio_pacnt = CFG_PACNT;
	gpio->gpio_paddr = CFG_PADDR;
	gpio->gpio_padat = CFG_PADAT;
	gpio->gpio_pbcnt = CFG_PBCNT;
	gpio->gpio_pbddr = CFG_PBDDR;
	gpio->gpio_pbdat = CFG_PBDAT;
	gpio->gpio_pdcnt = CFG_PDCNT;

	/* Memory Controller: */
	csctrl->cs_br0 = CFG_BR0_PRELIM;
	csctrl->cs_or0 = CFG_OR0_PRELIM;

#if (defined(CFG_OR1_PRELIM) && defined(CFG_BR1_PRELIM))
	csctrl->cs_br1 = CFG_BR1_PRELIM;
	csctrl->cs_or1 = CFG_OR1_PRELIM;
#endif

#if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM)
	csctrl->cs_br2 = CFG_BR2_PRELIM;
	csctrl->cs_or2 = CFG_OR2_PRELIM;
#endif

#if defined(CFG_OR3_PRELIM) && defined(CFG_BR3_PRELIM)
	csctrl->cs_br3 = CFG_BR3_PRELIM;
	csctrl->cs_or3 = CFG_OR3_PRELIM;
#endif

#if defined(CFG_OR4_PRELIM) && defined(CFG_BR4_PRELIM)
	csctrl->cs_br4 = CFG_BR4_PRELIM;
	csctrl->cs_or4 = CFG_OR4_PRELIM;
#endif

#if defined(CFG_OR5_PRELIM) && defined(CFG_BR5_PRELIM)
	csctrl->cs_br5 = CFG_BR5_PRELIM;
	csctrl->cs_or5 = CFG_OR5_PRELIM;
#endif

#if defined(CFG_OR6_PRELIM) && defined(CFG_BR6_PRELIM)
	csctrl->cs_br6 = CFG_BR6_PRELIM;
	csctrl->cs_or6 = CFG_OR6_PRELIM;
#endif

#if defined(CFG_OR7_PRELIM) && defined(CFG_BR7_PRELIM)
	csctrl->cs_br7 = CFG_BR7_PRELIM;
	csctrl->cs_or7 = CFG_OR7_PRELIM;
#endif

#endif				/* #ifndef CONFIG_MONITOR_IS_IN_RAM */

	/* enable instruction cache now */
	icache_enable();

}

/*
 * initialize higher level parts of CPU like timers
 */
int cpu_init_r(void)
{
	return (0);
}

void uart_port_conf(void)
{
	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;

	/* Setup Ports: */
	switch (CFG_UART_PORT) {
	case 0:
		gpio->gpio_pbcnt &= ~(GPIO_PBCNT_PB0MSK | GPIO_PBCNT_PB1MSK);
		gpio->gpio_pbcnt |= (GPIO_PBCNT_URT0_TXD | GPIO_PBCNT_URT0_RXD);
		break;
	case 1:
		gpio->gpio_pdcnt &= ~(GPIO_PDCNT_PD1MSK | GPIO_PDCNT_PD4MSK);
		gpio->gpio_pdcnt |= (GPIO_PDCNT_URT1_RXD | GPIO_PDCNT_URT1_TXD);
		break;
	}
}
#endif				/* #if defined(CONFIG_M5272) */

#if defined(CONFIG_M5275)

/*
 * Breathe some life into the CPU...
 *
 * Set up the memory map,
 * initialize a bunch of registers,
 * initialize the UPM's
 */
void cpu_init_f(void)
{
	/* if we come from RAM we assume the CPU is
	 * already initialized.
	 */

#ifndef CONFIG_MONITOR_IS_IN_RAM
	volatile wdog_t *wdog_reg = (wdog_t *)(MMAP_WDOG);
	volatile gpio_t *gpio_reg = (gpio_t *)(MMAP_GPIO);
	volatile csctrl_t *csctrl_reg = (csctrl_t *)(MMAP_FBCS);

	/* Kill watchdog so we can initialize the PLL */
	wdog_reg->wcr = 0;

	/* Memory Controller: */
	/* Flash */
	csctrl_reg->ar0 = CFG_AR0_PRELIM;
	csctrl_reg->cr0 = CFG_CR0_PRELIM;
	csctrl_reg->mr0 = CFG_MR0_PRELIM;

#if (defined(CFG_AR1_PRELIM) && defined(CFG_CR1_PRELIM) && defined(CFG_MR1_PRELIM))
	csctrl_reg->ar1 = CFG_AR1_PRELIM;
	csctrl_reg->cr1 = CFG_CR1_PRELIM;
	csctrl_reg->mr1 = CFG_MR1_PRELIM;
#endif

#if (defined(CFG_AR2_PRELIM) && defined(CFG_CR2_PRELIM) && defined(CFG_MR2_PRELIM))
	csctrl_reg->ar2 = CFG_AR2_PRELIM;
	csctrl_reg->cr2 = CFG_CR2_PRELIM;
	csctrl_reg->mr2 = CFG_MR2_PRELIM;
#endif

#if (defined(CFG_AR3_PRELIM) && defined(CFG_CR3_PRELIM) && defined(CFG_MR3_PRELIM))
	csctrl_reg->ar3 = CFG_AR3_PRELIM;
	csctrl_reg->cr3 = CFG_CR3_PRELIM;
	csctrl_reg->mr3 = CFG_MR3_PRELIM;
#endif

#if (defined(CFG_AR4_PRELIM) && defined(CFG_CR4_PRELIM) && defined(CFG_MR4_PRELIM))
	csctrl_reg->ar4 = CFG_AR4_PRELIM;
	csctrl_reg->cr4 = CFG_CR4_PRELIM;
	csctrl_reg->mr4 = CFG_MR4_PRELIM;
#endif

#if (defined(CFG_AR5_PRELIM) && defined(CFG_CR5_PRELIM) && defined(CFG_MR5_PRELIM))
	csctrl_reg->ar5 = CFG_AR5_PRELIM;
	csctrl_reg->cr5 = CFG_CR5_PRELIM;
	csctrl_reg->mr5 = CFG_MR5_PRELIM;
#endif

#if (defined(CFG_AR6_PRELIM) && defined(CFG_CR6_PRELIM) && defined(CFG_MR6_PRELIM))
	csctrl_reg->ar6 = CFG_AR6_PRELIM;
	csctrl_reg->cr6 = CFG_CR6_PRELIM;
	csctrl_reg->mr6 = CFG_MR6_PRELIM;
#endif

#if (defined(CFG_AR7_PRELIM) && defined(CFG_CR7_PRELIM) && defined(CFG_MR7_PRELIM))
	csctrl_reg->ar7 = CFG_AR7_PRELIM;
	csctrl_reg->cr7 = CFG_CR7_PRELIM;
	csctrl_reg->mr7 = CFG_MR7_PRELIM;
#endif

#endif				/* #ifndef CONFIG_MONITOR_IS_IN_RAM */

#ifdef CONFIG_FSL_I2C
	CFG_I2C_PINMUX_REG &= CFG_I2C_PINMUX_CLR;
	CFG_I2C_PINMUX_REG |= CFG_I2C_PINMUX_SET;