ppc4xx-sdram.h

来自「最新版的u-boot,2008-10-18发布」· C头文件 代码 · 共 1,425 行 · 第 1/5 页

#define SDRAM_SDTR1_LDOF_MASK		0x80000000
#define SDRAM_SDTR1_LDOF_1_CLK		0x00000000
#define SDRAM_SDTR1_LDOF_2_CLK		0x80000000
#define SDRAM_SDTR1_RTW_MASK		0x00F00000
#define SDRAM_SDTR1_RTW_2_CLK		0x00200000
#define SDRAM_SDTR1_RTW_3_CLK		0x00300000
#define SDRAM_SDTR1_WTWO_MASK		0x000F0000
#define SDRAM_SDTR1_WTWO_0_CLK		0x00000000
#define SDRAM_SDTR1_WTWO_1_CLK		0x00010000
#define SDRAM_SDTR1_RTRO_MASK		0x0000F000
#define SDRAM_SDTR1_RTRO_1_CLK		0x00001000
#define SDRAM_SDTR1_RTRO_2_CLK		0x00002000

/*
 * SDRAM SDTR2 Options
 */
#define SDRAM_SDTR2_RCD_MASK		0xF0000000
#define SDRAM_SDTR2_RCD_1_CLK		0x10000000
#define SDRAM_SDTR2_RCD_2_CLK		0x20000000
#define SDRAM_SDTR2_RCD_3_CLK		0x30000000
#define SDRAM_SDTR2_RCD_4_CLK		0x40000000
#define SDRAM_SDTR2_RCD_5_CLK		0x50000000
#define SDRAM_SDTR2_WTR_MASK		0x0F000000
#define SDRAM_SDTR2_WTR_1_CLK		0x01000000
#define SDRAM_SDTR2_WTR_2_CLK		0x02000000
#define SDRAM_SDTR2_WTR_3_CLK		0x03000000
#define SDRAM_SDTR2_WTR_4_CLK		0x04000000
#define SDRAM_SDTR3_WTR_ENCODE(n)	((((u32)(n))&0xF)<<24)
#define SDRAM_SDTR2_XSNR_MASK		0x00FF0000
#define SDRAM_SDTR2_XSNR_8_CLK		0x00080000
#define SDRAM_SDTR2_XSNR_16_CLK		0x00100000
#define SDRAM_SDTR2_XSNR_32_CLK		0x00200000
#define SDRAM_SDTR2_XSNR_64_CLK		0x00400000
#define SDRAM_SDTR2_WPC_MASK		0x0000F000
#define SDRAM_SDTR2_WPC_2_CLK		0x00002000
#define SDRAM_SDTR2_WPC_3_CLK		0x00003000
#define SDRAM_SDTR2_WPC_4_CLK		0x00004000
#define SDRAM_SDTR2_WPC_5_CLK		0x00005000
#define SDRAM_SDTR2_WPC_6_CLK		0x00006000
#define SDRAM_SDTR3_WPC_ENCODE(n)	((((u32)(n))&0xF)<<12)
#define SDRAM_SDTR2_RPC_MASK		0x00000F00
#define SDRAM_SDTR2_RPC_2_CLK		0x00000200
#define SDRAM_SDTR2_RPC_3_CLK		0x00000300
#define SDRAM_SDTR2_RPC_4_CLK		0x00000400
#define SDRAM_SDTR2_RP_MASK		0x000000F0
#define SDRAM_SDTR2_RP_3_CLK		0x00000030
#define SDRAM_SDTR2_RP_4_CLK		0x00000040
#define SDRAM_SDTR2_RP_5_CLK		0x00000050
#define SDRAM_SDTR2_RP_6_CLK		0x00000060
#define SDRAM_SDTR2_RP_7_CLK		0x00000070
#define SDRAM_SDTR2_RRD_MASK		0x0000000F
#define SDRAM_SDTR2_RRD_2_CLK		0x00000002
#define SDRAM_SDTR2_RRD_3_CLK		0x00000003

/*
 * SDRAM SDTR3 Options
 */
#define SDRAM_SDTR3_RAS_MASK		0x1F000000
#define SDRAM_SDTR3_RAS_ENCODE(n)	((((u32)(n))&0x1F)<<24)
#define SDRAM_SDTR3_RC_MASK		0x001F0000
#define SDRAM_SDTR3_RC_ENCODE(n)	((((u32)(n))&0x1F)<<16)
#define SDRAM_SDTR3_XCS_MASK		0x00001F00
#define SDRAM_SDTR3_XCS			0x00000D00
#define SDRAM_SDTR3_RFC_MASK		0x0000003F
#define SDRAM_SDTR3_RFC_ENCODE(n)	((((u32)(n))&0x3F)<<0)

/*
 * ECC Error Status
 */
#define SDRAM_ECCES_MASK		 PPC_REG_VAL(21, 0x3FFFFF)
#define SDRAM_ECCES_BNCE_MASK		 PPC_REG_VAL(15, 0xFFFF)
#define SDRAM_ECCES_BNCE_ENCODE(lane)	 PPC_REG_VAL(((lane) & 0xF), 1)
#define SDRAM_ECCES_CKBER_MASK		 PPC_REG_VAL(17, 0x3)
#define SDRAM_ECCES_CKBER_NONE		 PPC_REG_VAL(17, 0)
#define SDRAM_ECCES_CKBER_16_ECC_0_3	 PPC_REG_VAL(17, 2)
#define SDRAM_ECCES_CKBER_32_ECC_0_3	 PPC_REG_VAL(17, 1)
#define SDRAM_ECCES_CKBER_32_ECC_4_8	 PPC_REG_VAL(17, 2)
#define SDRAM_ECCES_CKBER_32_ECC_0_8	 PPC_REG_VAL(17, 3)
#define SDRAM_ECCES_CE			 PPC_REG_VAL(18, 1)
#define SDRAM_ECCES_UE			 PPC_REG_VAL(19, 1)
#define SDRAM_ECCES_BKNER_MASK		 PPC_REG_VAL(21, 0x3)
#define SDRAM_ECCES_BK0ER		 PPC_REG_VAL(20, 1)
#define SDRAM_ECCES_BK1ER		 PPC_REG_VAL(21, 1)

/*
 * Memory Bank 0-1 configuration
 */
#define SDRAM_BXCF_M_AM_MASK		0x00000F00	/* Addressing mode	*/
#define SDRAM_BXCF_M_AM_0		0x00000000	/*   Mode 0		*/
#define SDRAM_BXCF_M_AM_1		0x00000100	/*   Mode 1		*/
#define SDRAM_BXCF_M_AM_2		0x00000200	/*   Mode 2		*/
#define SDRAM_BXCF_M_AM_3		0x00000300	/*   Mode 3		*/
#define SDRAM_BXCF_M_AM_4		0x00000400	/*   Mode 4		*/
#define SDRAM_BXCF_M_AM_5		0x00000500	/*   Mode 5		*/
#define SDRAM_BXCF_M_AM_6		0x00000600	/*   Mode 6		*/
#define SDRAM_BXCF_M_AM_7		0x00000700	/*   Mode 7		*/
#define SDRAM_BXCF_M_AM_8		0x00000800	/*   Mode 8		*/
#define SDRAM_BXCF_M_AM_9		0x00000900	/*   Mode 9		*/
#define SDRAM_BXCF_M_BE_MASK		0x00000001	/* Memory Bank Enable	*/
#define SDRAM_BXCF_M_BE_DISABLE		0x00000000	/* Memory Bank Enable	*/
#define SDRAM_BXCF_M_BE_ENABLE		0x00000001	/* Memory Bank Enable	*/

#define SDRAM_RTSR_TRK1SM_MASK		0xC0000000	/* Tracking State Mach 1*/
#define SDRAM_RTSR_TRK1SM_ATBASE	0x00000000	/* atbase state		*/
#define SDRAM_RTSR_TRK1SM_MISSED	0x40000000	/* missed state		*/
#define SDRAM_RTSR_TRK1SM_ATPLS1	0x80000000	/* atpls1 state		*/
#define SDRAM_RTSR_TRK1SM_RESET		0xC0000000	/* reset  state		*/

#define SDR0_MFR_FIXD			0x10000000	/* Workaround for PCI/DMA */

#endif /* CONFIG_SDRAM_PPC4xx_IBM_DDR2 */

#if defined(CONFIG_SDRAM_PPC4xx_DENALI_DDR2)
/*
 * SDRAM Controller
 */
#define DDR0_00				0x00
#define DDR0_00_INT_ACK_MASK		0x7F000000	/* Write only */
#define DDR0_00_INT_ACK_ALL		0x7F000000
#define DDR0_00_INT_ACK_ENCODE(n)	((((u32)(n))&0x7F)<<24)
#define DDR0_00_INT_ACK_DECODE(n)	((((u32)(n))>>24)&0x7F)
/* Status */
#define DDR0_00_INT_STATUS_MASK		0x00FF0000	/* Read only */
/* Bit0. A single access outside the defined PHYSICAL memory space detected. */
#define DDR0_00_INT_STATUS_BIT0		0x00010000
/* Bit1. Multiple accesses outside the defined PHYSICAL memory space detected. */
#define DDR0_00_INT_STATUS_BIT1		0x00020000
/* Bit2. Single correctable ECC event detected */
#define DDR0_00_INT_STATUS_BIT2		0x00040000
/* Bit3. Multiple correctable ECC events detected. */
#define DDR0_00_INT_STATUS_BIT3		0x00080000
/* Bit4. Single uncorrectable ECC event detected. */
#define DDR0_00_INT_STATUS_BIT4		0x00100000
/* Bit5. Multiple uncorrectable ECC events detected. */
#define DDR0_00_INT_STATUS_BIT5		0x00200000
/* Bit6. DRAM initialization complete. */
#define DDR0_00_INT_STATUS_BIT6		0x00400000
/* Bit7. Logical OR of all lower bits. */
#define DDR0_00_INT_STATUS_BIT7		0x00800000

#define DDR0_00_INT_STATUS_ENCODE(n)	((((u32)(n))&0xFF)<<16)
#define DDR0_00_INT_STATUS_DECODE(n)	((((u32)(n))>>16)&0xFF)
#define DDR0_00_DLL_INCREMENT_MASK	0x00007F00
#define DDR0_00_DLL_INCREMENT_ENCODE(n)	((((u32)(n))&0x7F)<<8)
#define DDR0_00_DLL_INCREMENT_DECODE(n)	((((u32)(n))>>8)&0x7F)
#define DDR0_00_DLL_START_POINT_MASK	0x0000007F
#define DDR0_00_DLL_START_POINT_ENCODE(n) ((((u32)(n))&0x7F)<<0)
#define DDR0_00_DLL_START_POINT_DECODE(n) ((((u32)(n))>>0)&0x7F)

#define DDR0_01				0x01
#define DDR0_01_PLB0_DB_CS_LOWER_MASK	0x1F000000
#define DDR0_01_PLB0_DB_CS_LOWER_ENCODE(n) ((((u32)(n))&0x1F)<<24)
#define DDR0_01_PLB0_DB_CS_LOWER_DECODE(n) ((((u32)(n))>>24)&0x1F)
#define DDR0_01_PLB0_DB_CS_UPPER_MASK	0x001F0000
#define DDR0_01_PLB0_DB_CS_UPPER_ENCODE(n) ((((u32)(n))&0x1F)<<16)
#define DDR0_01_PLB0_DB_CS_UPPER_DECODE(n) ((((u32)(n))>>16)&0x1F)
#define DDR0_01_OUT_OF_RANGE_TYPE_MASK	0x00000700	/* Read only */
#define DDR0_01_OUT_OF_RANGE_TYPE_ENCODE(n) ((((u32)(n))&0x7)<<8)
#define DDR0_01_OUT_OF_RANGE_TYPE_DECODE(n) ((((u32)(n))>>8)&0x7)
#define DDR0_01_INT_MASK_MASK		0x000000FF
#define DDR0_01_INT_MASK_ENCODE(n)	((((u32)(n))&0xFF)<<0)
#define DDR0_01_INT_MASK_DECODE(n)	((((u32)(n))>>0)&0xFF)
#define DDR0_01_INT_MASK_ALL_ON		0x000000FF
#define DDR0_01_INT_MASK_ALL_OFF	0x00000000

#define DDR0_02				0x02
#define DDR0_02_MAX_CS_REG_MASK		0x02000000	/* Read only */
#define DDR0_02_MAX_CS_REG_ENCODE(n)	((((u32)(n))&0x2)<<24)
#define DDR0_02_MAX_CS_REG_DECODE(n)	((((u32)(n))>>24)&0x2)
#define DDR0_02_MAX_COL_REG_MASK	0x000F0000	/* Read only */
#define DDR0_02_MAX_COL_REG_ENCODE(n)	((((u32)(n))&0xF)<<16)
#define DDR0_02_MAX_COL_REG_DECODE(n)	((((u32)(n))>>16)&0xF)
#define DDR0_02_MAX_ROW_REG_MASK	0x00000F00	/* Read only */
#define DDR0_02_MAX_ROW_REG_ENCODE(n)	((((u32)(n))&0xF)<<8)
#define DDR0_02_MAX_ROW_REG_DECODE(n)	((((u32)(n))>>8)&0xF)
#define DDR0_02_START_MASK		0x00000001
#define DDR0_02_START_ENCODE(n)		((((u32)(n))&0x1)<<0)
#define DDR0_02_START_DECODE(n)		((((u32)(n))>>0)&0x1)
#define DDR0_02_START_OFF		0x00000000
#define DDR0_02_START_ON		0x00000001

#define DDR0_03				0x03
#define DDR0_03_BSTLEN_MASK		0x07000000
#define DDR0_03_BSTLEN_ENCODE(n)	((((u32)(n))&0x7)<<24)
#define DDR0_03_BSTLEN_DECODE(n)	((((u32)(n))>>24)&0x7)
#define DDR0_03_CASLAT_MASK		0x00070000
#define DDR0_03_CASLAT_ENCODE(n)	((((u32)(n))&0x7)<<16)
#define DDR0_03_CASLAT_DECODE(n)	((((u32)(n))>>16)&0x7)
#define DDR0_03_CASLAT_LIN_MASK		0x00000F00
#define DDR0_03_CASLAT_LIN_ENCODE(n)	((((u32)(n))&0xF)<<8)
#define DDR0_03_CASLAT_LIN_DECODE(n)	((((u32)(n))>>8)&0xF)
#define DDR0_03_INITAREF_MASK		0x0000000F
#define DDR0_03_INITAREF_ENCODE(n)	((((u32)(n))&0xF)<<0)
#define DDR0_03_INITAREF_DECODE(n)	((((u32)(n))>>0)&0xF)

#define DDR0_04				0x04
#define DDR0_04_TRC_MASK		0x1F000000
#define DDR0_04_TRC_ENCODE(n)		((((u32)(n))&0x1F)<<24)
#define DDR0_04_TRC_DECODE(n)		((((u32)(n))>>24)&0x1F)
#define DDR0_04_TRRD_MASK		0x00070000
#define DDR0_04_TRRD_ENCODE(n)		((((u32)(n))&0x7)<<16)
#define DDR0_04_TRRD_DECODE(n)		((((u32)(n))>>16)&0x7)
#define DDR0_04_TRTP_MASK		0x00000700
#define DDR0_04_TRTP_ENCODE(n)		((((u32)(n))&0x7)<<8)
#define DDR0_04_TRTP_DECODE(n)		((((u32)(n))>>8)&0x7)

#define DDR0_05				0x05
#define DDR0_05_TMRD_MASK		0x1F000000
#define DDR0_05_TMRD_ENCODE(n)		((((u32)(n))&0x1F)<<24)
#define DDR0_05_TMRD_DECODE(n)		((((u32)(n))>>24)&0x1F)
#define DDR0_05_TEMRS_MASK		0x00070000
#define DDR0_05_TEMRS_ENCODE(n)		((((u32)(n))&0x7)<<16)
#define DDR0_05_TEMRS_DECODE(n)		((((u32)(n))>>16)&0x7)
#define DDR0_05_TRP_MASK		0x00000F00
#define DDR0_05_TRP_ENCODE(n)		((((u32)(n))&0xF)<<8)
#define DDR0_05_TRP_DECODE(n)		((((u32)(n))>>8)&0xF)
#define DDR0_05_TRAS_MIN_MASK		0x000000FF
#define DDR0_05_TRAS_MIN_ENCODE(n)	((((u32)(n))&0xFF)<<0)
#define DDR0_05_TRAS_MIN_DECODE(n)	((((u32)(n))>>0)&0xFF)

#define DDR0_06				0x06
#define DDR0_06_WRITEINTERP_MASK	0x01000000
#define DDR0_06_WRITEINTERP_ENCODE(n)	((((u32)(n))&0x1)<<24)
#define DDR0_06_WRITEINTERP_DECODE(n)	((((u32)(n))>>24)&0x1)
#define DDR0_06_TWTR_MASK		0x00070000
#define DDR0_06_TWTR_ENCODE(n)		((((u32)(n))&0x7)<<16)
#define DDR0_06_TWTR_DECODE(n)		((((u32)(n))>>16)&0x7)
#define DDR0_06_TDLL_MASK		0x0000FF00
#define DDR0_06_TDLL_ENCODE(n)		((((u32)(n))&0xFF)<<8)
#define DDR0_06_TDLL_DECODE(n)		((((u32)(n))>>8)&0xFF)
#define DDR0_06_TRFC_MASK		0x0000007F
#define DDR0_06_TRFC_ENCODE(n)		((((u32)(n))&0x7F)<<0)
#define DDR0_06_TRFC_DECODE(n)		((((u32)(n))>>0)&0x7F)

#define DDR0_07				0x07
#define DDR0_07_NO_CMD_INIT_MASK	0x01000000
#define DDR0_07_NO_CMD_INIT_ENCODE(n)	((((u32)(n))&0x1)<<24)
#define DDR0_07_NO_CMD_INIT_DECODE(n)	((((u32)(n))>>24)&0x1)
#define DDR0_07_TFAW_MASK		0x001F0000
#define DDR0_07_TFAW_ENCODE(n)		((((u32)(n))&0x1F)<<16)
#define DDR0_07_TFAW_DECODE(n)		((((u32)(n))>>16)&0x1F)
#define DDR0_07_AUTO_REFRESH_MODE_MASK	0x00000100
#define DDR0_07_AUTO_REFRESH_MODE_ENCODE(n) ((((u32)(n))&0x1)<<8)
#define DDR0_07_AUTO_REFRESH_MODE_DECODE(n) ((((u32)(n))>>8)&0x1)
#define DDR0_07_AREFRESH_MASK		0x00000001
#define DDR0_07_AREFRESH_ENCODE(n)	((((u32)(n))&0x1)<<0)
#define DDR0_07_AREFRESH_DECODE(n)	((((u32)(n))>>0)&0x1)

#define DDR0_08				0x08
#define DDR0_08_WRLAT_MASK		0x07000000
#define DDR0_08_WRLAT_ENCODE(n)		((((u32)(n))&0x7)<<24)
#define DDR0_08_WRLAT_DECODE(n)		((((u32)(n))>>24)&0x7)
#define DDR0_08_TCPD_MASK		0x00FF0000
#define DDR0_08_TCPD_ENCODE(n)		((((u32)(n))&0xFF)<<16)
#define DDR0_08_TCPD_DECODE(n)		((((u32)(n))>>16)&0xFF)
#define DDR0_08_DQS_N_EN_MASK		0x00000100
#define DDR0_08_DQS_N_EN_ENCODE(n)	((((u32)(n))&0x1)<<8)
#define DDR0_08_DQS_N_EN_DECODE(n)	((((u32)(n))>>8)&0x1)
#define DDR0_08_DDRII_SDRAM_MODE_MASK	0x00000001
#define DDR0_08_DDRII_ENCODE(n)		((((u32)(n))&0x1)<<0)
#define DDR0_08_DDRII_DECODE(n)		((((u32)(n))>>0)&0x1)

#define DDR0_09				0x09
#define DDR0_09_OCD_ADJUST_PDN_CS_0_MASK 0x1F000000
#define DDR0_09_OCD_ADJUST_PDN_CS_0_ENCODE(n) ((((u32)(n))&0x1F)<<24)
#define DDR0_09_OCD_ADJUST_PDN_CS_0_DECODE(n) ((((u32)(n))>>24)&0x1F)
#define DDR0_09_RTT_0_MASK		0x00030000
#define DDR0_09_RTT_0_ENCODE(n)		((((u32)(n))&0x3)<<16)
#define DDR0_09_RTT_0_DECODE(n)		((((u32)(n))>>16)&0x3)
#define DDR0_09_WR_DQS_SHIFT_BYPASS_MASK  0x00007F00
#define DDR0_09_WR_DQS_SHIFT_BYPASS_ENCODE(n) ((((u32)(n))&0x7F)<<8)
#define DDR0_09_WR_DQS_SHIFT_BYPASS_DECODE(n) ((((u32)(n))>>8)&0x7F)
#define DDR0_09_WR_DQS_SHIFT_MASK	0x0000007F
#define DDR0_09_WR_DQS_SHIFT_ENCODE(n)	((((u32)(n))&0x7F)<<0)
#define DDR0_09_WR_DQS_SHIFT_DECODE(n)	((((u32)(n))>>0)&0x7F)

#define DDR0_10				0x0A
#define DDR0_10_WRITE_MODEREG_MASK	0x00010000	/* Write only */
#define DDR0_10_WRITE_MODEREG_ENCODE(n)	((((u32)(n))&0x1)<<16)
#define DDR0_10_WRITE_MODEREG_DECODE(n)	((((u32)(n))>>16)&0x1)
#define DDR0_10_CS_MAP_MASK		0x00000300
#define DDR0_10_CS_MAP_NO_MEM		0x00000000
#define DDR0_10_CS_MAP_RANK0_INSTALLED	0x00000100
#define DDR0_10_CS_MAP_RANK1_INSTALLED	0x00000200
#define DDR0_10_CS_MAP_ENCODE(n)	((((u32)(n))&0x3)<<8)