ppc4xx-sdram.h

来自「最新版的u-boot,2008-10-18发布」· C头文件 代码 · 共 1,425 行 · 第 1/5 页

 * SDRAM Read Feedback Delay Control Register
 */
#define SDRAM_RFDC_ARSE_MASK		0x80000000
#define SDRAM_RFDC_ARSE_DISABLE		0x80000000
#define SDRAM_RFDC_ARSE_ENABLE		0x00000000
#define SDRAM_RFDC_RFOS_MASK		0x007F0000
#define SDRAM_RFDC_RFOS_ENCODE(n)	((((u32)(n))&0x7F)<<16)
#define SDRAM_RFDC_RFFD_MASK		0x000007FF
#define SDRAM_RFDC_RFFD_ENCODE(n)	((((u32)(n))&0x7FF)<<0)

#define SDRAM_RFDC_RFFD_MAX		0x7FF

/*
 * SDRAM Delay Line Calibration Register
 */
#define SDRAM_DLCR_DCLM_MASK		0x80000000
#define SDRAM_DLCR_DCLM_MANUAL		0x80000000
#define SDRAM_DLCR_DCLM_AUTO		0x00000000
#define SDRAM_DLCR_DLCR_MASK		0x08000000
#define SDRAM_DLCR_DLCR_CALIBRATE	0x08000000
#define SDRAM_DLCR_DLCR_IDLE		0x00000000
#define SDRAM_DLCR_DLCS_MASK		0x07000000
#define SDRAM_DLCR_DLCS_NOT_RUN		0x00000000
#define SDRAM_DLCR_DLCS_IN_PROGRESS	0x01000000
#define SDRAM_DLCR_DLCS_COMPLETE	0x02000000
#define SDRAM_DLCR_DLCS_CONT_DONE	0x03000000
#define SDRAM_DLCR_DLCS_ERROR		0x04000000
#define SDRAM_DLCR_DLCV_MASK		0x000001FF
#define SDRAM_DLCR_DLCV_ENCODE(n)	((((u32)(n))&0x1FF)<<0)
#define SDRAM_DLCR_DLCV_DECODE(n)	((((u32)(n))>>0)&0x1FF)

/*
 * SDRAM Memory On Die Terimination Control Register
 */
#define SDRAM_MODT_ODTON_DISABLE		PPC_REG_VAL(0, 0)
#define SDRAM_MODT_ODTON_ENABLE			PPC_REG_VAL(0, 1)
#define SDRAM_MODT_EB1W_DISABLE			PPC_REG_VAL(1, 0)
#define SDRAM_MODT_EB1W_ENABLE			PPC_REG_VAL(1, 1)
#define SDRAM_MODT_EB1R_DISABLE			PPC_REG_VAL(2, 0)
#define SDRAM_MODT_EB1R_ENABLE			PPC_REG_VAL(2, 1)
#define SDRAM_MODT_EB0W_DISABLE			PPC_REG_VAL(7, 0)
#define SDRAM_MODT_EB0W_ENABLE			PPC_REG_VAL(7, 1)
#define SDRAM_MODT_EB0R_DISABLE			PPC_REG_VAL(8, 0)
#define SDRAM_MODT_EB0R_ENABLE			PPC_REG_VAL(8, 1)

/*
 * SDRAM Controller On Die Termination Register
 */
#define SDRAM_CODT_ODT_ON			PPC_REG_VAL(0, 1)
#define SDRAM_CODT_ODT_OFF			PPC_REG_VAL(0, 0)
#define SDRAM_CODT_RK1W_ON			PPC_REG_VAL(1, 1)
#define SDRAM_CODT_RK1W_OFF			PPC_REG_VAL(1, 0)
#define SDRAM_CODT_RK1R_ON			PPC_REG_VAL(2, 1)
#define SDRAM_CODT_RK1R_OFF			PPC_REG_VAL(2, 0)
#define SDRAM_CODT_RK0W_ON			PPC_REG_VAL(7, 1)
#define SDRAM_CODT_RK0W_OFF			PPC_REG_VAL(7, 0)
#define SDRAM_CODT_RK0R_ON			PPC_REG_VAL(8, 1)
#define SDRAM_CODT_RK0R_OFF			PPC_REG_VAL(8, 0)
#define SDRAM_CODT_ODTSH_NORMAL			PPC_REG_VAL(10, 0)
#define SDRAM_CODT_ODTSH_REMOVE_ONE_AT_END	PPC_REG_VAL(10, 1)
#define SDRAM_CODT_ODTSH_ADD_ONE_AT_START	PPC_REG_VAL(10, 2)
#define SDRAM_CODT_ODTSH_SHIFT_ONE_EARLIER	PPC_REG_VAL(10, 3)
#define SDRAM_CODT_CODTZ_75OHM			PPC_REG_VAL(11, 0)
#define SDRAM_CODT_CKEG_ON			PPC_REG_VAL(12, 1)
#define SDRAM_CODT_CKEG_OFF			PPC_REG_VAL(12, 0)
#define SDRAM_CODT_CTLG_ON			PPC_REG_VAL(13, 1)
#define SDRAM_CODT_CTLG_OFF			PPC_REG_VAL(13, 0)
#define SDRAM_CODT_FBDG_ON			PPC_REG_VAL(14, 1)
#define SDRAM_CODT_FBDG_OFF			PPC_REG_VAL(14, 0)
#define SDRAM_CODT_FBRG_ON			PPC_REG_VAL(15, 1)
#define SDRAM_CODT_FBRG_OFF			PPC_REG_VAL(15, 0)
#define SDRAM_CODT_CKLZ_36OHM			PPC_REG_VAL(18, 1)
#define SDRAM_CODT_CKLZ_18OHM			PPC_REG_VAL(18, 0)
#define SDRAM_CODT_DQS_VOLTAGE_DDR_MASK		PPC_REG_VAL(26, 1)
#define SDRAM_CODT_DQS_2_5_V_DDR1		PPC_REG_VAL(26, 0)
#define SDRAM_CODT_DQS_1_8_V_DDR2		PPC_REG_VAL(26, 1)
#define SDRAM_CODT_DQS_MASK			PPC_REG_VAL(27, 1)
#define SDRAM_CODT_DQS_DIFFERENTIAL		PPC_REG_VAL(27, 0)
#define SDRAM_CODT_DQS_SINGLE_END		PPC_REG_VAL(27, 1)
#define SDRAM_CODT_CKSE_DIFFERENTIAL		PPC_REG_VAL(28, 0)
#define SDRAM_CODT_CKSE_SINGLE_END		PPC_REG_VAL(28, 1)
#define SDRAM_CODT_FEEBBACK_RCV_SINGLE_END	PPC_REG_VAL(29, 1)
#define SDRAM_CODT_FEEBBACK_DRV_SINGLE_END	PPC_REG_VAL(30, 1)
#define SDRAM_CODT_IO_HIZ			PPC_REG_VAL(31, 0)
#define SDRAM_CODT_IO_NMODE			PPC_REG_VAL(31, 1)

/*
 * SDRAM Initialization Preload Register
 */
#define SDRAM_INITPLR_ENABLE			PPC_REG_VAL(0, 1)
#define SDRAM_INITPLR_DISABLE			PPC_REG_VAL(0, 0)
#define SDRAM_INITPLR_IMWT_MASK			PPC_REG_VAL(8, 0xFF)
#define SDRAM_INITPLR_IMWT_ENCODE(n)		PPC_REG_VAL(8, \
							    (static_cast(u32, \
									 n)) \
							    & 0xFF)
#define SDRAM_INITPLR_ICMD_MASK			PPC_REG_VAL(12, 0x7)
#define SDRAM_INITPLR_ICMD_ENCODE(n)		PPC_REG_VAL(12, \
							    (static_cast(u32, \
									 n)) \
							    & 0x7)
#define SDRAM_INITPLR_IBA_MASK			PPC_REG_VAL(15, 0x7)
#define SDRAM_INITPLR_IBA_ENCODE(n)		PPC_REG_VAL(15, \
							    (static_cast(u32, \
									 n)) \
							    & 0x7)
#define SDRAM_INITPLR_IMA_MASK			PPC_REG_VAL(31, 0x7FFF)
#define SDRAM_INITPLR_IMA_ENCODE(n)		PPC_REG_VAL(31, \
							    (static_cast(u32, \
									 n)) \
							    & 0x7FFF)

/*
 * JEDEC DDR Initialization Commands
 */
#define JEDEC_CMD_NOP				7
#define JEDEC_CMD_PRECHARGE			2
#define JEDEC_CMD_REFRESH			1
#define JEDEC_CMD_EMR				0
#define JEDEC_CMD_READ				5
#define JEDEC_CMD_WRITE				4

/*
 * JEDEC Precharge Command Memory Address Arguments
 */
#define JEDEC_MA_PRECHARGE_ONE			(0 << 10)
#define JEDEC_MA_PRECHARGE_ALL			(1 << 10)

/*
 * JEDEC DDR EMR Command Bank Address Arguments
 */
#define JEDEC_BA_MR				0
#define JEDEC_BA_EMR				1
#define JEDEC_BA_EMR2				2
#define JEDEC_BA_EMR3				3

/*
 * JEDEC DDR Mode Register
 */
#define JEDEC_MA_MR_PDMODE_FAST_EXIT		(0 << 12)
#define JEDEC_MA_MR_PDMODE_SLOW_EXIT		(1 << 12)
#define JEDEC_MA_MR_WR_MASK			(0x7 << 9)
#define JEDEC_MA_MR_WR_DDR1			(0x0 << 9)
#define JEDEC_MA_MR_WR_DDR2_2_CYC		(0x1 << 9)
#define JEDEC_MA_MR_WR_DDR2_3_CYC		(0x2 << 9)
#define JEDEC_MA_MR_WR_DDR2_4_CYC		(0x3 << 9)
#define JEDEC_MA_MR_WR_DDR2_5_CYC		(0x4 << 9)
#define JEDEC_MA_MR_WR_DDR2_6_CYC		(0x5 << 9)
#define JEDEC_MA_MR_DLL_RESET			(1 << 8)
#define JEDEC_MA_MR_MODE_NORMAL			(0 << 8)
#define JEDEC_MA_MR_MODE_TEST			(1 << 8)
#define JEDEC_MA_MR_CL_MASK			(0x7 << 4)
#define JEDEC_MA_MR_CL_DDR1_2_0_CLK		(0x2 << 4)
#define JEDEC_MA_MR_CL_DDR1_2_5_CLK		(0x6 << 4)
#define JEDEC_MA_MR_CL_DDR1_3_0_CLK		(0x3 << 4)
#define JEDEC_MA_MR_CL_DDR2_2_0_CLK		(0x2 << 4)
#define JEDEC_MA_MR_CL_DDR2_3_0_CLK		(0x3 << 4)
#define JEDEC_MA_MR_CL_DDR2_4_0_CLK		(0x4 << 4)
#define JEDEC_MA_MR_CL_DDR2_5_0_CLK		(0x5 << 4)
#define JEDEC_MA_MR_CL_DDR2_6_0_CLK		(0x6 << 4)
#define JEDEC_MA_MR_CL_DDR2_7_0_CLK		(0x7 << 4)
#define JEDEC_MA_MR_BTYP_SEQUENTIAL		(0 << 3)
#define JEDEC_MA_MR_BTYP_INTERLEAVED		(1 << 3)
#define JEDEC_MA_MR_BLEN_MASK			(0x7 << 0)
#define JEDEC_MA_MR_BLEN_4			(2 << 0)
#define JEDEC_MA_MR_BLEN_8			(3 << 0)

/*
 * JEDEC DDR Extended Mode Register
 */
#define JEDEC_MA_EMR_OUTPUT_MASK		(1 << 12)
#define JEDEC_MA_EMR_OUTPUT_ENABLE		(0 << 12)
#define JEDEC_MA_EMR_OUTPUT_DISABLE		(1 << 12)
#define JEDEC_MA_EMR_RQDS_MASK			(1 << 11)
#define JEDEC_MA_EMR_RDQS_DISABLE		(0 << 11)
#define JEDEC_MA_EMR_RDQS_ENABLE		(1 << 11)
#define JEDEC_MA_EMR_DQS_MASK			(1 << 10)
#define JEDEC_MA_EMR_DQS_DISABLE		(1 << 10)
#define JEDEC_MA_EMR_DQS_ENABLE			(0 << 10)
#define JEDEC_MA_EMR_OCD_MASK			(0x7 << 7)
#define JEDEC_MA_EMR_OCD_EXIT			(0 << 7)
#define JEDEC_MA_EMR_OCD_ENTER			(7 << 7)
#define JEDEC_MA_EMR_AL_DDR1_0_CYC		(0 << 3)
#define JEDEC_MA_EMR_AL_DDR2_1_CYC		(1 << 3)
#define JEDEC_MA_EMR_AL_DDR2_2_CYC		(2 << 3)
#define JEDEC_MA_EMR_AL_DDR2_3_CYC		(3 << 3)
#define JEDEC_MA_EMR_AL_DDR2_4_CYC		(4 << 3)
#define JEDEC_MA_EMR_RTT_MASK			(0x11 << 2)
#define JEDEC_MA_EMR_RTT_DISABLED		(0x00 << 2)
#define JEDEC_MA_EMR_RTT_75OHM			(0x01 << 2)
#define JEDEC_MA_EMR_RTT_150OHM			(0x10 << 2)
#define JEDEC_MA_EMR_RTT_50OHM			(0x11 << 2)
#define JEDEC_MA_EMR_ODS_MASK			(1 << 1)
#define JEDEC_MA_EMR_ODS_NORMAL			(0 << 1)
#define JEDEC_MA_EMR_ODS_WEAK			(1 << 1)
#define JEDEC_MA_EMR_DLL_MASK			(1 << 0)
#define JEDEC_MA_EMR_DLL_ENABLE			(0 << 0)
#define JEDEC_MA_EMR_DLL_DISABLE		(1 << 0)

/*
 * JEDEC DDR Extended Mode Register 2
 */
#define JEDEC_MA_EMR2_TEMP_COMMERCIAL		(0 << 7)
#define JEDEC_MA_EMR2_TEMP_INDUSTRIAL		(1 << 7)

/*
 * SDRAM Mode Register (Corresponds 1:1 w/ JEDEC Mode Register)
 */
#define SDRAM_MMODE_WR_MASK			JEDEC_MA_MR_WR_MASK
#define SDRAM_MMODE_WR_DDR1			JEDEC_MA_MR_WR_DDR1
#define SDRAM_MMODE_WR_DDR2_2_CYC		JEDEC_MA_MR_WR_DDR2_2_CYC
#define SDRAM_MMODE_WR_DDR2_3_CYC		JEDEC_MA_MR_WR_DDR2_3_CYC
#define SDRAM_MMODE_WR_DDR2_4_CYC		JEDEC_MA_MR_WR_DDR2_4_CYC
#define SDRAM_MMODE_WR_DDR2_5_CYC		JEDEC_MA_MR_WR_DDR2_5_CYC
#define SDRAM_MMODE_WR_DDR2_6_CYC		JEDEC_MA_MR_WR_DDR2_6_CYC
#define SDRAM_MMODE_DCL_MASK			JEDEC_MA_MR_CL_MASK
#define SDRAM_MMODE_DCL_DDR1_2_0_CLK		JEDEC_MA_MR_CL_DDR1_2_0_CLK
#define SDRAM_MMODE_DCL_DDR1_2_5_CLK		JEDEC_MA_MR_CL_DDR1_2_5_CLK
#define SDRAM_MMODE_DCL_DDR1_3_0_CLK		JEDEC_MA_MR_CL_DDR1_3_0_CLK
#define SDRAM_MMODE_DCL_DDR2_2_0_CLK		JEDEC_MA_MR_CL_DDR2_2_0_CLK
#define SDRAM_MMODE_DCL_DDR2_3_0_CLK		JEDEC_MA_MR_CL_DDR2_3_0_CLK
#define SDRAM_MMODE_DCL_DDR2_4_0_CLK		JEDEC_MA_MR_CL_DDR2_4_0_CLK
#define SDRAM_MMODE_DCL_DDR2_5_0_CLK		JEDEC_MA_MR_CL_DDR2_5_0_CLK
#define SDRAM_MMODE_DCL_DDR2_6_0_CLK		JEDEC_MA_MR_CL_DDR2_6_0_CLK
#define SDRAM_MMODE_DCL_DDR2_7_0_CLK		JEDEC_MA_MR_CL_DDR2_7_0_CLK
#define SDRAM_MMODE_BTYP_SEQUENTIAL		JEDEC_MA_MR_BTYP_SEQUENTIAL
#define SDRAM_MMODE_BTYP_INTERLEAVED		JEDEC_MA_MR_BTYP_INTERLEAVED
#define SDRAM_MMODE_BLEN_MASK			JEDEC_MA_MR_BLEN_MASK
#define SDRAM_MMODE_BLEN_4			JEDEC_MA_MR_BLEN_4
#define SDRAM_MMODE_BLEN_8			JEDEC_MA_MR_BLEN_8

/*
 * SDRAM Extended Mode Register (Corresponds 1:1 w/ JEDEC Extended
 * Mode Register)
 */
#define SDRAM_MEMODE_QOFF_MASK			JEDEC_MA_EMR_OUTPUT_MASK
#define SDRAM_MEMODE_QOFF_DISABLE		JEDEC_MA_EMR_OUTPUT_DISABLE
#define SDRAM_MEMODE_QOFF_ENABLE		JEDEC_MA_EMR_OUTPUT_ENABLE
#define SDRAM_MEMODE_RDQS_MASK			JEDEC_MA_EMR_RQDS_MASK
#define SDRAM_MEMODE_RDQS_DISABLE		JEDEC_MA_EMR_RDQS_DISABLE
#define SDRAM_MEMODE_RDQS_ENABLE		JEDEC_MA_EMR_RDQS_ENABLE
#define SDRAM_MEMODE_DQS_MASK			JEDEC_MA_EMR_DQS_MASK
#define SDRAM_MEMODE_DQS_DISABLE		JEDEC_MA_EMR_DQS_DISABLE
#define SDRAM_MEMODE_DQS_ENABLE			JEDEC_MA_EMR_DQS_ENABLE
#define SDRAM_MEMODE_AL_DDR1_0_CYC		JEDEC_MA_EMR_AL_DDR1_0_CYC
#define SDRAM_MEMODE_AL_DDR2_1_CYC		JEDEC_MA_EMR_AL_DDR2_1_CYC
#define SDRAM_MEMODE_AL_DDR2_2_CYC		JEDEC_MA_EMR_AL_DDR2_2_CYC
#define SDRAM_MEMODE_AL_DDR2_3_CYC		JEDEC_MA_EMR_AL_DDR2_3_CYC
#define SDRAM_MEMODE_AL_DDR2_4_CYC		JEDEC_MA_EMR_AL_DDR2_4_CYC
#define SDRAM_MEMODE_RTT_MASK			JEDEC_MA_EMR_RTT_MASK
#define SDRAM_MEMODE_RTT_DISABLED		JEDEC_MA_EMR_RTT_DISABLED
#define SDRAM_MEMODE_RTT_75OHM			JEDEC_MA_EMR_RTT_75OHM
#define SDRAM_MEMODE_RTT_150OHM			JEDEC_MA_EMR_RTT_150OHM
#define SDRAM_MEMODE_RTT_50OHM			JEDEC_MA_EMR_RTT_50OHM
#define SDRAM_MEMODE_DIC_MASK			JEDEC_MA_EMR_ODS_MASK
#define SDRAM_MEMODE_DIC_NORMAL			JEDEC_MA_EMR_ODS_NORMAL
#define SDRAM_MEMODE_DIC_WEAK			JEDEC_MA_EMR_ODS_WEAK
#define SDRAM_MEMODE_DLL_MASK			JEDEC_MA_EMR_DLL_MASK
#define SDRAM_MEMODE_DLL_DISABLE		JEDEC_MA_EMR_DLL_DISABLE
#define SDRAM_MEMODE_DLL_ENABLE			JEDEC_MA_EMR_DLL_ENABLE

/*
 * SDRAM Clock Timing Register
 */
#define SDRAM_CLKTR_CLKP_MASK		0xC0000000
#define SDRAM_CLKTR_CLKP_0_DEG		0x00000000
#define SDRAM_CLKTR_CLKP_180_DEG_ADV	0x80000000
#define SDRAM_CLKTR_CLKP_90_DEG_ADV	0x40000000
#define SDRAM_CLKTR_CLKP_270_DEG_ADV	0xC0000000

/*
 * SDRAM Write Timing Register
 */
#define SDRAM_WRDTR_LLWP_MASK		0x10000000
#define SDRAM_WRDTR_LLWP_DIS		0x10000000
#define SDRAM_WRDTR_LLWP_1_CYC		0x00000000
#define SDRAM_WRDTR_WTR_MASK		0x0E000000
#define SDRAM_WRDTR_WTR_0_DEG		0x06000000
#define SDRAM_WRDTR_WTR_90_DEG_ADV	0x04000000
#define SDRAM_WRDTR_WTR_180_DEG_ADV	0x02000000
#define SDRAM_WRDTR_WTR_270_DEG_ADV	0x00000000

/*
 * SDRAM SDTR1 Options
 */