ppc4xx-sdram.h

来自「最新版的u-boot,2008-10-18发布」· C头文件 代码 · 共 1,425 行 · 第 1/5 页

/*
 * (C) Copyright 2008
 * Stefan Roese, DENX Software Engineering, [e-mail].
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef _PPC4xx_SDRAM_H_
#define _PPC4xx_SDRAM_H_

#if defined(CONFIG_SDRAM_PPC4xx_IBM_SDRAM)

/*
 * SDRAM Controller
 */

/*
 * XXX - ToDo: Revisit file to change all these lower case defines into
 * upper case. Also needs to be done in the controller setup code too
 * of course. sr, 2008-06-02
 */
#ifndef CONFIG_405EP
#define mem_besra	0x00	/* bus error syndrome reg a		*/
#define mem_besrsa	0x04	/* bus error syndrome reg set a		*/
#define mem_besrb	0x08	/* bus error syndrome reg b		*/
#define mem_besrsb	0x0c	/* bus error syndrome reg set b		*/
#define mem_bear	0x10	/* bus error address reg		*/
#endif
#define mem_mcopt1	0x20	/* memory controller options 1		*/
#define mem_status	0x24	/* memory status			*/
#define mem_rtr		0x30	/* refresh timer reg			*/
#define mem_pmit	0x34	/* power management idle timer		*/
#define mem_mb0cf	0x40	/* memory bank 0 configuration		*/
#define mem_mb1cf	0x44	/* memory bank 1 configuration		*/
#ifndef CONFIG_405EP
#define mem_mb2cf	0x48	/* memory bank 2 configuration		*/
#define mem_mb3cf	0x4c	/* memory bank 3 configuration		*/
#endif
#define mem_sdtr1	0x80	/* timing reg 1				*/
#ifndef CONFIG_405EP
#define mem_ecccf	0x94	/* ECC configuration			*/
#define mem_eccerr	0x98	/* ECC error status			*/
#endif

#endif /* CONFIG_SDRAM_PPC4xx_IBM_SDRAM */

#if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR)

/*
 * Memory controller registers
 */
#define SDRAM_CFG0	0x20	/* memory controller options 0		*/
#define SDRAM_CFG1	0x21	/* memory controller options 1		*/

/*
 * XXX - ToDo: Revisit file to change all these lower case defines into
 * upper case. Also needs to be done in the controller setup code too
 * of course. sr, 2008-06-02
 */
#define mem_besr0_clr	0x0000	/* bus error status reg 0 (clr)		*/
#define mem_besr0_set	0x0004	/* bus error status reg 0 (set)		*/
#define mem_besr1_clr	0x0008	/* bus error status reg 1 (clr)		*/
#define mem_besr1_set	0x000c	/* bus error status reg 1 (set)		*/
#define mem_bear	0x0010	/* bus error address reg		*/
#define mem_mirq_clr	0x0011	/* bus master interrupt (clr)		*/
#define mem_mirq_set	0x0012	/* bus master interrupt (set)		*/
#define mem_slio	0x0018	/* ddr sdram slave interface options	*/
#define mem_cfg0	0x0020	/* ddr sdram options 0			*/
#define mem_cfg1	0x0021	/* ddr sdram options 1			*/
#define mem_devopt	0x0022	/* ddr sdram device options		*/
#define mem_mcsts	0x0024	/* memory controller status		*/
#define mem_rtr		0x0030	/* refresh timer register		*/
#define mem_pmit	0x0034	/* power management idle timer		*/
#define mem_uabba	0x0038	/* plb UABus base address		*/
#define mem_b0cr	0x0040	/* ddr sdram bank 0 configuration	*/
#define mem_b1cr	0x0044	/* ddr sdram bank 1 configuration	*/
#define mem_b2cr	0x0048	/* ddr sdram bank 2 configuration	*/
#define mem_b3cr	0x004c	/* ddr sdram bank 3 configuration	*/
#define mem_tr0		0x0080	/* sdram timing register 0		*/
#define mem_tr1		0x0081	/* sdram timing register 1		*/
#define mem_clktr	0x0082	/* ddr clock timing register		*/
#define mem_wddctr	0x0083	/* write data/dm/dqs clock timing reg	*/
#define mem_dlycal	0x0084	/* delay line calibration register	*/
#define mem_eccesr	0x0098	/* ECC error status			*/

/*
 * Memory Controller Options 0
 */
#define SDRAM_CFG0_DCEN		0x80000000	/* SDRAM Controller Enable	*/
#define SDRAM_CFG0_MCHK_MASK	0x30000000	/* Memory data errchecking mask */
#define SDRAM_CFG0_MCHK_NON	0x00000000	/* No ECC generation		*/
#define SDRAM_CFG0_MCHK_GEN	0x20000000	/* ECC generation		*/
#define SDRAM_CFG0_MCHK_CHK	0x30000000	/* ECC generation and checking	*/
#define SDRAM_CFG0_RDEN		0x08000000	/* Registered DIMM enable	*/
#define SDRAM_CFG0_PMUD		0x04000000	/* Page management unit		*/
#define SDRAM_CFG0_DMWD_MASK	0x02000000	/* DRAM width mask		*/
#define SDRAM_CFG0_DMWD_32	0x00000000	/* 32 bits			*/
#define SDRAM_CFG0_DMWD_64	0x02000000	/* 64 bits			*/
#define SDRAM_CFG0_UIOS_MASK	0x00C00000	/* Unused IO State		*/
#define SDRAM_CFG0_PDP		0x00200000	/* Page deallocation policy	*/

/*
 * Memory Controller Options 1
 */
#define SDRAM_CFG1_SRE		0x80000000	/* Self-Refresh Entry		*/
#define SDRAM_CFG1_PMEN		0x40000000	/* Power Management Enable	*/

/*
 * SDRAM DEVPOT Options
 */
#define SDRAM_DEVOPT_DLL	0x80000000
#define SDRAM_DEVOPT_DS		0x40000000

/*
 * SDRAM MCSTS Options
 */
#define SDRAM_MCSTS_MRSC	0x80000000
#define SDRAM_MCSTS_SRMS	0x40000000
#define SDRAM_MCSTS_CIS		0x20000000

/*
 * SDRAM Refresh Timer Register
 */
#define SDRAM_RTR_RINT_MASK	  0xFFFF0000
#define SDRAM_RTR_RINT_ENCODE(n)  (((n) << 16) & SDRAM_RTR_RINT_MASK)

/*
 * SDRAM UABus Base Address Reg
 */
#define SDRAM_UABBA_UBBA_MASK	0x0000000F

/*
 * Memory Bank 0-7 configuration
 */
#define SDRAM_BXCR_SDBA_MASK	0xff800000	  /* Base address	      */
#define SDRAM_BXCR_SDSZ_MASK	0x000e0000	  /* Size		      */
#define SDRAM_BXCR_SDSZ_8	0x00020000	  /*   8M		      */
#define SDRAM_BXCR_SDSZ_16	0x00040000	  /*  16M		      */
#define SDRAM_BXCR_SDSZ_32	0x00060000	  /*  32M		      */
#define SDRAM_BXCR_SDSZ_64	0x00080000	  /*  64M		      */
#define SDRAM_BXCR_SDSZ_128	0x000a0000	  /* 128M		      */
#define SDRAM_BXCR_SDSZ_256	0x000c0000	  /* 256M		      */
#define SDRAM_BXCR_SDSZ_512	0x000e0000	  /* 512M		      */
#define SDRAM_BXCR_SDAM_MASK	0x0000e000	  /* Addressing mode	      */
#define SDRAM_BXCR_SDAM_1	0x00000000	  /*   Mode 1		      */
#define SDRAM_BXCR_SDAM_2	0x00002000	  /*   Mode 2		      */
#define SDRAM_BXCR_SDAM_3	0x00004000	  /*   Mode 3		      */
#define SDRAM_BXCR_SDAM_4	0x00006000	  /*   Mode 4		      */
#define SDRAM_BXCR_SDBE		0x00000001	  /* Memory Bank Enable	      */

/*
 * SDRAM TR0 Options
 */
#define SDRAM_TR0_SDWR_MASK	0x80000000
#define	 SDRAM_TR0_SDWR_2_CLK	0x00000000
#define	 SDRAM_TR0_SDWR_3_CLK	0x80000000
#define SDRAM_TR0_SDWD_MASK	0x40000000
#define	 SDRAM_TR0_SDWD_0_CLK	0x00000000
#define	 SDRAM_TR0_SDWD_1_CLK	0x40000000
#define SDRAM_TR0_SDCL_MASK	0x01800000
#define	 SDRAM_TR0_SDCL_2_0_CLK 0x00800000
#define	 SDRAM_TR0_SDCL_2_5_CLK 0x01000000
#define	 SDRAM_TR0_SDCL_3_0_CLK 0x01800000
#define SDRAM_TR0_SDPA_MASK	0x000C0000
#define	 SDRAM_TR0_SDPA_2_CLK	0x00040000
#define	 SDRAM_TR0_SDPA_3_CLK	0x00080000
#define	 SDRAM_TR0_SDPA_4_CLK	0x000C0000
#define SDRAM_TR0_SDCP_MASK	0x00030000
#define	 SDRAM_TR0_SDCP_2_CLK	0x00000000
#define	 SDRAM_TR0_SDCP_3_CLK	0x00010000
#define	 SDRAM_TR0_SDCP_4_CLK	0x00020000
#define	 SDRAM_TR0_SDCP_5_CLK	0x00030000
#define SDRAM_TR0_SDLD_MASK	0x0000C000
#define	 SDRAM_TR0_SDLD_1_CLK	0x00000000
#define	 SDRAM_TR0_SDLD_2_CLK	0x00004000
#define SDRAM_TR0_SDRA_MASK	0x0000001C
#define	 SDRAM_TR0_SDRA_6_CLK	0x00000000
#define	 SDRAM_TR0_SDRA_7_CLK	0x00000004
#define	 SDRAM_TR0_SDRA_8_CLK	0x00000008
#define	 SDRAM_TR0_SDRA_9_CLK	0x0000000C
#define	 SDRAM_TR0_SDRA_10_CLK	0x00000010
#define	 SDRAM_TR0_SDRA_11_CLK	0x00000014
#define	 SDRAM_TR0_SDRA_12_CLK	0x00000018
#define	 SDRAM_TR0_SDRA_13_CLK	0x0000001C
#define SDRAM_TR0_SDRD_MASK	0x00000003
#define	 SDRAM_TR0_SDRD_2_CLK	0x00000001
#define	 SDRAM_TR0_SDRD_3_CLK	0x00000002
#define	 SDRAM_TR0_SDRD_4_CLK	0x00000003

/*
 * SDRAM TR1 Options
 */
#define SDRAM_TR1_RDSS_MASK	0xC0000000
#define	 SDRAM_TR1_RDSS_TR0	0x00000000
#define	 SDRAM_TR1_RDSS_TR1	0x40000000
#define	 SDRAM_TR1_RDSS_TR2	0x80000000
#define	 SDRAM_TR1_RDSS_TR3	0xC0000000
#define SDRAM_TR1_RDSL_MASK	0x00C00000
#define	 SDRAM_TR1_RDSL_STAGE1	0x00000000
#define	 SDRAM_TR1_RDSL_STAGE2	0x00400000
#define	 SDRAM_TR1_RDSL_STAGE3	0x00800000
#define SDRAM_TR1_RDCD_MASK	0x00000800
#define	 SDRAM_TR1_RDCD_RCD_0_0 0x00000000
#define	 SDRAM_TR1_RDCD_RCD_1_2 0x00000800
#define SDRAM_TR1_RDCT_MASK	0x000001FF
#define	 SDRAM_TR1_RDCT_ENCODE(x)  (((x) << 0) & SDRAM_TR1_RDCT_MASK)
#define	 SDRAM_TR1_RDCT_DECODE(x)  (((x) & SDRAM_TR1_RDCT_MASK) >> 0)
#define	 SDRAM_TR1_RDCT_MIN	0x00000000
#define	 SDRAM_TR1_RDCT_MAX	0x000001FF

/*
 * SDRAM WDDCTR Options
 */
#define SDRAM_WDDCTR_WRCP_MASK	0xC0000000
#define	 SDRAM_WDDCTR_WRCP_0DEG	  0x00000000
#define	 SDRAM_WDDCTR_WRCP_90DEG  0x40000000
#define	 SDRAM_WDDCTR_WRCP_180DEG 0x80000000
#define SDRAM_WDDCTR_DCD_MASK	0x000001FF

/*
 * SDRAM CLKTR Options
 */
#define SDRAM_CLKTR_CLKP_MASK	0xC0000000
#define	 SDRAM_CLKTR_CLKP_0DEG	  0x00000000
#define	 SDRAM_CLKTR_CLKP_90DEG	  0x40000000
#define	 SDRAM_CLKTR_CLKP_180DEG  0x80000000
#define SDRAM_CLKTR_DCDT_MASK	0x000001FF

/*
 * SDRAM DLYCAL Options
 */
#define SDRAM_DLYCAL_DLCV_MASK	0x000003FC
#define	 SDRAM_DLYCAL_DLCV_ENCODE(x) (((x)<<2) & SDRAM_DLYCAL_DLCV_MASK)
#define	 SDRAM_DLYCAL_DLCV_DECODE(x) (((x) & SDRAM_DLYCAL_DLCV_MASK)>>2)

#endif /* CONFIG_SDRAM_PPC4xx_IBM_DDR */

#if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR2)

#define SDRAM_DLYCAL_DLCV_MASK		0x000003FC
#define SDRAM_DLYCAL_DLCV_ENCODE(x)	(((x)<<2) & SDRAM_DLYCAL_DLCV_MASK)
#define SDRAM_DLYCAL_DLCV_DECODE(x)	(((x) & SDRAM_DLYCAL_DLCV_MASK)>>2)

#if !defined(CONFIG_405EX)
/*
 * Memory queue defines
 */
#define SDRAMQ_DCR_BASE 0x040

#define SDRAM_R0BAS		(SDRAMQ_DCR_BASE+0x0)	/* rank 0 base address & size  */
#define SDRAM_R1BAS		(SDRAMQ_DCR_BASE+0x1)	/* rank 1 base address & size  */
#define SDRAM_R2BAS		(SDRAMQ_DCR_BASE+0x2)	/* rank 2 base address & size  */
#define SDRAM_R3BAS		(SDRAMQ_DCR_BASE+0x3)	/* rank 3 base address & size  */
#define SDRAM_CONF1HB		(SDRAMQ_DCR_BASE+0x5)	/* configuration 1 HB          */
#define SDRAM_CONF1HB_AAFR	0x80000000	/* Address Ack on First Request - Bit 0 */
#define SDRAM_CONF1HB_PRPD	0x00080000	/* PLB Read pipeline Disable - Bit 12 */
#define SDRAM_CONF1HB_PWPD	0x00040000	/* PLB Write pipeline Disable - Bit 13 */
#define SDRAM_CONF1HB_PRW	0x00020000	/* PLB Read Wait - Bit 14 */
#define SDRAM_CONF1HB_RPLM	0x00001000	/* Read Passing Limit 1 - Bits 16..19 */
#define SDRAM_CONF1HB_RPEN	0x00000800	/* Read Passing Enable - Bit 20 */
#define SDRAM_CONF1HB_RFTE	0x00000400	/* Read Flow Through Enable - Bit 21 */
#define SDRAM_CONF1HB_WRCL	0x00000080	/* MCIF Cycle Limit 1 - Bits 22..24 */
#define SDRAM_CONF1HB_MASK	0x0000F380	/* RPLM & WRCL mask */

#define SDRAM_ERRSTATHB		(SDRAMQ_DCR_BASE+0x7)	/* error status HB             */
#define SDRAM_ERRADDUHB		(SDRAMQ_DCR_BASE+0x8)	/* error address upper 32 HB   */
#define SDRAM_ERRADDLHB		(SDRAMQ_DCR_BASE+0x9)	/* error address lower 32 HB   */
#define SDRAM_PLBADDULL		(SDRAMQ_DCR_BASE+0xA)	/* PLB base address upper 32 LL */
#define SDRAM_CONF1LL		(SDRAMQ_DCR_BASE+0xB)	/* configuration 1 LL          */