immap_512x.h

来自「最新版的u-boot,2008-10-18发布」· C头文件 代码 · 共 619 行 · 第 1/2 页

/*
 * MSCAN
 */
typedef struct mscan512x {
	u8 fixme[0x100];
} mscan512x_t;

/*
 * BDLC
 */
typedef struct bdlc512x {
	u8 fixme[0x100];
} bdlc512x_t;

/*
 * SDHC
 */
typedef struct sdhc512x {
	u8 fixme[0x100];
} sdhc512x_t;

/*
 * SPDIF
 */
typedef struct spdif512x {
	u8 fixme[0x100];
} spdif512x_t;

/*
 * I2C
 */
typedef struct i2c512x_dev {
	volatile u32 madr;		/* I2Cn + 0x00 */
	volatile u32 mfdr;		/* I2Cn + 0x04 */
	volatile u32 mcr;		/* I2Cn + 0x08 */
	volatile u32 msr;		/* I2Cn + 0x0C */
	volatile u32 mdr;		/* I2Cn + 0x10 */
	u8 res0[0x0C];
} i2c512x_dev_t;

typedef struct i2c512x {
	i2c512x_dev_t dev[3];
	volatile u32 icr;
	volatile u32 mifr;
	u8 res0[0x98];
} i2c512x_t;

/*
 * AXE
 */
typedef struct axe512x {
	u8 fixme[0x100];
} axe512x_t;

/*
 * DIU
 */
typedef struct diu512x {
	u8 fixme[0x100];
} diu512x_t;

/*
 * CFM
 */
typedef struct cfm512x {
	u8 fixme[0x100];
} cfm512x_t;

/*
 * FEC
 */
typedef struct fec512x {
	u8 fixme[0x800];
} fec512x_t;

/*
 * ULPI
 */
typedef struct ulpi512x {
	u8 fixme[0x600];
} ulpi512x_t;

/*
 * UTMI
 */
typedef struct utmi512x {
	u8 fixme[0x3000];
} utmi512x_t;

/*
 * PCI DMA
 */
typedef struct pcidma512x {
	u8 fixme[0x300];
} pcidma512x_t;

/*
 * IO Control
 */
typedef struct ioctrl512x {
	u32 regs[0x400];
} ioctrl512x_t;

/*
 * IIM
 */
typedef struct iim512x {
	u8 fixme[0x1000];
} iim512x_t;

/*
 * LPC
 */
typedef struct lpc512x {
	u32	cs_cfg[8];	/* Chip Select N Configuration Registers
				   No dedicated entry for CS Boot as == CS0 */
	u32	cs_cr;		/* Chip Select Control Register */
	u32	cs_sr;		/* Chip Select Status Register */
	u32	cs_bcr;		/* Chip Select Burst Control Register */
	u32	cs_dccr;	/* Chip Select Deadcycle Control Register */
	u32	cs_hccr;	/* Chip Select Holdcycle Control Register */
	u8	res0[0xcc];
	u32	sclpc_psr;	/* SCLPC Packet Size Register */
	u32	sclpc_sar;	/* SCLPC Start Address Register */
	u32	sclpc_cr;	/* SCLPC Control Register */
	u32	sclpc_er;	/* SCLPC Enable Register */
	u32	sclpc_nar;	/* SCLPC NextAddress Register */
	u32	sclpc_sr;	/* SCLPC Status Register */
	u32	sclpc_bdr;	/* SCLPC Bytes Done Register */
	u32	emb_scr;	/* EMB Share Counter Register */
	u32	emb_pcr;	/* EMB Pause Control Register */
	u8	res1[0x1c];
	u32	lpc_fdwr;	/* LPC RX/TX FIFO Data Word Register */
	u32	lpc_fsr;	/* LPC RX/TX FIFO Status Register */
	u32	lpc_cr;		/* LPC RX/TX FIFO Control Register */
	u32	lpc_ar;		/* LPC RX/TX FIFO Alarm Register */
	u8	res2[0xb0];
} lpc512x_t;

/*
 * PATA
 */
typedef struct pata512x {
	u8 fixme[0x100];
} pata512x_t;

/*
 * PSC
 */
typedef struct psc512x {
	volatile u8	mode;		/* PSC + 0x00 */
	volatile u8	res0[3];
	union {				/* PSC + 0x04 */
		volatile u16	status;
		volatile u16	clock_select;
	} sr_csr;
#define psc_status	sr_csr.status
#define psc_clock_select sr_csr.clock_select
	volatile u16	res1;
	volatile u8	command;	/* PSC + 0x08 */
	volatile u8	res2[3];
	union {				/* PSC + 0x0c */
		volatile u8	buffer_8;
		volatile u16	buffer_16;
		volatile u32	buffer_32;
	} buffer;
#define psc_buffer_8	buffer.buffer_8
#define psc_buffer_16	buffer.buffer_16
#define psc_buffer_32	buffer.buffer_32
	union {				/* PSC + 0x10 */
		volatile u8	ipcr;
		volatile u8	acr;
	} ipcr_acr;
#define psc_ipcr	ipcr_acr.ipcr
#define psc_acr		ipcr_acr.acr
	volatile u8	res3[3];
	union {				/* PSC + 0x14 */
		volatile u16	isr;
		volatile u16	imr;
	} isr_imr;
#define psc_isr		isr_imr.isr
#define psc_imr		isr_imr.imr
	volatile u16	res4;
	volatile u8	ctur;		/* PSC + 0x18 */
	volatile u8	res5[3];
	volatile u8	ctlr;		/* PSC + 0x1c */
	volatile u8	res6[3];
	volatile u32	ccr;		/* PSC + 0x20 */
	volatile u8	res7[12];
	volatile u8	ivr;		/* PSC + 0x30 */
	volatile u8	res8[3];
	volatile u8	ip;		/* PSC + 0x34 */
	volatile u8	res9[3];
	volatile u8	op1;		/* PSC + 0x38 */
	volatile u8	res10[3];
	volatile u8	op0;		/* PSC + 0x3c */
	volatile u8	res11[3];
	volatile u32	sicr;		/* PSC + 0x40 */
	volatile u8	res12[60];
	volatile u32	tfcmd;		/* PSC + 0x80 */
	volatile u32	tfalarm;	/* PSC + 0x84 */
	volatile u32	tfstat;		/* PSC + 0x88 */
	volatile u32	tfintstat;	/* PSC + 0x8C */
	volatile u32	tfintmask;	/* PSC + 0x90 */
	volatile u32	tfcount;	/* PSC + 0x94 */
	volatile u16	tfwptr;		/* PSC + 0x98 */
	volatile u16	tfrptr;		/* PSC + 0x9A */
	volatile u32	tfsize;		/* PSC + 0x9C */
	volatile u8	res13[28];
	union {				/* PSC + 0xBC */
		volatile u8	buffer_8;
		volatile u16	buffer_16;
		volatile u32	buffer_32;
	} tfdata_buffer;
#define tfdata_8	tfdata_buffer.buffer_8
#define tfdata_16	tfdata_buffer.buffer_16
#define tfdata_32	tfdata_buffer.buffer_32

	volatile u32	rfcmd;		/* PSC + 0xC0 */
	volatile u32	rfalarm;	/* PSC + 0xC4 */
	volatile u32	rfstat;		/* PSC + 0xC8 */
	volatile u32	rfintstat;	/* PSC + 0xCC */
	volatile u32	rfintmask;	/* PSC + 0xD0 */
	volatile u32	rfcount;	/* PSC + 0xD4 */
	volatile u16	rfwptr;		/* PSC + 0xD8 */
	volatile u16	rfrptr;		/* PSC + 0xDA */
	volatile u32	rfsize;		/* PSC + 0xDC */
	volatile u8	res18[28];
	union {				/* PSC + 0xFC */
		volatile u8	buffer_8;
		volatile u16	buffer_16;
		volatile u32	buffer_32;
	} rfdata_buffer;
#define rfdata_8	rfdata_buffer.buffer_8
#define rfdata_16	rfdata_buffer.buffer_16
#define rfdata_32	rfdata_buffer.buffer_32
} psc512x_t;

/*
 * FIFOC
 */
typedef struct fifoc512x {
	u32 fifoc_cmd;
	u32 fifoc_int;
	u32 fifoc_dma;
	u32 fifoc_axe;
	u32 fifoc_debug;
	u8 fixme[0xEC];
} fifoc512x_t;

/*
 * SATA
 */
typedef struct sata512x {
	u8 fixme[0x2000];
} sata512x_t;

typedef struct immap {
	sysconf512x_t		sysconf;	/* System configuration */
	u8			res0[0x700];
	wdt512x_t		wdt;		/* Watch Dog Timer (WDT) */
	rtclk512x_t		rtc;		/* Real Time Clock Module */
	gpt512x_t		gpt;		/* General Purpose Timer */
	ipic512x_t		ipic;		/* Integrated Programmable Interrupt Controller */
	arbiter512x_t		arbiter;	/* CSB Arbiter */
	reset512x_t		reset;		/* Reset Module */
	clk512x_t		clk;		/* Clock Module */
	pmc512x_t		pmc;		/* Power Management Control Module */
	gpio512x_t		gpio;		/* General purpose I/O module */
	u8			res1[0x100];
	mscan512x_t		mscan;		/* MSCAN */
	bdlc512x_t		bdlc;		/* BDLC */
	sdhc512x_t		sdhc;		/* SDHC */
	spdif512x_t		spdif;		/* SPDIF */
	i2c512x_t		i2c;		/* I2C Controllers */
	u8			res2[0x800];
	axe512x_t		axe;		/* AXE */
	diu512x_t		diu;		/* Display Interface Unit */
	cfm512x_t		cfm;		/* Clock Frequency Measurement */
	u8			res3[0x500];
	fec512x_t		fec;		/* Fast Ethernet Controller */
	ulpi512x_t		ulpi;		/* USB ULPI */
	u8			res4[0xa00];
	utmi512x_t		utmi;		/* USB UTMI */
	u8			res5[0x1000];
	pcidma512x_t		pci_dma;	/* PCI DMA */
	pciconf512x_t		pci_conf;	/* PCI Configuration */
	u8			res6[0x80];
	ios512x_t		ios;		/* PCI Sequencer */
	pcictrl512x_t		pci_ctrl;	/* PCI Controller Control and Status */
	u8			res7[0xa00];
	ddr512x_t		mddrc;		/* Multi-port DDR Memory Controller */
	ioctrl512x_t		io_ctrl;	/* IO Control */
	iim512x_t		iim;		/* IC Identification module */
	u8			res8[0x4000];
	lpc512x_t		lpc;		/* LocalPlus Controller */
	pata512x_t		pata;		/* Parallel ATA */
	u8			res9[0xd00];
	psc512x_t		psc[12];	/* PSCs */
	u8			res10[0x300];
	fifoc512x_t		fifoc;		/* FIFO Controller */
	u8			res11[0x2000];
	dma512x_t		dma;		/* DMA */
	u8			res12[0xa800];
	sata512x_t		sata;		/* Serial ATA */
	u8			res13[0xde000];
} immap_t;
#endif /* __IMMAP_512x__ */