cpu_sh7722.h

来自「最新版的u-boot,2008-10-18发布」· C头文件 代码 · 共 1,338 行 · 第 1/3 页

#define DMAOB       0xA454C09C
#define SPLRI       0xA454C0B8
#define SPRRI       0xA454C0BC
#define SPURI       0xA454C0C4
#define SPTIS       0xA454C0C8
#define SPSTS       0xA454C0CC
#define SPCTL       0xA454C0D0
#define SPIRI       0xA454C0D4
#define SPQCF       0xA454C0D8
#define SPQCS       0xA454C0DC
#define SPQCT       0xA454C0E0
#define DPEAK       0xA454C0F0
#define DSLPD       0xA454C0F4
#define DSLLV       0xA454C0F8
#define BRGASEL     0xA454C100
#define BRRA        0xA454C104
#define BRGBSEL     0xA454C108
#define BRRB        0xA454C10C

/*	USB	*/
#define IFR0        0xA4480000
#define ISR0        0xA4480010
#define IER0        0xA4480020
#define EPDR0I      0xA4480030
#define EPDR0O      0xA4480034
#define EPDR0S      0xA4480038
#define EPDR1       0xA448003C
#define EPDR2       0xA4480040
#define EPDR3       0xA4480044
#define EPDR4       0xA4480048
#define EPDR5       0xA448004C
#define EPDR6       0xA4480050
#define EPDR7       0xA4480054
#define EPDR8       0xA4480058
#define EPDR9       0xA448005C
#define EPSZ0O      0xA4480080
#define EPSZ3       0xA4480084
#define EPSZ6       0xA4480088
#define EPSZ9       0xA448008C
#define TRG         0xA44800A0
#define DASTS       0xA44800A4
#define FCLR        0xA44800AA
#define DMA         0xA44800AC
#define EPSTL       0xA44800B2
#define CVR         0xA44800B4
#define TSR         0xA44800B8
#define CTLR        0xA44800BC
#define EPIR        0xA44800C0
#define XVERCR      0xA44800D0
#define STLMR       0xA44800D4

/*	KEYSC	*/
#define KYCR1       0xA44B0000
#define KYCR2       0xA44B0004
#define KYINDR      0xA44B0008
#define KYOUTDR     0xA44B000C

/*	MMCIF	*/
#define CMDR0       0xA4448000
#define CMDR1       0xA4448001
#define CMDR2       0xA4448002
#define CMDR3       0xA4448003
#define CMDR4       0xA4448004
#define CMDR5       0xA4448005
#define CMDSTRT     0xA4448006
#define OPCR        0xA444800A
#define CSTR        0xA444800B
#define INTCR0      0xA444800C
#define INTCR1      0xA444800D
#define INTSTR0     0xA444800E
#define INTSTR1     0xA444800F
#define CLKON       0xA4448010
#define CTOCR       0xA4448011
#define VDCNT       0xA4448012
#define TBCR        0xA4448014
#define MODER       0xA4448016
#define CMDTYR      0xA4448018
#define RSPTYR      0xA4448019
#define TBNCR       0xA444801A
#define RSPR0       0xA4448020
#define RSPR1       0xA4448021
#define RSPR2       0xA4448022
#define RSPR3       0xA4448023
#define RSPR4       0xA4448024
#define RSPR5       0xA4448025
#define RSPR6       0xA4448026
#define RSPR7       0xA4448027
#define RSPR8       0xA4448028
#define RSPR9       0xA4448029
#define RSPR10      0xA444802A
#define RSPR11      0xA444802B
#define RSPR12      0xA444802C
#define RSPR13      0xA444802D
#define RSPR14      0xA444802E
#define RSPR15      0xA444802F
#define RSPR16      0xA4448030
#define RSPRD       0xA4448031
#define DTOUTR      0xA4448032
#define DR          0xA4448040
#define FIFOCLR     0xA4448042
#define DMACR       0xA4448044
#define INTCR2      0xA4448046
#define INTSTR2     0xA4448048

/*	Z3D3	*/
#define DLBI        0xFD980000
#define DLBD0       0xFD980080
#define DLBD1       0xFD980100
#define GEWM        0xFD984000
#define ICD0        0xFD988000
#define ICD1        0xFD989000
#define ICT         0xFD98A000
#define ILM         0xFD98C000
#define FLM0        0xFD98C800
#define FLM1        0xFD98D000
#define FLUT        0xFD98D800
#define Z3D_PC      0xFD98E400
#define Z3D_PCSP    0xFD98E404
#define Z3D_PAR     0xFD98E408
#define Z3D_IMADR   0xFD98E40C
#define Z3D_BTR0    0xFD98E410
#define Z3D_BTR1    0xFD98E414
#define Z3D_BTR2    0xFD98E418
#define Z3D_BTR3    0xFD98E41C
#define Z3D_LC0     0xFD98E420
#define Z3D_LC1     0xFD98E424
#define Z3D_LC2     0xFD98E428
#define Z3D_LC3     0xFD98E42C
#define Z3D_FR0     0xFD98E430
#define Z3D_FR1     0xFD98E434
#define Z3D_FR2     0xFD98E438
#define Z3D_SR      0xFD98E440
#define Z3D_SMDR    0xFD98E444
#define Z3D_PBIR    0xFD98E448
#define Z3D_DMDR    0xFD98E44C
#define Z3D_IREG    0xFD98E460
#define Z3D_AR00    0xFD98E480
#define Z3D_AR01    0xFD98E484
#define Z3D_AR02    0xFD98E488
#define Z3D_AR03    0xFD98E48C
#define Z3D_BR00    0xFD98E490
#define Z3D_BR01    0xFD98E494
#define Z3D_IXR00   0xFD98E4A0
#define Z3D_IXR01   0xFD98E4A4
#define Z3D_IXR02   0xFD98E4A8
#define Z3D_IXR03   0xFD98E4AC
#define Z3D_AR10    0xFD98E4C0
#define Z3D_AR11    0xFD98E4C4
#define Z3D_AR12    0xFD98E4C8
#define Z3D_AR13    0xFD98E4CC
#define Z3D_BR10    0xFD98E4D0
#define Z3D_BR11    0xFD98E4D4
#define Z3D_IXR10   0xFD98E4E0
#define Z3D_IXR11   0xFD98E4E4
#define Z3D_IXR12   0xFD98E4E8
#define Z3D_IXR13   0xFD98E4EC
#define Z3D_AR20    0xFD98E500
#define Z3D_AR21    0xFD98E504
#define Z3D_AR22    0xFD98E508
#define Z3D_AR23    0xFD98E50C
#define Z3D_BR20    0xFD98E510
#define Z3D_BR21    0xFD98E514
#define Z3D_IXR20   0xFD98E520
#define Z3D_IXR21   0xFD98E524
#define Z3D_IXR22   0xFD98E528
#define Z3D_IXR23   0xFD98E52C
#define Z3D_MR0     0xFD98E540
#define Z3D_MR1     0xFD98E544
#define Z3D_MR2     0xFD98E548
#define Z3D_MR3     0xFD98E54C
#define Z3D_WORKRST 0xFD98E558
#define Z3D_WORKWST 0xFD98E55C
#define Z3D_DBADR   0xFD98E560
#define Z3D_DLBPRST 0xFD98E564
#define Z3D_DLBRST  0xFD98E568
#define Z3D_DLBWST  0xFD98E56C
#define Z3D_UDR0    0xFD98E570
#define Z3D_UDR1    0xFD98E574
#define Z3D_UDR2    0xFD98E578
#define Z3D_UDR3    0xFD98E57C
#define Z3D_CCR0    0xFD98E580
#define Z3D_CCR1    0xFD98E584
#define Z3D_EXPR    0xFD98E588
#define Z3D_V0_X    0xFD9A0000
#define Z3D_V0_Y    0xFD9A0004
#define Z3D_V0_Z    0xFD9A0008
#define Z3D_V0_W    0xFD9A000C
#define Z3D_V0_A    0xFD9A0010
#define Z3D_V0_R    0xFD9A0014
#define Z3D_V0_G    0xFD9A0018
#define Z3D_V0_B    0xFD9A001C
#define Z3D_V0_F    0xFD9A0020
#define Z3D_V0_SR   0xFD9A0024
#define Z3D_V0_SG   0xFD9A0028
#define Z3D_V0_SB   0xFD9A002C
#define Z3D_V0_U0   0xFD9A0030
#define Z3D_V0_V0   0xFD9A0034
#define Z3D_V0_U1   0xFD9A0038
#define Z3D_V0_V1   0xFD9A003C
#define Z3D_V1_X    0xFD9A0080
#define Z3D_V1_Y    0xFD9A0084
#define Z3D_V1_Z    0xFD9A0088
#define Z3D_V1_W    0xFD9A008C
#define Z3D_V1_A    0xFD9A0090
#define Z3D_V1_R    0xFD9A0094
#define Z3D_V1_G    0xFD9A0098
#define Z3D_V1_B    0xFD9A009C
#define Z3D_V1_F    0xFD9A00A0
#define Z3D_V1_SR   0xFD9A00A4
#define Z3D_V1_SG   0xFD9A00A8
#define Z3D_V1_SB   0xFD9A00AC
#define Z3D_V1_U0   0xFD9A00B0
#define Z3D_V1_V0   0xFD9A00B4
#define Z3D_V1_U1   0xFD9A00B8
#define Z3D_V1_V1   0xFD9A00BC
#define Z3D_V2_X    0xFD9A0100
#define Z3D_V2_Y    0xFD9A0104
#define Z3D_V2_Z    0xFD9A0108
#define Z3D_V2_W    0xFD9A010C
#define Z3D_V2_A    0xFD9A0110
#define Z3D_V2_R    0xFD9A0114
#define Z3D_V2_G    0xFD9A0118
#define Z3D_V2_B    0xFD9A011C
#define Z3D_V2_F    0xFD9A0120
#define Z3D_V2_SR   0xFD9A0124
#define Z3D_V2_SG   0xFD9A0128
#define Z3D_V2_SB   0xFD9A012C
#define Z3D_V2_U0   0xFD9A0130
#define Z3D_V2_V0   0xFD9A0134
#define Z3D_V2_U1   0xFD9A0138
#define Z3D_V2_V1   0xFD9A013C
#define Z3D_RENDER              0xFD9A0180
#define Z3D_POLYGON_OFFSET      0xFD9A0184
#define Z3D_VERTEX_CONTROL      0xFD9A0200
#define Z3D_STATE_MODE          0xFD9A0204
#define Z3D_FPU_MODE            0xFD9A0318
#define Z3D_SCISSOR_MIN         0xFD9A0400
#define Z3D_SCISSOR_MAX         0xFD9A0404
#define Z3D_TEXTURE_MODE_A      0xFD9A0408
#define Z3D_TEXTURE_MODE_B      0xFD9A040C
#define Z3D_TEXTURE_BASE_HI_A   0xFD9A0418
#define Z3D_TEXTURE_BASE_LO_A   0xFD9A041C
#define Z3D_TEXTURE_BASE_HI_B   0xFD9A0420
#define Z3D_TEXTURE_BASE_LO_B   0xFD9A0424
#define Z3D_TEXTURE_ALPHA_A0    0xFD9A0438
#define Z3D_TEXTURE_ALPHA_A1    0xFD9A043C
#define Z3D_TEXTURE_ALPHA_A2    0xFD9A0440
#define Z3D_TEXTURE_ALPHA_A3    0xFD9A0444
#define Z3D_TEXTURE_ALPHA_A4    0xFD9A0448
#define Z3D_TEXTURE_ALPHA_A5    0xFD9A044C
#define Z3D_TEXTURE_ALPHA_B0    0xFD9A0450
#define Z3D_TEXTURE_ALPHA_B1    0xFD9A0454
#define Z3D_TEXTURE_ALPHA_B2    0xFD9A0458
#define Z3D_TEXTURE_ALPHA_B3    0xFD9A045C
#define Z3D_TEXTURE_ALPHA_B4    0xFD9A0460
#define Z3D_TEXTURE_ALPHA_B5    0xFD9A0464
#define Z3D_TEXTURE_FLUSH       0xFD9A0498
#define Z3D_GAMMA_TABLE0        0xFD9A049C
#define Z3D_GAMMA_TABLE1        0xFD9A04A0
#define Z3D_GAMMA_TABLE2        0xFD9A04A4
#define Z3D_ALPHA_TEST              0xFD9A0800
#define Z3D_STENCIL_TEST            0xFD9A0804
#define Z3D_DEPTH_ROP_BLEND_DITHER  0xFD9A0808
#define Z3D_MASK                    0xFD9A080C
#define Z3D_FBUS_MODE               0xFD9A0810
#define Z3D_GNT_SET                 0xFD9A0814
#define Z3D_BETWEEN_TEST            0xFD9A0818
#define Z3D_FB_BASE                 0xFD9A081C
#define Z3D_LCD_SIZE                0xFD9A0820
#define Z3D_FB_FLUSH                0xFD9A0824
#define Z3D_CACHE_INVALID           0xFD9A0828
#define Z3D_SC_MODE         0xFD9A0830
#define Z3D_SC0_MIN         0xFD9A0834
#define Z3D_SC0_MAX         0xFD9A0838
#define Z3D_SC1_MIN         0xFD9A083C
#define Z3D_SC1_MAX         0xFD9A0840
#define Z3D_SC2_MIN         0xFD9A0844
#define Z3D_SC2_MAX         0xFD9A0848
#define Z3D_SC3_MIN         0xFD9A084C
#define Z3D_SC3_MAX         0xFD9A0850
#define Z3D_READRESET       0xFD9A0854
#define Z3D_DET_MIN         0xFD9A0858
#define Z3D_DET_MAX         0xFD9A085C
#define Z3D_FB_BASE_SR      0xFD9A0860
#define Z3D_LCD_SIZE_SR     0xFD9A0864
#define Z3D_2D_CTRL_STATUS          0xFD9A0C00
#define Z3D_2D_SIZE                 0xFD9A0C04
#define Z3D_2D_SRCLOC               0xFD9A0C08
#define Z3D_2D_DSTLOC               0xFD9A0C0C
#define Z3D_2D_DMAPORT              0xFD9A0C10
#define Z3D_2D_CONSTANT_SOURCE0     0xFD9A0C14
#define Z3D_2D_CONSTANT_SOURCE1     0xFD9A0C18
#define Z3D_2D_STPCOLOR0            0xFD9A0C1C
#define Z3D_2D_STPCOLOR1            0xFD9A0C20
#define Z3D_2D_STPPARAMETER_SET0    0xFD9A0C24
#define Z3D_2D_STPPARAMETER_SET1    0xFD9A0C28
#define Z3D_2D_STPPAT_0     0xFD9A0C40
#define Z3D_2D_STPPAT_1     0xFD9A0C44
#define Z3D_2D_STPPAT_2     0xFD9A0C48
#define Z3D_2D_STPPAT_3     0xFD9A0C4C
#define Z3D_2D_STPPAT_4     0xFD9A0C50
#define Z3D_2D_STPPAT_5     0xFD9A0C54
#define Z3D_2D_STPPAT_6     0xFD9A0C58
#define Z3D_2D_STPPAT_7     0xFD9A0C5C
#define Z3D_2D_STPPAT_8     0xFD9A0C60
#define Z3D_2D_STPPAT_9     0xFD9A0C64
#define Z3D_2D_STPPAT_10    0xFD9A0C68
#define Z3D_2D_STPPAT_11    0xFD9A0C6C
#define Z3D_2D_STPPAT_12    0xFD9A0C70
#define Z3D_2D_STPPAT_13    0xFD9A0C74
#define Z3D_2D_STPPAT_14    0xFD9A0C78
#define Z3D_2D_STPPAT_15    0xFD9A0C7C
#define Z3D_2D_STPPAT_16    0xFD9A0C80
#define Z3D_2D_STPPAT_17    0xFD9A0C84
#define Z3D_2D_STPPAT_18    0xFD9A0C88
#define Z3D_2D_STPPAT_19    0xFD9A0C8C
#define Z3D_2D_STPPAT_20    0xFD9A0C90
#define Z3D_2D_STPPAT_21    0xFD9A0C94
#define Z3D_2D_STPPAT_22    0xFD9A0C98
#define Z3D_2D_STPPAT_23    0xFD9A0C9C
#define Z3D_2D_STPPAT_24    0xFD9A0CA0
#define Z3D_2D_STPPAT_25    0xFD9A0CA4
#define Z3D_2D_STPPAT_26    0xFD9A0CA8
#define Z3D_2D_STPPAT_27    0xFD9A0CAC
#define Z3D_2D_STPPAT_28    0xFD9A0CB0
#define Z3D_2D_STPPAT_29    0xFD9A0CB4
#define Z3D_2D_STPPAT_30    0xFD9A0CB8
#define Z3D_2D_STPPAT_31    0xFD9A0CBC
#define Z3D_WR_CTRL         0xFD9A1000
#define Z3D_WR_P0           0xFD9A1004
#define Z3D_WR_P1           0xFD9A1008
#define Z3D_WR_P2           0xFD9A100C
#define Z3D_WR_FGC          0xFD9A1010
#define Z3D_WR_BGC          0xFD9A1014
#define Z3D_WR_SZ           0xFD9A1018
#define Z3D_WR_PATPARAM     0xFD9A101C
#define Z3D_WR_PAT          0xFD9A1020
#define Z3D_SYS_STATUS      0xFD9A1400
#define Z3D_SYS_RESET       0xFD9A1404
#define Z3D_SYS_CLK         0xFD9A1408
#define Z3D_SYS_CONF        0xFD9A140C
#define Z3D_SYS_VERSION     0xFD9A1410
#define Z3D_SYS_DBINV       0xFD9A1418
#define Z3D_SYS_I2F_FMT     0xFD9A1420
#define Z3D_SYS_I2F_SRC     0xFD9A1424
#define Z3D_SYS_I2F_DST     0xFD9A1428
#define Z3D_SYS_GBCNT       0xFD9A1430
#define Z3D_SYS_BSYCNT      0xFD9A1434
#define Z3D_SYS_INT_STATUS  0xFD9A1450
#define Z3D_SYS_INT_MASK    0xFD9A1454
#define Z3D_SYS_INT_CLEAR   0xFD9A1458
#define TCD0        0xFD9C0000
#define TCD1        0xFD9C0400
#define TCD2        0xFD9C0800
#define TCD3        0xFD9C0C00
#define TCT0        0xFD9C1000
#define TCT1        0xFD9C1400
#define TCT2        0xFD9C1800
#define TCT3        0xFD9C1C00

/*	PFC	*/
#define PACR        0xA4050100
#define PBCR        0xA4050102
#define PCCR        0xA4050104
#define PDCR        0xA4050106
#define PECR        0xA4050108
#define PFCR        0xA405010A
#define PGCR        0xA405010C
#define PHCR        0xA405010E
#define PJCR        0xA4050110
#define PKCR        0xA4050112
#define PLCR        0xA4050114
#define PMCR        0xA4050116
#define PNCR        0xA4050118
#define PQCR        0xA405011A
#define PRCR        0xA405011C
#define PSCR        0xA405011E
#define PTCR        0xA4050140
#define PUCR        0xA4050142
#define PVCR        0xA4050144
#define PWCR        0xA4050146
#define PXCR        0xA4050148
#define PYCR        0xA405014A
#define PZCR        0xA405014C
#define PSELA       0xA405014E
#define PSELB       0xA4050150
#define PSELC       0xA4050152
#define PSELD       0xA4050154
#define PSELE       0xA4050156
#define HIZCRA      0xA4050158
#define HIZCRB      0xA405015A
#define HIZCRC      0xA405015C
#define HIZCRC		0xA405015C
#define MSELCRA		0xA4050180
#define MSELCRB		0xA4050182
#define PULCR		0xA4050184
#define SBSCR		0xA4050186
#define DRVCR		0xA405018A

/*	I/O Port	*/
#define PADR        0xA4050120
#define PBDR        0xA4050122
#define PCDR        0xA4050124
#define PDDR        0xA4050126
#define PEDR        0xA4050128
#define PFDR        0xA405012A
#define PGDR        0xA405012C
#define PHDR        0xA405012E
#define PJDR        0xA4050130
#define PKDR        0xA4050132
#define PLDR        0xA4050134
#define PMDR        0xA4050136
#define PNDR        0xA4050138
#define PQDR        0xA405013A
#define PRDR        0xA405013C
#define PSDR        0xA405013E
#define PTDR        0xA4050160
#define PUDR        0xA4050162
#define PVDR        0xA4050164
#define PWDR        0xA4050166
#define PYDR        0xA4050168
#define PZDR        0xA405016A

/*	UBC	*/
#define CBR0        0xFF200000
#define CRR0        0xFF200004
#define CAR0        0xFF200008
#define CAMR0       0xFF20000C
#define CBR1        0xFF200020
#define CRR1        0xFF200024
#define CAR1        0xFF200028
#define CAMR1       0xFF20002C
#define CDR1        0xFF200030
#define CDMR1       0xFF200034
#define CETR1       0xFF200038
#define CCMFR       0xFF200600
#define CBCR        0xFF200620

/*	H-UDI	*/
#define SDIR        0xFC110000
#define SDDRH       0xFC110008
#define SDDRL       0xFC11000A
#define SDINT       0xFC110018

#endif /* _ASM_CPU_SH7722_H_ */