cpu_sh7722.h

来自「最新版的u-boot,2008-10-18发布」· C头文件 代码 · 共 1,338 行 · 第 1/3 页

/*
 * (C) Copyright 2007 Nobuhiro Iwamatsu <[e-mail]>
 *
 * SH7722 Internal I/O register
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef _ASM_CPU_SH7722_H_
#define _ASM_CPU_SH7722_H_

#define CACHE_OC_NUM_WAYS	4
#define CCR_CACHE_INIT	0x0000090d

/*	EXP	*/
#define TRA		0xFF000020
#define EXPEVT		0xFF000024
#define INTEVT		0xFF000028

/*	MMU	*/
#define PTEH		0xFF000000
#define PTEL		0xFF000004
#define TTB		0xFF000008
#define TEA		0xFF00000C
#define MMUCR		0xFF000010
#define PASCR		0xFF000070
#define IRMCR		0xFF000078

/*	CACHE	*/
#define CCR		0xFF00001C
#define RAMCR		0xFF000074

/*	XY MEMORY	*/
#define XSA		0xFF000050
#define YSA		0xFF000054
#define XDA		0xFF000058
#define YDA		0xFF00005C
#define XPR		0xFF000060
#define YPR		0xFF000064
#define XEA		0xFF000068
#define YEA		0xFF00006C

/*	INTC	*/
#define ICR0		0xA4140000
#define ICR1		0xA414001C
#define INTPRI0		0xA4140010
#define INTREQ0		0xA4140024
#define INTMSK0		0xA4140044
#define INTMSKCLR0	0xA4140064
#define NMIFCR		0xA41400C0
#define USERIMASK	0xA4700000
#define IPRA		0xA4080000
#define IPRB		0xA4080004
#define IPRC		0xA4080008
#define IPRD		0xA408000C
#define IPRE		0xA4080010
#define IPRF		0xA4080014
#define IPRG		0xA4080018
#define IPRH		0xA408001C
#define IPRI		0xA4080020
#define IPRJ		0xA4080024
#define IPRK		0xA4080028
#define IPRL		0xA408002C
#define IMR0		0xA4080080
#define IMR1		0xA4080084
#define IMR2		0xA4080088
#define IMR3		0xA408008C
#define IMR4		0xA4080090
#define IMR5		0xA4080094
#define IMR6		0xA4080098
#define IMR7		0xA408009C
#define IMR8		0xA40800A0
#define IMR9		0xA40800A4
#define IMR10		0xA40800A8
#define IMR11		0xA40800AC
#define IMCR0		0xA40800C0
#define IMCR1		0xA40800C4
#define IMCR2		0xA40800C8
#define IMCR3		0xA40800CC
#define IMCR4		0xA40800D0
#define IMCR5		0xA40800D4
#define IMCR6		0xA40800D8
#define IMCR7		0xA40800DC
#define IMCR8		0xA40800E0
#define IMCR9		0xA40800E4
#define IMCR10		0xA40800E8
#define IMCR11		0xA40800EC
#define MFI_IPRA	0xA40B0000
#define MFI_IPRB	0xA40B0004
#define MFI_IPRC	0xA40B0008
#define MFI_IPRD	0xA40B000C
#define MFI_IPRE	0xA40B0010
#define MFI_IPRF	0xA40B0014
#define MFI_IPRG	0xA40B0018
#define MFI_IPRH	0xA40B001C
#define MFI_IPRI	0xA40B0020
#define MFI_IPRJ	0xA40B0024
#define MFI_IPRK	0xA40B0028
#define MFI_IPRL	0xA40B002C
#define MFI_IMR0	0xA40B0080
#define MFI_IMR1	0xA40B0084
#define MFI_IMR2	0xA40B0088
#define MFI_IMR3	0xA40B008C
#define MFI_IMR4	0xA40B0090
#define MFI_IMR5	0xA40B0094
#define MFI_IMR6	0xA40B0098
#define MFI_IMR7	0xA40B009C
#define MFI_IMR8	0xA40B00A0
#define MFI_IMR9	0xA40B00A4
#define MFI_IMR10	0xA40B00A8
#define MFI_IMR11	0xA40B00AC
#define MFI_IMCR0	0xA40B00C0
#define MFI_IMCR1	0xA40B00C4
#define MFI_IMCR2	0xA40B00C8
#define MFI_IMCR3	0xA40B00CC
#define MFI_IMCR4	0xA40B00D0
#define MFI_IMCR5	0xA40B00D4
#define MFI_IMCR6	0xA40B00D8
#define MFI_IMCR7	0xA40B00DC
#define MFI_IMCR8	0xA40B00E0
#define MFI_IMCR9	0xA40B00E4
#define MFI_IMCR10	0xA40B00E8
#define MFI_IMCR11	0xA40B00EC

/*	BSC	*/
#define CMNCR	    0xFEC10000
#define	CS0BCR	    0xFEC10004
#define CS2BCR      0xFEC10008
#define CS4BCR      0xFEC10010
#define CS5ABCR     0xFEC10014
#define CS5BBCR     0xFEC10018
#define CS6ABCR     0xFEC1001C
#define CS6BBCR     0xFEC10020
#define CS0WCR      0xFEC10024
#define CS2WCR      0xFEC10028
#define CS4WCR      0xFEC10030
#define CS5AWCR     0xFEC10034
#define CS5BWCR     0xFEC10038
#define CS6AWCR     0xFEC1003C
#define CS6BWCR     0xFEC10040
#define RBWTCNT     0xFEC10054

/*	SBSC	*/
#define SBSC_SDCR   0xFE400008
#define SBSC_SDWCR  0xFE40000C
#define SBSC_SDPCR  0xFE400010
#define SBSC_RTCSR  0xFE400014
#define SBSC_RTCNT  0xFE400018
#define SBSC_RTCOR  0xFE40001C
#define SBSC_RFCR   0xFE400020

/*	DMAC	*/
#define SAR_0       0xFE008020
#define DAR_0       0xFE008024
#define TCR_0       0xFE008028
#define CHCR_0      0xFE00802C
#define SAR_1       0xFE008030
#define DAR_1       0xFE008034
#define TCR_1       0xFE008038
#define CHCR_1      0xFE00803C
#define SAR_2       0xFE008040
#define DAR_2       0xFE008044
#define TCR_2       0xFE008048
#define CHCR_2      0xFE00804C
#define SAR_3       0xFE008050
#define DAR_3       0xFE008054
#define TCR_3       0xFE008058
#define CHCR_3      0xFE00805C
#define SAR_4       0xFE008070
#define DAR_4       0xFE008074
#define TCR_4       0xFE008078
#define CHCR_4      0xFE00807C
#define SAR_5       0xFE008080
#define DAR_5       0xFE008084
#define TCR_5       0xFE008088
#define CHCR_5      0xFE00808C
#define SARB_0      0xFE008120
#define DARB_0      0xFE008124
#define TCRB_0      0xFE008128
#define SARB_1      0xFE008130
#define DARB_1      0xFE008134
#define TCRB_1      0xFE008138
#define SARB_2      0xFE008140
#define DARB_2      0xFE008144
#define TCRB_2      0xFE008148
#define SARB_3      0xFE008150
#define DARB_3      0xFE008154
#define TCRB_3      0xFE008158
#define DMAOR       0xFE008060
#define DMARS_0     0xFE009000
#define DMARS_1     0xFE009004
#define DMARS_2     0xFE009008

/*	CPG	*/
#define FRQCR       0xA4150000
#define VCLKCR      0xA4150004
#define SCLKACR     0xA4150008
#define SCLKBCR     0xA415000C
#define PLLCR       0xA4150024
#define DLLFRQ      0xA4150050

/*	LOW POWER MODE	*/
#define STBCR       0xA4150020
#define MSTPCR0     0xA4150030
#define MSTPCR1     0xA4150034
#define MSTPCR2     0xA4150038
#define BAR         0xA4150040

/*	RWDT	*/
#define RWTCNT      0xA4520000
#define RWTCSR      0xA4520004
#define WTCNT	RWTCNT


/*	TMU	*/
#define TSTR        0xFFD80004
#define TCOR0       0xFFD80008
#define TCNT0       0xFFD8000C
#define TCR0        0xFFD80010
#define TCOR1       0xFFD80014
#define TCNT1       0xFFD80018
#define TCR1        0xFFD8001C
#define TCOR2       0xFFD80020
#define TCNT2       0xFFD80024
#define TCR2        0xFFD80028

/*	TPU	*/
#define TPU_TSTR    0xA4C90000
#define TPU_TCR0    0xA4C90010
#define TPU_TMDR0   0xA4C90014
#define TPU_TIOR0   0xA4C90018
#define TPU_TIER0   0xA4C9001C
#define TPU_TSR0    0xA4C90020
#define TPU_TCNT0   0xA4C90024
#define TPU_TGR0A   0xA4C90028
#define TPU_TGR0B   0xA4C9002C
#define TPU_TGR0C   0xA4C90030
#define TPU_TGR0D   0xA4C90034
#define TPU_TCR1    0xA4C90050
#define TPU_TMDR1   0xA4C90054
#define TPU_TIER1   0xA4C9005C
#define TPU_TSR1    0xA4C90060
#define TPU_TCNT1   0xA4C90064
#define TPU_TGR1A   0xA4C90068
#define TPU_TGR1B   0xA4C9006C
#define TPU_TGR1C   0xA4C90070
#define TPU_TGR1D   0xA4C90074
#define TPU_TCR2    0xA4C90090
#define TPU_TMDR2   0xA4C90094
#define TPU_TIER2   0xA4C9009C
#define TPU_TSR2    0xA4C900A0
#define TPU_TCNT2   0xA4C900A4
#define TPU_TGR2A   0xA4C900A8
#define TPU_TGR2B   0xA4C900AC
#define TPU_TGR2C   0xA4C900B0
#define TPU_TGR2D   0xA4C900B4
#define TPU_TCR3    0xA4C900D0
#define TPU_TMDR3   0xA4C900D4
#define TPU_TIER3   0xA4C900DC
#define TPU_TSR3    0xA4C900E0
#define TPU_TCNT3   0xA4C900E4
#define TPU_TGR3A   0xA4C900E8
#define TPU_TGR3B   0xA4C900EC
#define TPU_TGR3C   0xA4C900F0
#define TPU_TGR3D   0xA4C900F4

/*	CMT	*/
#define CMSTR       0xA44A0000
#define CMCSR       0xA44A0060
#define CMCNT       0xA44A0064
#define CMCOR       0xA44A0068

/*	SIO	*/
#define SIOMDR      0xA4500000
#define SIOCTR      0xA4500004
#define SIOSTBCR0   0xA4500008
#define SIOSTBCR1   0xA450000C
#define SIOTDR      0xA4500014
#define SIORDR      0xA4500018
#define SIOSTR      0xA450001C
#define SIOIER      0xA4500020
#define SIOSCR      0xA4500024

/*	SIOF	*/
#define SIMDR0      0xA4410000
#define SISCR0      0xA4410002
#define SITDAR0     0xA4410004
#define SIRDAR0     0xA4410006
#define SICDAR0     0xA4410008
#define SICTR0      0xA441000C
#define SIFCTR0     0xA4410010
#define SISTR0      0xA4410014
#define SIIER0      0xA4410016
#define SITDR0      0xA4410020
#define SIRDR0      0xA4410024
#define SITCR0      0xA4410028
#define SIRCR0      0xA441002C
#define SPICR0      0xA4410030
#define SIMDR1      0xA4420000
#define SISCR1      0xA4420002
#define SITDAR1     0xA4420004
#define SIRDAR1     0xA4420006
#define SICDAR1     0xA4420008
#define SICTR1      0xA442000C
#define SIFCTR1     0xA4420010
#define SISTR1      0xA4420014
#define SIIER1      0xA4420016
#define SITDR1      0xA4420020
#define SIRDR1      0xA4420024
#define SITCR1      0xA4420028
#define SIRCR1      0xA442002C
#define SPICR1      0xA4420030

/*	SCIF	*/
/*
#define SCSMR       0xFFE00000
#define SCBRR       0xFFE00004
#define SCSCR       0xFFE00008
#define SCFTDR      0xFFE0000C
#define SCFSR       0xFFE00010
#define SCFRDR      0xFFE00014
#define SCFCR       0xFFE00018
#define SCFDR       0xFFE0001C
#define SCLSR       0xFFE00024
#define SCSMR1      0xFFE10000
#define SCBRR1      0xFFE10004
#define SCSCR1      0xFFE10008
#define SCFTDR1     0xFFE1000C
#define SCFSR1      0xFFE10010
#define SCFRDR1     0xFFE10014
#define SCFCR1      0xFFE10018
#define SCFDR1      0xFFE1001C
#define SCLSR1      0xFFE10024
#define SCSMR2      0xFFE20000
#define SCBRR2      0xFFE20004
#define SCSCR2      0xFFE20008
#define SCFTDR2     0xFFE2000C
#define SCFSR2      0xFFE20010
#define SCFRDR2     0xFFE20014
#define SCFCR2      0xFFE20018
#define SCFDR2      0xFFE2001C
#define SCLSR2      0xFFE20024
#define SCSMR3      0xFFE30000
#define SCBRR3      0xFFE30004
#define SCSCR3      0xFFE30008
#define SCFTDR3     0xFFE3000C
#define SCFSR3      0xFFE30010
#define SCFRDR3     0xFFE30014
#define SCFCR3      0xFFE30018
#define SCFDR3      0xFFE3001C
#define SCLSR3      0xFFE30024
*/
#define SCIF0_BASE  0xFFE00000

/*	SIM	*/
#define SIM_SCSMR       0xA4490000
#define SIM_SCBRR       0xA4490002
#define SIM_SCSCR       0xA4490004
#define SIM_SCTDR       0xA4490006
#define SIM_SCSSR       0xA4490008
#define SIM_SCRDR       0xA449000A
#define SIM_SCSCMR      0xA449000C
#define SIM_SCSC2R      0xA449000E
#define SIM_SCWAIT      0xA4490010
#define SIM_SCGRD       0xA4490012
#define SIM_SCSMPL      0xA4490014
#define SIM_SCDMAEN     0xA4490016

/*	IrDA	*/
#define IRIF_INIT1      0xA45D0012
#define IRIF_INIT2      0xA45D0014
#define IRIF_RINTCLR    0xA45D0016
#define IRIF_TINTCLR    0xA45D0018
#define IRIF_SIR0       0xA45D0020
#define IRIF_SIR1       0xA45D0022
#define IRIF_SIR2       0xA45D0024
#define IRIF_SIR3       0xA45D0026
#define IRIF_SIR_FRM    0xA45D0028
#define IRIF_SIR_EOF    0xA45D002A
#define IRIF_SIR_FLG    0xA45D002C
#define IRIF_SIR_STS2   0xA45D002E
#define IRIF_UART0      0xA45D0030
#define IRIF_UART1      0xA45D0032
#define IRIF_UART2      0xA45D0034
#define IRIF_UART3      0xA45D0036
#define IRIF_UART4      0xA45D0038
#define IRIF_UART5      0xA45D003A
#define IRIF_UART6      0xA45D003C
#define IRIF_UART7      0xA45D003E
#define IRIF_CRC0       0xA45D0040
#define IRIF_CRC1       0xA45D0042
#define IRIF_CRC2       0xA45D0044
#define IRIF_CRC3       0xA45D0046
#define IRIF_CRC4       0xA45D0048

/*	IIC	*/
#define ICDR0       0xA4470000
#define ICCR0       0xA4470004
#define ICSR0       0xA4470008
#define ICIC0       0xA447000C
#define ICCL0       0xA4470010
#define ICCH0       0xA4470014
#define ICDR1       0xA4750000
#define ICCR1       0xA4750004
#define ICSR1       0xA4750008
#define ICIC1       0xA475000C
#define ICCL1       0xA4750010
#define ICCH1       0xA4750014

/*	FLCTL	*/
#define FLCMNCR     0xA4530000
#define FLCMDCR     0xA4530004
#define FLCMCDR     0xA4530008
#define FLADR       0xA453000C
#define FLDATAR     0xA4530010
#define FLDTCNTR    0xA4530014
#define FLINTDMACR  0xA4530018
#define FLBSYTMR    0xA453001C
#define FLBSYCNT    0xA4530020
#define FLDTFIFO    0xA4530024
#define FLECFIFO    0xA4530028
#define FLTRCR      0xA453002C
#define FLADR2      0xA453003C

/*	MFI	*/
#define MFIIDX      0xA4C10000
#define MFIGSR      0xA4C10004
#define MFISCR      0xA4C10008
#define MFIMCR      0xA4C1000C
#define MFIIICR     0xA4C10010
#define MFIEICR     0xA4C10014
#define MFIADR      0xA4C10018
#define MFIDATA     0xA4C1001C