tqm85xx.h

来自「最新版的u-boot,2008-10-18发布」· C头文件 代码 · 共 728 行 · 第 1/2 页

/*
 * (C) Copyright 2007
 * Thomas Waehner, TQ-System GmbH, [e-mail].
 *
 * (C) Copyright 2005
 * Stefan Roese, DENX Software Engineering, [e-mail].
 *
 * Wolfgang Denk <[e-mail]>
 * Copyright 2004 Freescale Semiconductor.
 * (C) Copyright 2002,2003 Motorola,Inc.
 * Xianghua Xiao <[e-mail]>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * TQM85xx (8560/40/55/41/48) board configuration file
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/* High Level Configuration Options */
#define CONFIG_BOOKE		1	/* BOOKE			*/
#define CONFIG_E500		1	/* BOOKE e500 family		*/
#define CONFIG_MPC85xx		1	/* MPC8540/60/55/41		*/

#define CONFIG_PCI
#define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code	*/
#define CONFIG_PCIX_CHECK		/* PCIX olny works at 66 MHz	*/
#ifdef CONFIG_TQM8548
#define CONFIG_PCI1
#define CONFIG_PCIE1
#define CONFIG_FSL_PCIE_RESET	1	/* need PCIe reset errata	*/
#endif

#define CONFIG_TSEC_ENET		/* tsec ethernet support	*/

#define CONFIG_MISC_INIT_R	1	/* Call misc_init_r		*/

 /*
 * Configuration for big NOR Flashes
 *
 * Define CONFIG_TQM_BIGFLASH for boards with more than 128 MiB NOR Flash.
 * Please be aware, that this changes the whole memory map (new CCSRBAR
 * address, etc). You have to use an adapted Linux kernel or FDT blob
 * if this option is set.
 */
#undef CONFIG_TQM_BIGFLASH

/*
 * NAND flash support (disabled by default)
 *
 * Warning: NAND support will likely increase the U-Boot image size
 * to more than 256 KB. Please adjust TEXT_BASE if necessary.
 */
#undef CONFIG_NAND

/*
 * MPC8540 and MPC8548 don't have CPM module
 */
#if !defined(CONFIG_MPC8540) && !defined(CONFIG_MPC8548)
#define CONFIG_CPM2		1	/* has CPM2			*/
#endif

#define CONFIG_FSL_LAW		1	/* Use common FSL init code	*/

#undef	CONFIG_CAN_DRIVER		/* CAN Driver support		*/

/*
 * sysclk for MPC85xx
 *
 * Two valid values are:
 *    33333333
 *    66666666
 *
 * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
 * is likely the desired value here, so that is now the default.
 * The board, however, can run at 66MHz.  In any event, this value
 * must match the settings of some switches.  Details can be found
 * in the README.mpc85xxads.
 */

#ifndef CONFIG_SYS_CLK_FREQ
#define CONFIG_SYS_CLK_FREQ	33333333
#endif

/*
 * These can be toggled for performance analysis, otherwise use default.
 */
#define CONFIG_L2_CACHE			/* toggle L2 cache		*/
#define CONFIG_BTB			/* toggle branch predition	*/
#define CONFIG_ADDR_STREAMING		/* toggle addr streaming	*/

#define CFG_INIT_DBCR DBCR_IDM		/* Enable Debug Exceptions	*/

#undef	CFG_DRAM_TEST			/* memory test, takes time	*/
#define CFG_MEMTEST_START	0x00000000
#define CFG_MEMTEST_END		0x10000000

/*
 * Base addresses -- Note these are effective addresses where the
 * actual resources get mapped (not physical addresses)
 */
#define CFG_CCSRBAR_DEFAULT	0xFF700000	/* CCSRBAR Default	*/
#ifdef CONFIG_TQM_BIGFLASH
#define CFG_CCSRBAR	 	0xA0000000	/* relocated CCSRBAR	*/
#else /* !CONFIG_TQM_BIGFLASH */
#define CFG_CCSRBAR		0xE0000000	/* relocated CCSRBAR	*/
#endif /* CONFIG_TQM_BIGFLASH */
#define CFG_CCSRBAR_PHYS	CFG_CCSRBAR	/* physical addr of CCSRBAR */
#define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR	*/

#define CFG_PCI1_ADDR		(CFG_CCSRBAR + 0x8000)
#define CFG_PCI2_ADDR		(CFG_CCSRBAR + 0x9000)
#define CFG_PCIE1_ADDR		(CFG_CCSRBAR + 0xa000)

/*
 * DDR Setup
 */
#define CFG_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory	*/
#define CFG_SDRAM_BASE		CFG_DDR_SDRAM_BASE

#define CONFIG_NUM_DDR_CONTROLLERS	1
#define CONFIG_DIMM_SLOTS_PER_CTLR	1
#define CONFIG_CHIP_SELECTS_PER_CTRL	2

#if defined(CONFIG_TQM8540) || defined(CONFIG_TQM8560)
/* TQM8540 & 8560 need DLL-override */
#define CONFIG_DDR_DLL				/* DLL fix needed	*/
#define CONFIG_DDR_DEFAULT_CL	25		/* CAS latency 2,5	*/
#endif /* CONFIG_TQM8540 || CONFIG_TQM8560 */

#if defined(CONFIG_TQM8541) || defined(CONFIG_TQM8555) || \
    defined(CONFIG_TQM8548)
#define CONFIG_DDR_DEFAULT_CL	30		/* CAS latency 3	*/
#endif /* CONFIG_TQM8541 || CONFIG_TQM8555 || CONFIG_TQM8548 */

/*
 * Old TQM85xx boards have 'M' type Spansion Flashes from the S29GLxxxM
 * series while new boards have 'N' type Flashes from the S29GLxxxN
 * series, which have bigger sectors: 2 x 128 instead of 2 x 64 KB.
 */
#ifdef CONFIG_TQM8548
#define CONFIG_TQM_FLASH_N_TYPE
#endif /* CONFIG_TQM8548 */

/*
 * Flash on the Local Bus
 */
#ifdef CONFIG_TQM_BIGFLASH
#define CFG_FLASH0		0xE0000000
#define CFG_FLASH1		0xC0000000
#else /* !CONFIG_TQM_BIGFLASH */
#define CFG_FLASH0		0xFC000000
#define CFG_FLASH1		0xF8000000
#endif /* CONFIG_TQM_BIGFLASH */
#define CFG_FLASH_BANKS_LIST	{ CFG_FLASH1, CFG_FLASH0 }

#define CFG_LBC_FLASH_BASE	CFG_FLASH1	/* Localbus flash start	*/
#define CFG_FLASH_BASE		CFG_LBC_FLASH_BASE  /* start of FLASH	*/

/* Default ORx timings are for <= 41.7 MHz Local Bus Clock.
 *
 * Note: According to timing specifications external addr latch delay
 * (EAD, bit #0) must be set if Local Bus Clock is > 83 MHz.
 *
 * For other Local Bus Clocks see following table:
 *
 * Clock/MHz   CFG_ORx_PRELIM
 * 166         0x.....CA5
 * 133         0x.....C85
 * 100         0x.....C65
 *  83         0x.....FA2
 *  66         0x.....C82
 *  50         0x.....C60
 *  42         0x.....040
 *  33         0x.....030
 *  25         0x.....020
 *
 */
#ifdef CONFIG_TQM_BIGFLASH
#define CFG_BR0_PRELIM		0xE0001801	/* port size 32bit	*/
#define CFG_OR0_PRELIM		0xE0000040	/* 512MB Flash		*/
#define CFG_BR1_PRELIM		0xC0001801	/* port size 32bit	*/
#define CFG_OR1_PRELIM		0xE0000040	/* 512MB Flash		*/
#else /* !CONFIG_TQM_BIGFLASH */
#define CFG_BR0_PRELIM		0xfc001801	/* port size 32bit	*/
#define CFG_OR0_PRELIM		0xfc000040	/* 64MB Flash		*/
#define CFG_BR1_PRELIM		0xf8001801	/* port size 32bit	*/
#define CFG_OR1_PRELIM		0xfc000040	/* 64MB Flash		*/
#endif /* CONFIG_TQM_BIGFLASH */

#define CFG_FLASH_CFI			/* flash is CFI compat.		*/
#define CONFIG_FLASH_CFI_DRIVER		/* Use common CFI driver	*/
#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector	*/
#define CFG_FLASH_QUIET_TEST	1	/* don't warn upon unknown flash*/
#define CFG_FLASH_USE_BUFFER_WRITE	1 /* speed up output to Flash	*/

#define CFG_MAX_FLASH_BANKS	2	/* number of banks		*/
#define CFG_MAX_FLASH_SECT	512	/* sectors per device		*/
#undef	CFG_FLASH_CHECKSUM
#define CFG_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms)	*/
#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms)	*/

#define CFG_MONITOR_BASE	TEXT_BASE	/* start of monitor	*/

/*
 * Note: when changing the Local Bus clock divider you have to
 * change the timing values in CFG_ORx_PRELIM.
 *
 * LCRR[00:03] CLKDIV: System (CCB) clock divider. Valid values are 2, 4, 8.
 * LCRR[16:17] EADC  : External address delay cycles. It should be set to 2
 *                     for Local Bus Clock > 83.3 MHz.
 */
#define CFG_LBC_LCRR		0x00030008	/* LB clock ratio reg	*/
#define CFG_LBC_LBCR		0x00000000	/* LB config reg	*/
#define CFG_LBC_LSRT		0x20000000	/* LB sdram refresh timer */
#define CFG_LBC_MRTPR		0x20000000	/* LB refresh timer presc.*/

#define CONFIG_L1_INIT_RAM
#define CFG_INIT_RAM_LOCK	1
#define CFG_INIT_RAM_ADDR	(CFG_CCSRBAR \
				 + 0x04010000)	/* Initial RAM address	*/
#define CFG_INIT_RAM_END	0x4000		/* End used area in RAM	*/

#define CFG_GBL_DATA_SIZE	128	/* num bytes initial data	*/
#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET

#define CFG_MONITOR_LEN		(~TEXT_BASE + 1)/* Reserved for Monitor	*/
#define CFG_MALLOC_LEN		(384 * 1024)	/* Reserved for malloc	*/

/* Serial Port */
#if defined(CONFIG_TQM8560)

#define CONFIG_CONS_ON_SCC	/* define if console on SCC		*/
#undef	CONFIG_CONS_NONE	/* define if console on something else	*/
#define CONFIG_CONS_INDEX	1 /* which serial channel for console	*/

#else /* !CONFIG_TQM8560 */

#define CONFIG_CONS_INDEX     1
#undef	CONFIG_SERIAL_SOFTWARE_FIFO
#define CFG_NS16550
#define CFG_NS16550_SERIAL
#define CFG_NS16550_REG_SIZE	1
#define CFG_NS16550_CLK		get_bus_freq(0)

#define CFG_NS16550_COM1	(CFG_CCSRBAR+0x4500)
#define CFG_NS16550_COM2	(CFG_CCSRBAR+0x4600)

/* PS/2 Keyboard */
#define CONFIG_PS2KBD			/* AT-PS/2 Keyboard		*/
#define CONFIG_PS2MULT			/* .. on PS/2 Multiplexer	*/
#define CONFIG_PS2SERIAL	2	/* .. on DUART2			*/
#define CONFIG_PS2MULT_DELAY	(CFG_HZ/2)	/* Initial delay	*/
#define CONFIG_BOARD_EARLY_INIT_R	1

#endif /* CONFIG_TQM8560 */

#define CONFIG_BAUDRATE		115200

#define CFG_BAUDRATE_TABLE	\
	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}

#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
#define CFG_HUSH_PARSER		1	/* Use the HUSH parser		*/
#ifdef	CFG_HUSH_PARSER
#define	CFG_PROMPT_HUSH_PS2	"> "
#endif

/* pass open firmware flat tree */
#define CONFIG_OF_LIBFDT		1
#define CONFIG_OF_BOARD_SETUP		1
#define CONFIG_OF_STDOUT_VIA_ALIAS	1

/* CAN */
#define CFG_CAN_BASE		(CFG_CCSRBAR \
				 + 0x03000000)	/* CAN base address     */
#ifdef CONFIG_CAN_DRIVER
#define CFG_CAN_OR_AM		0xFFFF8000	/* 32 KiB address mask  */
#define CFG_OR2_CAN		(CFG_CAN_OR_AM | OR_UPM_BI)
#define CFG_BR2_CAN		((CFG_CAN_BASE & BR_BA) | \
				 BR_PS_8 | BR_MS_UPMC | BR_V)
#endif /* CONFIG_CAN_DRIVER */

/*
 * I2C
 */
#define CONFIG_FSL_I2C			/* Use FSL common I2C driver	*/
#define CONFIG_HARD_I2C			/* I2C with hardware support	*/
#undef	CONFIG_SOFT_I2C			/* I2C bit-banged		*/
#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
#define CFG_I2C_SLAVE		0x7F
#define CFG_I2C_NOPROBES	{0x48}	/* Don't probe these addrs	*/
#define CFG_I2C_OFFSET		0x3000

/* I2C RTC */
#define CONFIG_RTC_DS1337		/* Use ds1337 rtc via i2c	*/
#define CFG_I2C_RTC_ADDR	0x68	/* at address 0x68		*/

/* I2C EEPROM */
/*
 * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work also).
 */
#define CFG_I2C_EEPROM_ADDR		0x50	/* 1010000x		*/
#define CFG_I2C_EEPROM_ADDR_LEN		2
#define CFG_EEPROM_PAGE_WRITE_BITS	5	/* =32 Bytes per write	*/
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	20
#define CFG_I2C_MULTI_EEPROMS		1	/* more than one eeprom	*/

/* I2C SYSMON (LM75) */
#define CONFIG_DTT_LM75		1		/* ON Semi's LM75	*/
#define CONFIG_DTT_SENSORS	{0}		/* Sensor addresses	*/
#define CFG_DTT_MAX_TEMP	70
#define CFG_DTT_LOW_TEMP	-30
#define CFG_DTT_HYSTERESIS	3

#ifndef CONFIG_PCIE1
/* RapidIO MMU */
#ifdef CONFIG_TQM_BIGFLASH
#define CFG_RIO_MEM_BASE	0xb0000000	/* base address		*/
#define CFG_RIO_MEM_SIZE	0x10000000	/* 256M			*/
#else /* !CONFIG_TQM_BIGFLASH */
#define CFG_RIO_MEM_BASE	0xc0000000	/* base address		*/
#define CFG_RIO_MEM_SIZE	0x20000000	/* 512M			*/
#endif /* CONFIG_TQM_BIGFLASH */
#define CFG_RIO_MEM_PHYS	CFG_RIO_MEM_BASE
#endif /* CONFIG_PCIE1 */

/* NAND FLASH */
#ifdef CONFIG_NAND

#undef CONFIG_NAND_LEGACY

#define CONFIG_NAND_FSL_UPM	1

#define	CONFIG_MTD_NAND_ECC_JFFS2	1	/* use JFFS2 ECC	*/

/* address distance between chip selects */
#define	CFG_NAND_SELECT_DEVICE	1
#define	CFG_NAND_CS_DIST	0x200

#define CFG_NAND_SIZE		0x8000
#define CFG_NAND0_BASE		(CFG_CCSRBAR + 0x03010000)
#define CFG_NAND1_BASE		(CFG_NAND0_BASE + CFG_NAND_CS_DIST)
#define CFG_NAND2_BASE		(CFG_NAND1_BASE + CFG_NAND_CS_DIST)