lwmon5.h

来自「最新版的u-boot,2008-10-18发布」· C头文件代码 · 共 622 行 · 第 1/2 页
622 行
	"update=protect off FFF80000 FFFFFFFF;era FFF80000 FFFFFFFF;"	\		"cp.b 200000 FFF80000 80000\0"			        \	"upd=run load update\0"						\	"lwe_env=tftp 200000 /tftpboot.dev/lwmon5/env_uboot.bin;"	\		"autoscr 200000\0"					\	""#define CONFIG_BOOTCOMMAND	"run flash_self"#if 0#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/#else#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/#endif#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/#define	CONFIG_IBM_EMAC4_V4	1#define CONFIG_MII		1	/* MII PHY management		*/#define CONFIG_PHY_ADDR		3	/* PHY address, See schematics	*/#define CONFIG_PHY_RESET        1	/* reset phy upon startup         */#define CONFIG_PHY_RESET_DELAY	300#define CONFIG_HAS_ETH0#define CFG_RX_ETH_BUFFER	32	/* Number of ethernet rx buffers & descriptors */#define CONFIG_NET_MULTI	1#define CONFIG_HAS_ETH1		1	/* add support for "eth1addr"	*/#define CONFIG_PHY1_ADDR	1/* Video console */#define CONFIG_VIDEO#define CONFIG_VIDEO_MB862xx#define CONFIG_CFB_CONSOLE#define CONFIG_VIDEO_LOGO#define CONFIG_CONSOLE_EXTRA_INFO#define VIDEO_FB_16BPP_PIXEL_SWAP#define CONFIG_VGA_AS_SINGLE_DEVICE#define CONFIG_VIDEO_SW_CURSOR#define CONFIG_SPLASH_SCREEN/* USB */#ifdef CONFIG_440EPX#define CONFIG_USB_OHCI#define CONFIG_USB_STORAGE/* Comment this out to enable USB 1.1 device */#define USB_2_0_DEVICE#endif /* CONFIG_440EPX *//* Partitions */#define CONFIG_MAC_PARTITION#define CONFIG_DOS_PARTITION#define CONFIG_ISO_PARTITION/* * BOOTP options */#define CONFIG_BOOTP_BOOTFILESIZE#define CONFIG_BOOTP_BOOTPATH#define CONFIG_BOOTP_GATEWAY#define CONFIG_BOOTP_HOSTNAME/* * Command line configuration. */#include <config_cmd_default.h>#define CONFIG_CMD_ASKENV#define CONFIG_CMD_DATE#define CONFIG_CMD_DHCP#define CONFIG_CMD_DIAG#define CONFIG_CMD_EEPROM#define CONFIG_CMD_ELF#define CONFIG_CMD_FAT#define CONFIG_CMD_I2C#define CONFIG_CMD_IRQ#define CONFIG_CMD_LOG#define CONFIG_CMD_MII#define CONFIG_CMD_NET#define CONFIG_CMD_NFS#define CONFIG_CMD_PCI#define CONFIG_CMD_PING#define CONFIG_CMD_REGINFO#define CONFIG_CMD_SDRAM#ifdef CONFIG_VIDEO#define CONFIG_CMD_BMP#endif#ifdef CONFIG_440EPX#define CONFIG_CMD_USB#endif/*----------------------------------------------------------------------- * Miscellaneous configurable options *----------------------------------------------------------------------*/#define CONFIG_SUPPORT_VFAT#define CFG_LONGHELP			/* undef to save memory		*/#define CFG_PROMPT	        "=> "	/* Monitor Command Prompt	*/#define CFG_HUSH_PARSER		1	/* Use the HUSH parser		*/#ifdef	CFG_HUSH_PARSER#define	CFG_PROMPT_HUSH_PS2	"> "#endif#if defined(CONFIG_CMD_KGDB)#define CFG_CBSIZE	        1024	/* Console I/O Buffer Size	*/#else#define CFG_CBSIZE	        256	/* Console I/O Buffer Size	*/#endif#define CFG_PBSIZE              (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */#define CFG_MAXARGS	        16	/* max number of command args	*/#define CFG_BARGSIZE	        CFG_CBSIZE /* Boot Argument Buffer Size	*/#define CFG_MEMTEST_START	0x0400000 /* memtest works on		*/#define CFG_MEMTEST_END		0x0C00000 /* 4 ... 12 MB in DRAM	*/#define CFG_LOAD_ADDR		0x100000  /* default load address	*/#define CFG_EXTBDINFO		1	/* To use extended board_into (bd_t) */#define CFG_HZ		        1000	/* decrementer freq: 1 ms ticks	*/#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/#define CONFIG_LOOPW            1       /* enable loopw command         */#define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */#define CONFIG_VERSION_VARIABLE 1	/* include version env variable *//*----------------------------------------------------------------------- * PCI stuff *----------------------------------------------------------------------*//* General PCI */#define CONFIG_PCI			/* include pci support	        */#undef CONFIG_PCI_PNP			/* do (not) pci plug-and-play   */#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup  */#define CFG_PCI_TARGBASE        0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*//* Board-specific PCI */#define CFG_PCI_TARGET_INIT#define CFG_PCI_MASTER_INIT#define CFG_PCI_SUBSYS_VENDORID 0x10e8	/* AMCC				*/#define CFG_PCI_SUBSYS_ID       0xcafe	/* Whatever			*/#define CONFIG_HW_WATCHDOG	1	/* Use external HW-Watchdog	*/#define CONFIG_WD_PERIOD	40000	/* in usec */#define CONFIG_WD_MAX_RATE	66600	/* in ticks *//* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux *//*----------------------------------------------------------------------- * External Bus Controller (EBC) Setup *----------------------------------------------------------------------*/#define CFG_FLASH		CFG_FLASH_BASE/* Memory Bank 0 (NOR-FLASH) initialization					*/#define CFG_EBC_PB0AP		0x03050200#define CFG_EBC_PB0CR		(CFG_FLASH | 0xfc000)/* Memory Bank 1 (Lime) initialization						*/#define CFG_EBC_PB1AP		0x01004380#define CFG_EBC_PB1CR		(CFG_LIME_BASE_0 | 0xdc000)/* Memory Bank 2 (FPGA) initialization						*/#define CFG_EBC_PB2AP		0x01004400#define CFG_EBC_PB2CR		(CFG_FPGA_BASE_0 | 0x1c000)/* Memory Bank 3 (FPGA2) initialization						*/#define CFG_EBC_PB3AP		0x01004400#define CFG_EBC_PB3CR		(CFG_FPGA_BASE_1 | 0x1c000)#define CFG_EBC_CFG		0xb8400000/*----------------------------------------------------------------------- * Graphics (Fujitsu Lime) *----------------------------------------------------------------------*//* SDRAM Clock frequency adjustment register */#define CFG_LIME_SDRAM_CLOCK	0xC1FC0038/* Lime Clock frequency is to set 100MHz */#define CFG_LIME_CLOCK_100MHZ	0x00000#if 0/* Lime Clock frequency for 133MHz */#define CFG_LIME_CLOCK_133MHZ	0x10000#endif/* SDRAM Parameter register */#define CFG_LIME_MMR		0xC1FCFFFC/* SDRAM parameter value; was 0x414FB7F2, caused several vertical bars   and pixel flare on display when 133MHz was configured. According to   SDRAM chip datasheet CAS Latency is 3 for 133MHz and -75 Speed Grade */#ifdef CFG_LIME_CLOCK_133MHZ#define CFG_LIME_MMR_VALUE	0x414FB7F3#else#define CFG_LIME_MMR_VALUE	0x414FB7F2#endif/*----------------------------------------------------------------------- * GPIO Setup *----------------------------------------------------------------------*/#define CFG_GPIO_PHY1_RST	12#define CFG_GPIO_FLASH_WP	14#define CFG_GPIO_PHY0_RST	22#define CFG_GPIO_DSPIC_READY	51#define CFG_GPIO_EEPROM_EXT_WP	55#define CFG_GPIO_HIGHSIDE	56#define CFG_GPIO_EEPROM_INT_WP	57#define CFG_GPIO_BOARD_RESET	58#define CFG_GPIO_LIME_S		59#define CFG_GPIO_LIME_RST	60#define CFG_GPIO_SYSMON_STATUS	62#define CFG_GPIO_WATCHDOG	63/*----------------------------------------------------------------------- * PPC440 GPIO Configuration */#define CFG_4xx_GPIO_TABLE { /*	  Out		  GPIO	Alternate1	Alternate2	Alternate3 */ \{											\/* GPIO Core 0 */									\{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO0	EBC_ADDR(7)	DMA_REQ(2)	*/	\{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO1	EBC_ADDR(6)	DMA_ACK(2)	*/	\{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO2	EBC_ADDR(5)	DMA_EOT/TC(2)	*/	\{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO3	EBC_ADDR(4)	DMA_REQ(3)	*/	\{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO4	EBC_ADDR(3)	DMA_ACK(3)	*/	\{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO5	EBC_ADDR(2)	DMA_EOT/TC(3)	*/	\{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO6	EBC_CS_N(1)			*/	\{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO7	EBC_CS_N(2)			*/	\{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8	EBC_CS_N(3)			*/	\{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9	EBC_CS_N(4)			*/	\{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 EBC_CS_N(5)			*/	\{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO11 EBC_BUS_ERR			*/	\{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO12				*/	\{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO13				*/	\{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO14				*/	\{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO15				*/	\{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 GMCTxD(4)			*/	\{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 GMCTxD(5)			*/	\{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 GMCTxD(6)			*/	\{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO19 GMCTxD(7)			*/	\{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 RejectPkt0			*/	\{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 RejectPkt1			*/	\{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO22				*/	\{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 SCPD0				*/	\{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO24 GMCTxD(2)			*/	\{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO25 GMCTxD(3)			*/	\{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO26				*/	\{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO27 EXT_EBC_REQ	USB2D_RXERROR	*/	\{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO28		USB2D_TXVALID	*/	\{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO29 EBC_EXT_HDLA	USB2D_PAD_SUSPNDM */	\{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO30 EBC_EXT_ACK	USB2D_XCVRSELECT*/	\{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO31 EBC_EXR_BUSREQ	USB2D_TERMSELECT*/	\},											\{											\/* GPIO Core 1 */									\{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO32 USB2D_OPMODE0	EBC_DATA(2)	*/	\{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO33 USB2D_OPMODE1	EBC_DATA(3)	*/	\{GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_0}, /* GPIO34 UART0_DCD_N	UART1_DSR_CTS_N	UART2_SOUT*/ \{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N EBC_DATA(0)	UART3_SIN*/ \{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO37 UART0_RTS_N	EBC_DATA(1)	UART3_SOUT*/ \{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO38 UART0_DTR_N	UART1_SOUT	*/	\{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N	UART1_SIN	*/	\{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 UIC_IRQ(0)			*/	\{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 UIC_IRQ(1)			*/	\{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 UIC_IRQ(2)			*/	\{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 UIC_IRQ(3)			*/	\{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO44 UIC_IRQ(4)	DMA_ACK(1)	*/	\{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO45 UIC_IRQ(6)	DMA_EOT/TC(1)	*/	\{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO46 UIC_IRQ(7)	DMA_REQ(0)	*/	\{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 UIC_IRQ(8)	DMA_ACK(0)	*/	\{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 UIC_IRQ(9)	DMA_EOT/TC(0)	*/	\{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO49  Unselect via TraceSelect Bit	*/	\{GPIO1_BASE, GPIO_IN,  GPIO_SEL , GPIO_OUT_0}, /* GPIO50  Unselect via TraceSelect Bit	*/	\{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51  Unselect via TraceSelect Bit	*/	\{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52  Unselect via TraceSelect Bit	*/	\{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO53  Unselect via TraceSelect Bit	*/	\{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO54  Unselect via TraceSelect Bit	*/	\{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO55  Unselect via TraceSelect Bit	*/	\{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO56  Unselect via TraceSelect Bit	*/	\{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO57  Unselect via TraceSelect Bit	*/	\{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO58  Unselect via TraceSelect Bit	*/	\{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO59  Unselect via TraceSelect Bit	*/	\{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO60  Unselect via TraceSelect Bit	*/	\{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61  Unselect via TraceSelect Bit	*/	\{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62  Unselect via TraceSelect Bit	*/	\{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO63  Unselect via TraceSelect Bit	*/	\}											\}/* * Internal Definitions * * Boot Flags */#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/#define BOOTFLAG_WARM	0x02		/* Software reboot			*/#if defined(CONFIG_CMD_KGDB)#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */#define CONFIG_KGDB_SER_INDEX	2	    /* which serial port to use */#endif#endif	/* __CONFIG_H */
lwmon5.h - 源码说明

本页面展示了「最新版的u-boot,2008-10-18发布」中的 lwmon5.h 源码文件，采用 C头文件编程语言编写，共 622 行代码。您可以在线阅读完整代码内容，也可以返回资源详情页下载完整源码包进行本地学习和开发。
虫虫下载站收录了大量与u-boot相关的技术资源，包括源代码、技术文档、电路图等，是电子工程师和嵌入式开发者的专业学习平台。
⌨️ 快捷键说明

复制代码Ctrl + C
搜索代码Ctrl + F
全屏模式F11
增大字号Ctrl + =
减小字号Ctrl + -
显示快捷键?