mpc8572ds.h
来自「最新版的u-boot,2008-10-18发布」· C头文件 代码 · 共 592 行 · 第 1/2 页
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592 行
#define CONFIG_I2C_MULTI_BUS#define CONFIG_I2C_CMD_TREE#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */#define CFG_I2C_EEPROM_ADDR 0x57#define CFG_I2C_SLAVE 0x7F#define CFG_I2C_NOPROBES {{0,0x29}}/* Don't probe these addrs */#define CFG_I2C_OFFSET 0x3000#define CFG_I2C2_OFFSET 0x3100/* * I2C2 EEPROM */#define CONFIG_ID_EEPROM#ifdef CONFIG_ID_EEPROM#define CFG_I2C_EEPROM_NXID#endif#define CFG_I2C_EEPROM_ADDR 0x57#define CFG_I2C_EEPROM_ADDR_LEN 1#define CFG_EEPROM_BUS_NUM 1/* * General PCI * Memory space is mapped 1-1, but I/O space must start from 0. *//* PCI view of System Memory */#define CFG_PCI_MEMORY_BUS 0x00000000#define CFG_PCI_MEMORY_PHYS 0x00000000#define CFG_PCI_MEMORY_SIZE 0x80000000/* controller 3, direct to uli, tgtid 3, Base address 8000 */#define CFG_PCIE3_MEM_BASE 0x80000000#define CFG_PCIE3_MEM_PHYS CFG_PCIE3_MEM_BASE#define CFG_PCIE3_MEM_SIZE 0x20000000 /* 512M */#define CFG_PCIE3_IO_BASE 0x00000000#define CFG_PCIE3_IO_PHYS 0xffc00000#define CFG_PCIE3_IO_SIZE 0x00010000 /* 64k *//* controller 2, Slot 2, tgtid 2, Base address 9000 */#define CFG_PCIE2_MEM_BASE 0xa0000000#define CFG_PCIE2_MEM_PHYS CFG_PCIE2_MEM_BASE#define CFG_PCIE2_MEM_SIZE 0x20000000 /* 512M */#define CFG_PCIE2_IO_BASE 0x00000000#define CFG_PCIE2_IO_PHYS 0xffc10000#define CFG_PCIE2_IO_SIZE 0x00010000 /* 64k *//* controller 1, Slot 1, tgtid 1, Base address a000 */#define CFG_PCIE1_MEM_BASE 0xc0000000#define CFG_PCIE1_MEM_PHYS CFG_PCIE1_MEM_BASE#define CFG_PCIE1_MEM_SIZE 0x20000000 /* 512M */#define CFG_PCIE1_IO_BASE 0x00000000#define CFG_PCIE1_IO_PHYS 0xffc20000#define CFG_PCIE1_IO_SIZE 0x00010000 /* 64k */#if defined(CONFIG_PCI)/*PCIE video card used*/#define VIDEO_IO_OFFSET CFG_PCIE1_IO_PHYS/* video */#define CONFIG_VIDEO#if defined(CONFIG_VIDEO)#define CONFIG_BIOSEMU#define CONFIG_CFB_CONSOLE#define CONFIG_VIDEO_SW_CURSOR#define CONFIG_VGA_AS_SINGLE_DEVICE#define CONFIG_ATI_RADEON_FB#define CONFIG_VIDEO_LOGO/*#define CONFIG_CONSOLE_CURSOR*/#define CFG_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET#endif#define CONFIG_NET_MULTI#define CONFIG_PCI_PNP /* do pci plug-and-play */#undef CONFIG_EEPRO100#undef CONFIG_TULIP#undef CONFIG_RTL8139#ifdef CONFIG_RTL8139/* This macro is used by RTL8139 but not defined in PPC architecture */#define KSEG1ADDR(x) (x)#define _IO_BASE 0x00000000#endif#ifndef CONFIG_PCI_PNP #define PCI_ENET0_IOADDR CFG_PCIE3_IO_BASE #define PCI_ENET0_MEMADDR CFG_PCIE3_IO_BASE #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */#endif#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */#define CONFIG_DOS_PARTITION#define CONFIG_SCSI_AHCI#ifdef CONFIG_SCSI_AHCI#define CONFIG_SATA_ULI5288#define CFG_SCSI_MAX_SCSI_ID 4#define CFG_SCSI_MAX_LUN 1#define CFG_SCSI_MAX_DEVICE (CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN)#define CFG_SCSI_MAXDEVICE CFG_SCSI_MAX_DEVICE#endif /* SCSI */#endif /* CONFIG_PCI */#if defined(CONFIG_TSEC_ENET)#ifndef CONFIG_NET_MULTI#define CONFIG_NET_MULTI 1#endif#define CONFIG_MII 1 /* MII PHY management */#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */#define CONFIG_TSEC1 1#define CONFIG_TSEC1_NAME "eTSEC1"#define CONFIG_TSEC2 1#define CONFIG_TSEC2_NAME "eTSEC2"#define CONFIG_TSEC3 1#define CONFIG_TSEC3_NAME "eTSEC3"#define CONFIG_TSEC4 1#define CONFIG_TSEC4_NAME "eTSEC4"#define TSEC1_PHY_ADDR 0#define TSEC2_PHY_ADDR 1#define TSEC3_PHY_ADDR 2#define TSEC4_PHY_ADDR 3#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)#define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)#define TSEC1_PHYIDX 0#define TSEC2_PHYIDX 0#define TSEC3_PHYIDX 0#define TSEC4_PHYIDX 0#define CONFIG_ETHPRIME "eTSEC1"#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */#endif /* CONFIG_TSEC_ENET *//* * Environment */#define CONFIG_ENV_IS_IN_FLASH 1#if CFG_MONITOR_BASE > 0xfff80000#define CONFIG_ENV_ADDR 0xfff80000#else#define CONFIG_ENV_ADDR (CFG_MONITOR_BASE + 0x70000)#endif#define CONFIG_ENV_SIZE 0x2000#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change *//* * Command line configuration. */#include <config_cmd_default.h>#define CONFIG_CMD_IRQ#define CONFIG_CMD_PING#define CONFIG_CMD_I2C#define CONFIG_CMD_MII#define CONFIG_CMD_ELF#if defined(CONFIG_PCI)#define CONFIG_CMD_PCI#define CONFIG_CMD_BEDBUG#define CONFIG_CMD_NET#define CONFIG_CMD_SCSI#define CONFIG_CMD_EXT2#endif#undef CONFIG_WATCHDOG /* watchdog disabled *//* * Miscellaneous configurable options */#define CFG_LONGHELP /* undef to save memory */#define CONFIG_CMDLINE_EDITING /* Command-line editing */#define CFG_LOAD_ADDR 0x2000000 /* default load address */#define CFG_PROMPT "=> " /* Monitor Command Prompt */#if defined(CONFIG_CMD_KGDB)#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */#else#define CFG_CBSIZE 256 /* Console I/O Buffer Size */#endif#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */#define CFG_MAXARGS 16 /* max number of command args */#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */#define CFG_HZ 1000 /* decrementer freq: 1ms ticks *//* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*//* * Internal Definitions * * Boot Flags */#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */#define BOOTFLAG_WARM 0x02 /* Software reboot */#if defined(CONFIG_CMD_KGDB)#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */#endif/* * Environment Configuration *//* The mac addresses for all ethernet interface */#if defined(CONFIG_TSEC_ENET)#define CONFIG_HAS_ETH0#define CONFIG_ETHADDR 00:E0:0C:02:00:FD#define CONFIG_HAS_ETH1#define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD#define CONFIG_HAS_ETH2#define CONFIG_ETH2ADDR 00:E0:0C:02:02:FD#define CONFIG_HAS_ETH3#define CONFIG_ETH3ADDR 00:E0:0C:02:03:FD#endif#define CONFIG_IPADDR 192.168.1.254#define CONFIG_HOSTNAME unknown#define CONFIG_ROOTPATH /opt/nfsroot#define CONFIG_BOOTFILE uImage#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */#define CONFIG_SERVERIP 192.168.1.1#define CONFIG_GATEWAYIP 192.168.1.1#define CONFIG_NETMASK 255.255.255.0/* default location for tftp and bootm */#define CONFIG_LOADADDR 1000000#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */#undef CONFIG_BOOTARGS /* the boot command will set bootargs */#define CONFIG_BAUDRATE 115200#define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ "tftpflash=tftpboot $loadaddr $uboot; " \ "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ "erase " MK_STR(TEXT_BASE) " +$filesize; " \ "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ "consoledev=ttyS0\0" \ "ramdiskaddr=2000000\0" \ "ramdiskfile=8572ds/ramdisk.uboot\0" \ "fdtaddr=c00000\0" \ "fdtfile=8572ds/mpc8572ds.dtb\0" \ "bdev=sda3\0"#define CONFIG_HDBOOT \ "setenv bootargs root=/dev/$bdev rw " \ "console=$consoledev,$baudrate $othbootargs;" \ "tftp $loadaddr $bootfile;" \ "tftp $fdtaddr $fdtfile;" \ "bootm $loadaddr - $fdtaddr"#define CONFIG_NFSBOOTCOMMAND \ "setenv bootargs root=/dev/nfs rw " \ "nfsroot=$serverip:$rootpath " \ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ "console=$consoledev,$baudrate $othbootargs;" \ "tftp $loadaddr $bootfile;" \ "tftp $fdtaddr $fdtfile;" \ "bootm $loadaddr - $fdtaddr"#define CONFIG_RAMBOOTCOMMAND \ "setenv bootargs root=/dev/ram rw " \ "console=$consoledev,$baudrate $othbootargs;" \ "tftp $ramdiskaddr $ramdiskfile;" \ "tftp $loadaddr $bootfile;" \ "tftp $fdtaddr $fdtfile;" \ "bootm $loadaddr $ramdiskaddr $fdtaddr"#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT#endif /* __CONFIG_H */
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