platform.s

HAL硬件抽象层源码

;/*****************************************************************************
; * Copyright (C) ARM Limited 1998. All rights reserved. 
; *****************************************************************************/
;/************************************************************************
;
;  PID address map
;
;	NOTE: This is a multi-hosted header file for use with uHAL and
;	      supported debuggers.
;
;************************************************************************/

 IF :LNOT: :DEF: __address_h
__address_h			EQU		1

PLATFORM_ID			EQU		0x39437092
SYSTEM_CLOCK		EQU		50000000

; Common modules for uHAL can be included or excluded by changing these
; definitions. These can be over-ridden by the makefile/ARM project file
; provided the .h file can is rebuilt.
 IF :LNOT: :DEF: uHAL_BOOT
uHAL_BOOT			EQU		1
 ENDIF
 IF :LNOT: :DEF: uHAL_TIMERS
uHAL_TIMERS			EQU		1
 ENDIF
 IF :LNOT: :DEF: uHAL_INTERRUPTS
uHAL_INTERRUPTS		EQU		1
 ENDIF
 IF :LNOT: :DEF: uHAL_COMPLEX_IRQ
uHAL_COMPLEX_IRQ	EQU		1
 ENDIF
 IF :LNOT: :DEF: uHAL_PCI
uHAL_PCI			EQU		0
 ENDIF
 IF :LNOT: :DEF: uHAL_HEAP
uHAL_HEAP			EQU		1
uHAL_HEAP_BASE		EQU		0x00042000
uHAL_HEAP_SIZE		EQU		(SZ_16K+SZ_32K)
uHAL_STACK_BASE		EQU		0x00048000
uHAL_STACK_SIZE		EQU		SZ_32K
 ENDIF

; /* memory size */
uHAL_MEMORY_SIZE	EQU		(SZ_256K+SZ_64K)

; /* The Interrupt Controller */
ICBase			EQU	0x09001200

; /* IRQ/FIQ stuff */
IC_GMR				EQU		0x0000000
IC_TMR				EQU		0x0000004
IC_TPR				EQU		0x0000008
IC_IDR				EQU		0x000000C
IC_FSR				EQU		0x0000010
IC_ISR				EQU		0x0000014
IC_FMR				EQU		0x0000018
IC_IMR				EQU		0x000001C
IC_ISCR				EQU		0x0000020

MAXIRQNUM			EQU		20
MAXFIQNUM			EQU		20
MAXSWINUM			EQU		20

NR_IRQS				EQU		(MAXIRQNUM + 1)

RAM_BASE			EQU		0x00040000
RAM_SIZE			EQU		0x00010000
FLASH_BASE			EQU		0x08000000
FLASH_SIZE			EQU		0x00030000
CLEAN_BASE			EQU		FLASH_BASE
CLEAN_SIZE			EQU		FLASH_SIZE
EXTERNAL_IO_BASE	EQU		0x01000000
EXTERNAL_IO_SIZE	EQU		0x01000000
IO_BASE				EQU		0x09000000
IO_SIZE				EQU		0x01000000
	
; Number of Level2 table entries in uHAL_AddressTable
L2_TABLE_ENTRIES	EQU		0

; /* UART */
; /* define it so that it only ever uses one port */
HOST_COMPORT		EQU		UART_IO_BASE 
SEMIHOSTED_COMPORT	EQU		HOST_COMPORT
OS_COMPORT			EQU		HOST_COMPORT

; /* Values to set given baud rates */
DEFAULT_HOST_BAUD	EQU		ARM_BAUD_9600
DEFAULT_OS_BAUD		EQU		ARM_BAUD_115200

; /* This board uses the st16c552 UART as stdio */
UART_IO_BASE		EQU		(IO_BASE + 0x00001400)

;/* HMS39C7092 specific stuff */
;/*
; * Clock Divisors for various Baud rates (assuming that
; * the 7092EVMPID is using a 50 MHz clock for the UART)
; */
ARM_BAUD_PRESCALE	EQU		2

ARM_BAUD_1200		EQU		(SYSTEM_CLOCK/16/ARM_BAUD_PRESCALE/  1200)
ARM_BAUD_2400		EQU		(SYSTEM_CLOCK/16/ARM_BAUD_PRESCALE/  2400)
ARM_BAUD_4800		EQU		(SYSTEM_CLOCK/16/ARM_BAUD_PRESCALE/  4800)
ARM_BAUD_9600		EQU		(SYSTEM_CLOCK/16/ARM_BAUD_PRESCALE/  9600)
ARM_BAUD_19200		EQU		(SYSTEM_CLOCK/16/ARM_BAUD_PRESCALE/ 19200)
ARM_BAUD_38400		EQU		(SYSTEM_CLOCK/16/ARM_BAUD_PRESCALE/ 38400)
ARM_BAUD_57600		EQU		(SYSTEM_CLOCK/16/ARM_BAUD_PRESCALE/ 57600)
ARM_BAUD_115200		EQU		(SYSTEM_CLOCK/16/ARM_BAUD_PRESCALE/115200)

;/*
; * Register offsets
; */
UART_RHRTHR			EQU		0x00
UART_IER			EQU		0x04
UART_ISRFCR			EQU		0x08
UART_LCR			EQU		0x0C
UART_MCR			EQU		0x10
UART_LSR			EQU		0x14
UART_MSR			EQU		0x18
UART_SPR			EQU		0x1C
UART_CLKCR			EQU		0x20
UART_CLKDR			EQU		0x24
	
;/*
; * Line Status Register bits
; */
LSRRxData     		EQU		(1 << 0)
LSROverrun      	EQU		(1 << 1)
LSRParity       	EQU		(1 << 2)
LSRFraming      	EQU		(1 << 3)
LSRBreak        	EQU		(1 << 4)
LSRTxHoldEmpty  	EQU		(1 << 5)
LSRTxEmpty      	EQU		(1 << 6)
LSRFIFOError    	EQU		(1 << 7)

	
; /* LEDs */
uHAL_NUM_OF_LEDS	EQU		1
ALL_LEDS			EQU		1
;#define uHAL_LED_MASKS	{ 0 }
;#define uHAL_LED_OFFSETS	{ 0 }
 IF :LNOT: :DEF: HIGH
HIGH				EQU		1
 ENDIF
uHAL_LED_ON			EQU		1
uHAL_LED_OFF		EQU		0

; /* Timer stuff */
TIMERBase			EQU		0x09001300
TIMER_TSTARTR		EQU		0x00000000
TIMER_TSYNCR		EQU		0x00000004
TIMER_TCR0			EQU		0x00000020
TIMER_TIOCR0		EQU		0x00000024
TIMER_TIER0			EQU		0x00000028
TIMER_TSR0			EQU		0x0000002C
TIMER_TCNT0			EQU		0x00000030
TIMER_GRA0			EQU		0x00000034
TIMER_GRB0			EQU		0x00000038
	
OS_TIMER			EQU		1
MAX_TIMER			EQU		6

; The irq numbers of the individual timers
;#define TIMER_VECTORS	{ 0, 4}
;16Mhz clock, /16 divider, = 1000
mSEC_1				EQU		1000
MAX_PERIOD			EQU		0xFFFF	

; /* Port stuff */
PADR				EQU		0x09001600
PADDR				EQU		0x09001604
PBDR				EQU		0x09001608
PBDDR				EQU		0x0900160C
P1DR				EQU		0x09001610
P1DDR				EQU		0x09001614
P2DR				EQU		0x09001618
P2DDR				EQU		0x0900161C
P3DR				EQU		0x09001620
P3DDR				EQU		0x09001624
P4DR				EQU		0x09001628
P4DDR				EQU		0x0900162C
P5DR				EQU		0x09001630
P5DDR				EQU		0x09001634
P6DR				EQU		0x09001638
P6DDR				EQU		0x0900163C
P7DR				EQU		0x09001640
P7DDR				EQU		0x09001644
P8DR				EQU		0x09001648
P8DDR				EQU		0x0900164C
P9DR				EQU		0x09001650
P9DDR				EQU		0x09001654


;/*PMU stuff */
PMUCR				EQU		0x09001000
PMUSR				EQU		0x09001000
PCLKCR				EQU		0x09001008
MEMSR				EQU		0x0900100C
MEMCR				EQU		0x09001010
RSTCR				EQU		0x09001030


 ENDIF

	END