platform.h.bak

HAL硬件抽象层源码

/*****************************************************************************
 * Copyright (C) ARM Limited 1998. All rights reserved. 
 * Copyright (C) Hynix Semiconductor Limited 2002. All rights reserved. 
 *****************************************************************************/
/************************************************************************
 * 
 *   HMS39C7092 EVM Board address map
 * 
 * 	NOTE: This is a multi-hosted header file for use with uHAL and
 * 	      supported debuggers.
 * 
 * ************************************************************************/
//
//	Hynix HMS39C7092 flatform
//
#ifndef __address_h
#define __address_h                     1

#define PLATFORM_ID			0x39437092
#define	SYSTEM_CLOCK		50000000

/*  Common modules for uHAL can be included or excluded by changing these
 *  definitions. These can be over-ridden by the makefile/ARM project file
 *  provided the .h file can is rebuilt.
 */
#ifndef uHAL_BOOT
#define uHAL_BOOT           1
#endif
#ifndef uHAL_TIMERS
#define uHAL_TIMERS         1
#endif
#ifndef uHAL_INTERRUPTS
#define uHAL_INTERRUPTS     1
#endif
#ifndef uHAL_COMPLEX_IRQ
#define uHAL_COMPLEX_IRQ    1
#endif
#ifndef uHAL_PCI
#define uHAL_PCI            0
#endif
#ifndef uHAL_HEAP
#define uHAL_HEAP           1
#define uHAL_HEAP_BASE      0x00042000
#define uHAL_HEAP_SIZE      (SZ_16K+SZ_32K)
#define uHAL_STACK_BASE     0x00048000
#define uHAL_STACK_SIZE     SZ_32K
#endif

/* memory size */
#define uHAL_MEMORY_SIZE	(SZ_256K+SZ_64)

/* The Interrupt Controller */
#define ICBase				0x09001200

/* IRQ/FIQ stuff */
#define IC_GMR				0x00000000
#define	IC_TMR				0x00000004	
#define	IC_TPR				0x00000008
#define	IC_IDR				0x0000000C
#define	IC_FSR				0x00000010
#define	IC_ISR				0x00000014
#define	IC_FMR				0x00000018
#define	IC_IMR				0x0000001C
#define	IC_ISCR				0x00000020

#define MAXIRQNUM			20
#define MAXFIQNUM			20
#define MAXSWINUM			20

#define NR_IRQS				(MAXIRQNUM + 1)

#define RAM_BASE			0x00040000
#define RAM_SIZE			SZ_64K
#define FLASH_BASE			0x08000000
#define FLASH_SIZE			0x00030000
#define CLEAN_BASE			FLASH_BASE
#define CLEAN_SIZE			FLASH_SIZE
#define	IO_BASE				0x09000000
	
/*  Number of Level2 table entries in uHAL_AddressTable
 */
#define L2_TABLE_ENTRIES    0

/* UART */
/* define it so that it only ever uses one port */
#define HOST_COMPORT		UART_IO_BASE 
#define SEMIHOSTED_COMPORT	HOST_COMPORT
#define OS_COMPORT			HOST_COMPORT

/* Values to set given baud rates */
#define DEFAULT_HOST_BAUD	ARM_BAUD_9600
#define DEFAULT_OS_BAUD		ARM_BAUD_115200

#define IO_MAPADDRESS(a)	(((unsigned int) a << 2) | IO_BASE)
#define _MapAddress(a)		IO_MAPADDRESS(a)
#define IO_READ(p)			(*(unsigned int *)(IO_MAPADDRESS(p)))
#define IO_WRITE(p, c)		(*(unsigned int *)(IO_MAPADDRESS(p)) = c)

/* This board uses the UART UART as stdio */
#define UART_IO_BASE		(IO_BASE + 0x00001400)

/* UART primitives */
#define GET_STATUS(p)		(*(volatile unsigned char *)((p) + UART_LSR))
#define RX_DATA(s)     		((s & LSRRxData) != 0)
#define GET_CHAR(p)			(*(volatile unsigned char *)((p) + UART_RHRTHR))
#define TX_READY(s)    		((s & LSRTxHoldEmpty) != 0)
#define PUT_CHAR(p,c)  		(*(volatile unsigned char *)((p) + UART_RHRTHR) = (c))
		
/* UART specific stuff */
/*
 *  * Clock Divisors for various Baud rates (assuming that
 *  * the PID is using a 33 MHz clock for the UART)
 *  */

#define ARM_BAUD_PRESCALE	2

#define ARM_BAUD_1200		(SYSTEM_CLOCK/16/ARM_BAUD_PRESCALE/  1200)
#define ARM_BAUD_2400		(SYSTEM_CLOCK/16/ARM_BAUD_PRESCALE/  2400)
#define ARM_BAUD_4800		(SYSTEM_CLOCK/16/ARM_BAUD_PRESCALE/  4800)
#define ARM_BAUD_9600		(SYSTEM_CLOCK/16/ARM_BAUD_PRESCALE/  9600)
#define ARM_BAUD_19200		(SYSTEM_CLOCK/16/ARM_BAUD_PRESCALE/ 19200)
#define ARM_BAUD_38400		(SYSTEM_CLOCK/16/ARM_BAUD_PRESCALE/ 38400)
#define ARM_BAUD_57600		(SYSTEM_CLOCK/16/ARM_BAUD_PRESCALE/ 57600)
#define ARM_BAUD_115200		(SYSTEM_CLOCK/16/ARM_BAUD_PRESCALE/115200)

/*
 *  * Register offsets
 *  */
#define UART_RHRTHR			0x00
#define UART_IER			0x04
#define UART_ISRFCR			0x08
#define UART_LCR			0x0C
#define UART_MCR			0x10
#define UART_LSR			0x14
#define UART_MSR			0x18
#define UART_SPR			0x1C
#define UART_CLKC			0x20
#define UART_CLKD			0x24
	
/*
 *  * Line Status Register bits
 *  */
#define LSRRxData			(1 << 0)
#define LSROverrun			(1 << 1)
#define LSRParity			(1 << 2)
#define LSRFraming			(1 << 3)
#define LSRBreak			(1 << 4)
#define LSRTxHoldEmpty		(1 << 5)
#define LSRTxEmpty			(1 << 6)
#define LSRFIFOError		(1 << 7)

	
/* LEDs */
#define uHAL_NUM_OF_LEDS	1
#define ALL_LEDS			1
#define uHAL_LED_MASKS	{ 0,0x20 }
#define uHAL_LED_OFFSETS	{ 0,(void*)P7DR }
#ifndef HIGH
#define HIGH				1
#endif
#define uHAL_LED_ON			1
#define uHAL_LED_OFF		0

/* Timer stuff */
#define	TIMERBase			0x09001300
#define	TIMER_TSTARTR		0x00000000
#define	TIMER_TSYNCR		0x00000004
#define	TIMER_TCR0			0x00000020
#define	TIMER_TIOCR0		0x00000024
#define	TIMER_TIER0			0x00000028
#define	TIMER_TSR0			0x0000002C
#define	TIMER_TCNT0			0x00000030
#define	TIMER_GRA0			0x00000034
#define	TIMER_GRB0			0x00000038
	
#define OS_TIMER 			1
#define MAX_TIMER			6

/*  The irq numbers of the individual timers
 */
#define TIMER_VECTORS	{1,14,15,16,17,18,19}
/* 16Mhz clock, /16 divider, = 1000
 */
#define mSEC_1				1000
#define MAX_PERIOD 			0xFFFF	

/* Port stuff */
#define	PADR				0x09001600
#define	PADDR				0x09001604
#define	PBDR				0x09001608
#define	PBDDR				0x0900160C
#define	P1DR				0x09001610
#define	P1DDR				0x09001614
#define	P2DR				0x09001618
#define	P2DDR				0x0900161C
#define	P3DR				0x09001620
#define	P3DDR				0x09001624
#define	P4DR				0x09001628
#define	P4DDR				0x0900162C
#define	P5DR				0x09001630
#define	P5DDR				0x09001634
#define	P6DR				0x09001638
#define	P6DDR				0x0900163C
#define	P7DR				0x09001640
#define	P7DDR				0x09001644
#define	P8DR				0x09001648
#define	P8DDR				0x0900164C
#define	P9DR				0x09001650
#define	P9DDR				0x09001654

/* PMU stuff */
#define	PMUCR				0x09001000
#define	PMUSR				0x09001000
#define	PCLKCR				0x09001008
#define	MEMSR				0x0900100C
#define	MEMCR				0x09001010
#define	RSTCR				0x09001030

#define	PAMR				0x09000000
#define	PBMR				0x09000004
#define	P1MR				0x09000008
#define	P2MR				0x0900000C
#define	P3MR				0x09000010
#define	P4MR				0x09000014
#define	P5MR				0x09000018
#define	P6MR				0x0900001C
#define	P7MR				0x09000020
#define	P8MR				0x09000024
#define	P9MR				0x09000028

#define	BCR0				0x09000100
#define	BCR1				0x09000104
#define	BCR2				0x09000108
#define	BCR3				0x0900010C
#define	BCR4				0x09000110
#define	BCR5				0x09000114
#define	BCR6				0x09000118
#define	BCR7				0x0900011C


#endif

/* 	END */