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主要用于时序分析,无论是ASIC还是FPGA以及DSP都很有效的.欢迎大家使用

CTune -- ClockTune (v0.9)

Jeng-Liang Tsai and Charlie Chung-Ping Chen

INTRODUCTION
    This beta version implements the BB+DME algorithm.  The program can either
    randomly generate sink nodes or read an input file, construct the clock
    tree topology, and output the result in a user specified postscript
    file.  The next version will allow users to nevigate the clock tree and
    tune the wire widths.
 
OS REQUIREMENT
    PC (Windows based) or SUN
 
DOWNLOAD
    http://www.cae.wisc.edu/~jltsai/CTune/CTune0.9.zip
        ( binary and inputs for Windows ) 
    http://www.cae.wisc.edu/~jltsai/CTune/CTune0.9.tar.gz
        ( binary and inputs for UNIX ) 

REFERENCE
	Ran-Song Tsay, "Exact Zero Skew," IEEE Int. Conference on Computer-Aided
	Design (ICCAD-91), pp. 336- 339, 1991. Nov. 1991.
	
    T.-H. Chao, Y.-C. Hsu, J.-M. Ho, K. D. Boese, and A. B. Kahng, "Zero 
    Skew Clock Routing with Minimum Wirelength," IEEE Trans. Circuits Syst.
    -II, pp. 799- 814, 1992.

TECHNIQUE SUPPORT
    If you have any technical problem, please email the author Jeng-Liang
    Tsai ([e-mail]) of this tool. Please also report any bug you
    find to the author. Thanks very much.