fa5_rdi.cnf

FIC8120 方案 Parser_ICE

HEAPBASE=0x00000000
ENDIANNESS=L
STACKBASE=0x00700000
{ TARGET_PROCESSORS
{ ARM_0
$ARM$
ENDIANNESS=L
RDIREG=COPROCESSOR
FA5_USE_SDM=YES
FA5_CTRL_DLG=FALSE
CONTROLLER_RDIVERSION=151
RESET_MODE=ENTER_ICE
{ CPU_A
{ ARM
}
}
PROCESSOR=FA5
}
}
STACKLIMIT=0x00700000
TARGET_DIR=T:\APD\Division\MPL\Service\FIC8120\CDROM_package_releasing\FIC8120 package 20060220\ICE\Parser_ICE
FA5_USE_SDM=YES
FA5_CTRL_DLG=FALSE
CONTROLLER_RDIVERSION=151
RESET_MODE=ENTER_ICE
PROCESSOR=FA5
HEAPLIMIT=0x00800000