📄 lib_host20.h
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///////////////////////////////////////////////////////////////////////////////
//
// File name: Lib_Host20.H
// Version: 1.0
// Date: 2005/01/31
//
// Author: Bruce
// Phone: (03) 578-7888
// Company: Faraday Tech. Corp.
//
// Description: 1.EHCI Data Structure
// 2.EHCI Register
// 3.Others
///////////////////////////////////////////////////////////////////////////////
#ifndef LIB_HOST20__H
//=================== 1.Condition Definition ============================================================
//========================================================================================================
#include "symbol.h"
//****************************
// Data Structure Allocation
//****************************
// 0x3000000~0x3001000 =>qHD
// 0x3001000~0x3002000 =>qTD
// 0x3002000~0x3003000 =>iTD
//
#define Host20_STRUCTURE_BASE_ADDRESS 0x3000000//(DRAM=48M)
#define Host20_STRUCTURE_qHD_BASE_ADDRESS Host20_STRUCTURE_BASE_ADDRESS//(DRAM=48M)
#define Host20_qHD_SIZE 0x40//(64bytes)
#define Host20_qHD_MAX 10//(10 )
#define Host20_STRUCTURE_qTD_BASE_ADDRESS (Host20_STRUCTURE_BASE_ADDRESS+0x1000)//(DRAM=48M)
#define Host20_qTD_SIZE 0x20//(32bytes)
#define Host20_qTD_MAX 50//(50 )
#define Host20_STRUCTURE_Preiodic_Frame_List_BASE_ADDRESS (Host20_STRUCTURE_BASE_ADDRESS+0x3000)//(DRAM=48M)
#define Host20_Preiodic_Frame_SIZE 0x04//(4bytes)
#define Host20_Preiodic_Frame_List_MAX 1024//(1024\)
#define Host20_STRUCTURE_iTD_BASE_ADDRESS (Host20_STRUCTURE_BASE_ADDRESS+0x10000)//(DRAM=48M)
#define Host20_iTD_SIZE 0x40//(64bytes)
#define Host20_iTD_MAX 1024//(10 )
#define Host20_DATA_PAGE_BASE_ADDRESS (Host20_STRUCTURE_BASE_ADDRESS+0x100000)//(DRAM=49M)
#define Host20_Page_SIZE 0x1000//(4Kbytes)
#define Host20_Page_MAX 1024//(10 )
#define Host20_MEM_TYPE_qTD 0x00
#define Host20_MEM_TYPE_iTD 0x01
#define Host20_MEM_TYPE_4K_BUFFER 0x02
#define Host20_MEM_TYPE_siTD 0x03
#define Host20_MEM_FREE 0x01
#define Host20_MEM_USED 0x02
#define OTGH_Dir_IN 0x01
#define OTGH_Dir_Out 0x00
#define OTGH_NULL 0x00
#define OTGH_ED_ISO 0x01
#define OTGH_ED_BULK 0x02
#define OTGH_ED_INT 0x03
#define OTGH_ED_Control 0x00
#define OTGH_FARADAY_TEST_AP 0x10237856
#define OTGH_SRP_HNP_Enable 0x03
#define OTGH_Remote_Wake_UP 0x00000400
#define OTGH_Remote_Wake_UP_INT 0x00000008
//=================== 2.Define Register Macro ================================================================
//========================================================================================================
//<1>.Macro volatile
#define mwHost20Port(bOffset) *((volatile UINT32 *) ( Host20_BASE_ADDRESS | bOffset))
#define mwHost20Bit_Rd(bByte,wBitNum) (mwHost20Port(bByte)&wBitNum)
#define mwHost20Bit_Set(bByte,wBitNum) (mwHost20Port(bByte)|=wBitNum)
#define mwHost20Bit_Clr(bByte,wBitNum) (mwHost20Port(bByte)&=~wBitNum)
//<2>.0x000(Capability Register)
#define mwHost20_HCIVersion_Rd() ((mwHost20Port(0x00)>>16)&0x0000FFFF)
#define mwHost20_CapLength_Rd() (mwHost20Port(0x00)&0x000000FF)
//<3>.0x004(HCSPARAMS - Structural Parameters)
#define mwHost20_NumPorts_Rd() ((mwHost20Port(0x04)&0x0000000F)
//<4>.0x008(HCCPARAMS - Capability Parameters)
#define mbHost20_ProgrammableFrameListFlag_Rd() (mwHost20Bit_Rd(0x08,BIT1)) //Bit 1
//<4>.0x010(USBCMD - USB Command Register)
#define mwHost20_USBCMD_IntThreshold_Rd() ((mwHost20Port(0x010)>>16)&0x0000FFFF) //Bit 16~23
#define mbHost20_USBCMD_IntThreshold_Set(bValue) (mwHost20Port(0x010)=((mwHost20Port(0x010)&0xFF00FFFF)|(((UINT32)(bValue))<<16)) //Bit 16~23
//----->Add "Asynchronous schedule Park mode ENable"
//----->Add "ASYNchronous schedule Park mode CouNT"
#define mbHost20_USBCMD_ParkMode_Rd() (mwHost20Bit_Rd(0x10,BIT11)>>11)
#define mbHost20_USBCMD_ParkMode_Set() (mwHost20Bit_Set(0x10,BIT11))
#define mbHost20_USBCMD_ParkMode_Clr() (mwHost20Bit_Clr(0x10,BIT11))
#define mbHost20_USBCMD_ParkMode_CNT_Rd() ((mwHost20Port(0x10)>>8)&0x00000003)
#define mbHost20_USBCMD_ParkMode_CNT_Set(bValue) (mwHost20Port(0x010)=(mwHost20Port(0x010)&0xFFFFFCFF)|(( (UINT32) bValue )<<8) ) //Bit 8~9
#define mbHost20_USBCMD_InterruptOnAsync_Rd() (mwHost20Bit_Rd(0x10,BIT6)) //Bit 6
#define mbHost20_USBCMD_InterruptOnAsync_Set() (mwHost20Bit_Set(0x10,BIT6)) //Bit 6
#define mbHost20_USBCMD_InterruptOnAsync_Clr() (mwHost20Bit_Clr(0x10,BIT6)) //Bit 6
#define mbHost20_USBCMD_AsynchronousEnable_Rd() (mwHost20Bit_Rd(0x10,BIT5)) //Bit 5
#define mbHost20_USBCMD_AsynchronousEnable_Set() (mwHost20Bit_Set(0x10,BIT5)) //Bit 5
#define mbHost20_USBCMD_AsynchronousEnable_Clr() (mwHost20Bit_Clr(0x10,BIT5)) //Bit 5
#define mbHost20_USBCMD_PeriodicEnable_Rd() (mwHost20Bit_Rd(0x10,BIT4) ) //Bit 4
#define mbHost20_USBCMD_PeriodicEnable_Set() (mwHost20Bit_Set(0x10,BIT4)) //Bit 4
#define mbHost20_USBCMD_PeriodicEnable_Clr() (mwHost20Bit_Clr(0x10,BIT4)) //Bit 4
#define mbHost20_USBCMD_FrameListSize_Rd() ((mwHost20Port(0x10)>>2)&0x00000003) //Bit 2~3
#define mbHost20_USBCMD_FrameListSize_Set(bValue) ((mwHost20Port(0x10)=((mwHost20Port(0x10)&0xFFFFFFF3)|(((UINT32)(bValue))<<2))) //Bit 2~3
#define HOST20_USBCMD_FrameListSize_1024 0x00
#define HOST20_USBCMD_FrameListSize_512 0x01
#define HOST20_USBCMD_FrameListSize_256 0x02
#define mbHost20_USBCMD_HCReset_Rd() (mwHost20Bit_Rd(0x10,BIT1)) //Bit 1
#define mbHost20_USBCMD_HCReset_Set() (mwHost20Bit_Set(0x10,BIT1)) //Bit 1
#define mbHost20_USBCMD_RunStop_Rd() (mwHost20Bit_Rd(0x10,BIT0) ) //Bit 0
#define mbHost20_USBCMD_RunStop_Set() (mwHost20Bit_Set(0x10,BIT0)) //Bit 0
#define mbHost20_USBCMD_RunStop_Clr() (mwHost20Bit_Clr(0x10,BIT0)) //Bit 0
#define HOST20_Enable 0x01
#define HOST20_Disable 0x00
//<5>.0x014(USBSTS - USB Status Register)
#define mwHost20_USBSTS_Rd() (mwHost20Port(0x14))
#define mwHost20_USBSTS_Set(wValue) (mwHost20Port(0x14)=wValue)
#define mwHost20_USBSTS_AsynchronousStatus_Rd() (mwHost20Bit_Rd(0x14,BIT15)) //Bit 15
#define mwHost20_USBSTS_PeriodicStatus_Rd() (mwHost20Bit_Rd(0x14,BIT14)) //Bit 14
#define mwHost20_USBSTS_Reclamation_Rd() (mwHost20Bit_Rd(0x14,BIT13)) //Bit 13
#define mwHost20_USBSTS_HCHalted_Rd() (mwHost20Bit_Rd(0x14,BIT12)) //Bit 12
#define mwHost20_USBSTS_IntOnAsyncAdvance_Rd() (mwHost20Bit_Rd(0x14,BIT5)) //Bit 5
#define mwHost20_USBSTS_IntOnAsyncAdvance_Set() (mwHost20Bit_Set(0x14,BIT5)) //Bit 5
#define mwHost20_USBSTS_SystemError_Rd() (mwHost20Bit_Rd(0x14,BIT4) ) //Bit 4
#define mwHost20_USBSTS_SystemError_Set() (mwHost20Bit_Set(0x14,BIT4)) //Bit 4
#define mwHost20_USBSTS_FrameRollover_Rd() (mwHost20Bit_Rd(0x14,BIT3)) //Bit 3
#define mwHost20_USBSTS_FrameRollover_Set() (mwHost20Bit_Set(0x14,BIT3)) //Bit 3
#define mwHost20_USBSTS_PortChangeDetect_Rd() (mwHost20Bit_Rd(0x14,BIT2)) //Bit 2
#define mwHost20_USBSTS_PortChangeDetect_Set() (mwHost20Bit_Set(0x14,BIT2)) //Bit 2
#define mwHost20_USBSTS_USBError_Rd() (mwHost20Bit_Rd(0x14,BIT1)) //Bit 1
#define mwHost20_USBSTS_USBError_Set() (mwHost20Bit_Set(0x14,BIT1)) //Bit 1
#define mwHost20_USBSTS_CompletionOfTransaction_Rd() (mwHost20Bit_Rd(0x14,BIT0)) //Bit 0
#define mwHost20_USBSTS_CompletionOfTransaction_Set() (mwHost20Bit_Set(0x14,BIT0)) //Bit 0
//<6>.0x018(USBINTR - USB Interrupt Enable Register)
#define mwHost20_USBINTR_Rd() (mwHost20Port(0x18))
#define mwHost20_USBINTR_Set(bValue) (mwHost20Port(0x18)=bValue)
#define mwHost20_USBINTR_IntOnAsyncAdvance_Rd() (mwHost20Bit_Rd(0x18,BIT5) ) //Bit 5
#define mwHost20_USBINTR_IntOnAsyncAdvance_Set() (mwHost20Bit_Set(0x18,BIT5)) //Bit 5
#define mwHost20_USBINTR_IntOnAsyncAdvance_Clr() (mwHost20Bit_Clr(0x18,BIT5)) //Bit 5
#define mwHost20_USBINTR_SystemError_Rd() (mwHost20Bit_Rd(0x18,BIT4)) //Bit 4
#define mwHost20_USBINTR_SystemError_Set() (mwHost20Bit_Set(0x18,BIT4)) //Bit 4
#define mwHost20_USBINTR_SystemError_Clr() (mwHost20Bit_Clr(0x18,BIT4)) //Bit 4
#define mwHost20_USBINTR_FrameRollover_Rd() (mwHost20Bit_Rd(0x18,BIT3) ) //Bit 3
#define mwHost20_USBINTR_FrameRollover_Set() (mwHost20Bit_Set(0x18,BIT3)) //Bit 3
#define mwHost20_USBINTR_FrameRollover_Clr() (mwHost20Bit_Clr(0x18,BIT3)) //Bit 3
#define mwHost20_USBINTR_PortChangeDetect_Rd() (mwHost20Bit_Rd(0x18,BIT2) ) //Bit 2
#define mwHost20_USBINTR_PortChangeDetect_Set() (mwHost20Bit_Set(0x18,BIT2)) //Bit 2
#define mwHost20_USBINTR_PortChangeDetect_Clr() (mwHost20Bit_Clr(0x18,BIT2)) //Bit 2
#define mwHost20_USBINTR_USBError_Rd() (mwHost20Bit_Rd(0x18,BIT1) ) //Bit 1
#define mwHost20_USBINTR_USBError_Set() (mwHost20Bit_Set(0x18,BIT1)) //Bit 1
#define mwHost20_USBINTR_USBError_Clr() (mwHost20Bit_Clr(0x18,BIT1)) //Bit 1
#define mwHost20_USBINTR_CompletionOfTransaction_Rd() (mwHost20Bit_Rd(0x18,BIT0) ) //Bit 0
#define mwHost20_USBINTR_CompletionOfTransaction_Set() (mwHost20Bit_Set(0x18,BIT0)) //Bit 0
#define mwHost20_USBINTR_CompletionOfTransaction_Clr() (mwHost20Bit_Clr(0x18,BIT0)) //Bit 0
#define HOST20_USBINTR_IntOnAsyncAdvance 0x20
#define HOST20_USBINTR_SystemError 0x10
#define HOST20_USBINTR_FrameRollover 0x08
#define HOST20_USBINTR_PortChangeDetect 0x04
#define HOST20_USBINTR_USBError 0x02
#define HOST20_USBINTR_CompletionOfTransaction 0x01
//<7>.0x01C(FRINDEX - Frame Index Register (Address = 01Ch))
#define mwHost20_FrameIndex_Rd() (mwHost20Port(0x1C)&0x00001FFF) //Only Read Bit0~Bit12(Skip Bit 13)
#define mwHost20_FrameIndex14Bit_Rd() (mwHost20Port(0x1C)&0x00003FFF) //Only Read Bit0~Bit12(Skip Bit 13)
#define mwHost20_FrameIndex_Set(wValue) (mwHost20Port(0x1C)=wValue)
//<8>.0x024(PERIODICLISTBASE - Periodic Frame List Base Address Register (Address = 024h))
#define mwHost20_PeriodicBaseAddr_Rd() (mwHost20Port(0x24))
#define mwHost20_PeriodicBaseAddr_Set(wValue) (mwHost20Port(0x24)=wValue)
//<9>.0x028(ASYNCLISTADDR - Current Asynchronous List Address Register (Address = 028h))
#define mwHost20_CurrentAsynchronousAddr_Rd() (mwHost20Port(0x28) )
#define mwHost20_CurrentAsynchronousAddr_Set(wValue) (mwHost20Port(0x28)=wValue)
//<10>.0x030(PORTSC - Port Status and Control Register(Address = 030h))
#define mwHost20_PORTSC_Rd() mwHost20Port(0x30)
#define mwHost20_PORTSC_LineStatus_Rd() ((mwHost20Port(0x30)>>10)&0x00000003)
#define mwHost20_PORTSC_PortReset_Rd() mwHost20Bit_Rd(0x30,BIT8)
#define mwHost20_PORTSC_PortReset_Set() mwHost20Bit_Set(0x30,BIT8)
#define mwHost20_PORTSC_PortReset_Clr() mwHost20Bit_Clr(0x30,BIT8)
#define mwHost20_PORTSC_ForceSuspend_Rd() mwHost20Bit_Rd(0x30,BIT7)
#define mwHost20_PORTSC_ForceSuspend_Set() mwHost20Bit_Set(0x30,BIT7)
#define mwHost20_PORTSC_ForceResume_Rd() mwHost20Bit_Rd(0x30,BIT6)
#define mwHost20_PORTSC_ForceResume_Set() mwHost20Bit_Set(0x30,BIT6)
#define mwHost20_PORTSC_ForceResume_Clr() mwHost20Bit_Clr(0x30,BIT6)
#define mwHost20_PORTSC_EnableDisableChange_Rd() mwHost20Bit_Rd(0x30,BIT3)
#define mwHost20_PORTSC_EnableDisableChange_Set() mwHost20Bit_Set(0x30,BIT3)
#define mwHost20_PORTSC_EnableDisable_Rd() mwHost20Bit_Rd(0x30,BIT2)
#define mwHost20_PORTSC_EnableDisable_Set() mwHost20Bit_Set(0x30,BIT2)
#define mwHost20_PORTSC_EnableDisable_Clr() mwHost20Bit_Clr(0x30,BIT2)
#define mwHost20_PORTSC_ConnectChange_Rd() mwHost20Bit_Rd(0x30,BIT1)
#define mwHost20_PORTSC_ConnectChange_Set() mwHost20Bit_Set(0x30,BIT1)
#define mwHost20_PORTSC_ConnectStatus_Rd() mwHost20Bit_Rd(0x30,BIT0)
#define mwHost20_Misc_LineStatus_Rd() ((mwHost20Port(0x30)>>10)&0x00000003)
//<10>.0x040(Misc. Register(Address = 040h))
#define mwHost20_Misc_EOF1Time_Set(bValue) (mwHost20Port(0x40)=((mwHost20Port(0x40)&0xFFFFFFF3)|(((UINT32)(bValue))<<2))) //Bit 2~3
#define mwHost20_Misc_Physuspend_Rd() (mwHost20Bit_Rd(0x40,BIT6)) //Bit 2~3
#define mwHost20_Misc_Physuspend_Set() (mwHost20Bit_Set(0x40,BIT6)) //Bit 2~3
#define mwHost20_Misc_Physuspend_Clr() (mwHost20Bit_Clr(0x40,BIT6)) //Bit 2~3
//<11>.0x080(OTG Control / Status Register (Address = 080h))
#define mwOTG20_Control_HOST_SPD_TYP_Rd() ((mwHost20Port(0x80)>>22)&0x00000003)
#define mwOTG20_Control_A_BUS_REQ_Set() (mwHost20Bit_Set(0x80,BIT4))
#define mwHost20_Control_ForceFullSpeed_Rd() (mwHost20Port(0x80)& BIT12)
#define mwHost20_Control_ForceFullSpeed_Set() (mwHost20Bit_Set(0x80,BIT12))
#define mwHost20_Control_ForceFullSpeed_Clr() (mwHost20Bit_Clr(0x80,BIT12))
#define mwHost20_Control_ForceHighSpeed_Rd() (mwHost20Port(0x80)& BIT14)
#define mwHost20_Control_ForceHighSpeed_Set() (mwHost20Bit_Set(0x80,BIT14))
#define mwHost20_Control_ForceHighSpeed_Clr() (mwHost20Bit_Clr(0x80,BIT14))
#define mwOTG20_Control_Phy_Reset_Set() (mwHost20Bit_Set(0x80,BIT15))
#define mwOTG20_Control_Phy_Reset_Clr() (mwHost20Bit_Clr(0x80,BIT15))
#define mwOTG20_Control_OTG_Reset_Set() (mwHost20Bit_Set(0x80,BIT24))
#define mwOTG20_Control_OTG_Reset_Clr() (mwHost20Bit_Clr(0x80,BIT24))
//<12>.0x0C4(Interrupt Mask)
#define mwOTG20_Interrupt_Mask_Rd() (mwHost20Port(0xC4)&0x00000007)
#define mwOTG20_Interrupt_Mask_Set(bValue) (mwHost20Port(0xC4)=bValue)
#define mwOTG20_Interrupt_Mask_Device_Set() (mwHost20Bit_Set(0xC4,BIT0))
#define mwOTG20_Interrupt_Mask_OTG_Set() (mwHost20Bit_Set(0xC4,BIT1))
#define mwOTG20_Interrupt_Mask_HOST_Set() (mwHost20Bit_Set(0xC4,BIT2))
#define mwOTG20_Interrupt_OutPut_High_Set() (mwHost20Bit_Set(0xC4,BIT3))
#define mwOTG20_Interrupt_OutPut_High_Clr() (mwHost20Bit_Clr(0xC4,BIT3))
//<13>.0x100(Device Controller Registers(Address = 100h~1FFh) )
#define mwPeri20_Control_ChipEnable_Set() (mwHost20Bit_Set(0x100,BIT5))
#define mwPeri20_Control_HALFSPEEDEnable_Set() (mwHost20Bit_Set(0x100,BIT1))
#define mwPeri20_Control_HALFSPEEDEnable_Clr() (mwHost20Bit_Clr(0x100,BIT1))
//=================== 3.Structure Definition =============================================================
//========================================================================================================
//<3.1>iTD Structure Definition****************************************
typedef struct {
//<1>.Next_Link_Pointer Word
UINT32 bTerminal:1; //Bit11~0
UINT32 bType:2; //Bit11~0
UINT32 bReserved:2; //Bit14~12
UINT32 bLinkPointer:27; //Bit15
} Periodic_Frame_List_Cell_Structure;
typedef struct {
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