pe_usb_fifoepxcfg.c

FIC8120方案的 StartCell_Driver

#include <stdarg.h>
#include "Pe_usb.h"
#include "Pe_usb_hs_pos.h"
#include "Pe_usb_fs_pos.h"
#include "FOTG200_peripheral.h"
#include "Pe_my_usbtable.h"

#if((OTG_AP_Satus == Bulk_AP) || (OTG_AP_Satus == Interrupt_AP))
/////////////////////////////////////////////////////
//		vOTGFIFO_EPxCfg_HS(void)
//		Description:
//			1. Configure the FIFO and EPx map
//		input: none
//		output: none
/////////////////////////////////////////////////////
void vOTGFIFO_EPxCfg_HS(void)
{
	int i;
	switch (u8OTGConfigValue)
	{
		#if (HS_CONFIGURATION_NUMBER >= 0X01)
		// Configuration 0X01
		case 0X01:
			switch (u8OTGInterfaceValue)
			{
				#if (HS_C1_INTERFACE_NUMBER >= 0x01)
				// Interface 0
				case 0:
					switch (u8OTGInterfaceAlternateSetting)
					{
						#if (HS_C1_I0_ALT_NUMBER >= 0X01)
						// AlternateSetting 0
						case 0:
							#if (HS_C1_I0_A0_EP_NUMBER >= 0X01)
							//EP0X01
							mUsbEPMap(EP1, HS_C1_I0_A0_EP1_MAP);
							mUsbFIFOMap(HS_C1_I0_A0_EP1_FIFO_START, HS_C1_I0_A0_EP1_FIFO_MAP);
							mUsbFIFOConfig(HS_C1_I0_A0_EP1_FIFO_START, HS_C1_I0_A0_EP1_FIFO_CONFIG);
							
							for(i = HS_C1_I0_A0_EP1_FIFO_START + 1 ;
								i < HS_C1_I0_A0_EP1_FIFO_START + HS_C1_I0_A0_EP1_FIFO_NO ;
							    i ++)
							{
								mUsbFIFOConfig(i, (HS_C1_I0_A0_EP1_FIFO_CONFIG & (~BIT7)) );
							}
							
							mUsbEPMxPtSz(EP1, HS_C1_I0_A0_EP1_DIRECTION, (HS_C1_I0_A0_EP1_MAX_PACKET & 0x7ff) );
							mUsbEPinHighBandSet(EP1 , HS_C1_I0_A0_EP1_DIRECTION , HS_C1_I0_A0_EP1_MAX_PACKET);
							#endif
							#if (HS_C1_I0_A0_EP_NUMBER >= 0X02)
							//EP0X02
							mUsbEPMap(EP2, HS_C1_I0_A0_EP2_MAP);
							
							#if((OTG_AP_Satus == Bulk_AP) && (Bulk_Satus == Bulk_FIFO_SingleDir))
							mUsbFIFOMap(HS_C1_I0_A0_EP2_FIFO_START, HS_C1_I0_A0_EP2_FIFO_MAP);
							#endif
							
							mUsbFIFOConfig(HS_C1_I0_A0_EP2_FIFO_START, HS_C1_I0_A0_EP2_FIFO_CONFIG);
							
							for(i = HS_C1_I0_A0_EP2_FIFO_START + 1 ;
								i < HS_C1_I0_A0_EP2_FIFO_START + HS_C1_I0_A0_EP2_FIFO_NO ;
							    i ++)
							{
								mUsbFIFOConfig(i, (HS_C1_I0_A0_EP2_FIFO_CONFIG & (~BIT7)) );
							}
							
							mUsbEPMxPtSz(EP2, HS_C1_I0_A0_EP2_DIRECTION, (HS_C1_I0_A0_EP2_MAX_PACKET & 0x7ff) );
							mUsbEPinHighBandSet(EP2 , HS_C1_I0_A0_EP2_DIRECTION , HS_C1_I0_A0_EP2_MAX_PACKET);
							#endif
							
							#if (HS_C1_I0_A0_EP_NUMBER >= 0X03)
							//EP0X03
							mUsbEPMap(EP3, HS_C1_I0_A0_EP3_MAP);						
							mUsbFIFOMap(HS_C1_I0_A0_EP3_FIFO_START, HS_C1_I0_A0_EP3_FIFO_MAP);
							mUsbFIFOConfig(HS_C1_I0_A0_EP3_FIFO_START, HS_C1_I0_A0_EP3_FIFO_CONFIG);
							
							for(i = HS_C1_I0_A0_EP3_FIFO_START + 1 ;
								i < HS_C1_I0_A0_EP3_FIFO_START + HS_C1_I0_A0_EP3_FIFO_NO ;
							    i ++)
							{
								mUsbFIFOConfig(i, (HS_C1_I0_A0_EP3_FIFO_CONFIG & (~BIT7)) );
							}
							
							mUsbEPMxPtSz(EP3, HS_C1_I0_A0_EP3_DIRECTION, (HS_C1_I0_A0_EP3_MAX_PACKET & 0x7ff) );
							mUsbEPinHighBandSet(EP3, HS_C1_I0_A0_EP3_DIRECTION , HS_C1_I0_A0_EP3_MAX_PACKET);
							#endif
							
							#if (HS_C1_I0_A0_EP_NUMBER >= 0X04)
							//EP0X04
							mUsbEPMap(EP4, HS_C1_I0_A0_EP4_MAP);							
							mUsbFIFOMap(HS_C1_I0_A0_EP4_FIFO_START, HS_C1_I0_A0_EP4_FIFO_MAP);						
							mUsbFIFOConfig(HS_C1_I0_A0_EP4_FIFO_START, HS_C1_I0_A0_EP4_FIFO_CONFIG);
							
							for(i = HS_C1_I0_A0_EP4_FIFO_START + 1 ;
								i < HS_C1_I0_A0_EP4_FIFO_START + HS_C1_I0_A0_EP4_FIFO_NO ;
							    i ++)
							{
								mUsbFIFOConfig(i, (HS_C1_I0_A0_EP4_FIFO_CONFIG & (~BIT7)) );
							}
							
							mUsbEPMxPtSz(EP4, HS_C1_I0_A0_EP4_DIRECTION, (HS_C1_I0_A0_EP4_MAX_PACKET & 0x7ff) );
							mUsbEPinHighBandSet(EP4 , HS_C1_I0_A0_EP4_DIRECTION , HS_C1_I0_A0_EP4_MAX_PACKET);
							#endif
							break;
						#endif
						default:
							break;
					}
					break;
				#endif
				default:
					break;
			}
			break;
		#endif
		default:
			break;
	}
}

void vOTGFIFO_EPxCfg_FS(void)
{
	int i;
	switch (u8OTGConfigValue)
	{
		#if (FS_CONFIGURATION_NUMBER >= 0X01)
		// Configuration 0X01
		case 0X01:
			switch (u8OTGInterfaceValue)
			{
				#if (FS_C1_INTERFACE_NUMBER >= 0x01)
				// Interface 0
				case 0:
					switch (u8OTGInterfaceAlternateSetting)
					{
						#if (FS_C1_I0_ALT_NUMBER >= 0X01)
						// AlternateSetting 0
						case 0:
							#if (FS_C1_I0_A0_EP_NUMBER >= 0X01)
							//EP0X01
							mUsbEPMap(EP1, FS_C1_I0_A0_EP1_MAP);
							mUsbFIFOMap(FS_C1_I0_A0_EP1_FIFO_START, FS_C1_I0_A0_EP1_FIFO_MAP);
							mUsbFIFOConfig(FS_C1_I0_A0_EP1_FIFO_START, FS_C1_I0_A0_EP1_FIFO_CONFIG);
							
							for(i = FS_C1_I0_A0_EP1_FIFO_START + 1 ;
								i < FS_C1_I0_A0_EP1_FIFO_START + FS_C1_I0_A0_EP1_FIFO_NO ;
							    i ++)
							{
								mUsbFIFOConfig(i, (FS_C1_I0_A0_EP1_FIFO_CONFIG & (~BIT7)) );
							}
							
							mUsbEPMxPtSz(EP1, FS_C1_I0_A0_EP1_DIRECTION, (FS_C1_I0_A0_EP1_MAX_PACKET & 0x7ff));
							mUsbEPinHighBandSet(EP1 , FS_C1_I0_A0_EP1_DIRECTION, FS_C1_I0_A0_EP1_MAX_PACKET);
							#endif
							#if (FS_C1_I0_A0_EP_NUMBER >= 0X02)
							//EP0X02
							mUsbEPMap(EP2, FS_C1_I0_A0_EP2_MAP);
							
							#if((OTG_AP_Satus == Bulk_AP) && (Bulk_Satus == Bulk_FIFO_SingleDir))							
							mUsbFIFOMap(FS_C1_I0_A0_EP2_FIFO_START, FS_C1_I0_A0_EP2_FIFO_MAP);
							#endif
							
							mUsbFIFOConfig(FS_C1_I0_A0_EP2_FIFO_START, FS_C1_I0_A0_EP2_FIFO_CONFIG);
							
							for(i = FS_C1_I0_A0_EP2_FIFO_START + 1 ;
								i < FS_C1_I0_A0_EP2_FIFO_START + FS_C1_I0_A0_EP2_FIFO_NO ;
							    i ++)
							{
								mUsbFIFOConfig(i, (FS_C1_I0_A0_EP2_FIFO_CONFIG & (~BIT7)) );
							}
							
							mUsbEPMxPtSz(EP2, FS_C1_I0_A0_EP2_DIRECTION, (FS_C1_I0_A0_EP2_MAX_PACKET & 0x7ff));
							mUsbEPinHighBandSet(EP2 , FS_C1_I0_A0_EP2_DIRECTION, FS_C1_I0_A0_EP2_MAX_PACKET);
							#endif
							#if (FS_C1_I0_A0_EP_NUMBER >= 0X03)
							//EP0X03
							mUsbEPMap(EP3, FS_C1_I0_A0_EP3_MAP);
							mUsbFIFOMap(FS_C1_I0_A0_EP3_FIFO_START, FS_C1_I0_A0_EP3_FIFO_MAP);
							mUsbFIFOConfig(FS_C1_I0_A0_EP3_FIFO_START, FS_C1_I0_A0_EP3_FIFO_CONFIG);
							
							for(i = FS_C1_I0_A0_EP3_FIFO_START + 1 ;
								i < FS_C1_I0_A0_EP3_FIFO_START + FS_C1_I0_A0_EP3_FIFO_NO ;
							    i ++)
							{
								mUsbFIFOConfig(i, (FS_C1_I0_A0_EP3_FIFO_CONFIG & (~BIT7)) );
							}
							
							mUsbEPMxPtSz(EP3, FS_C1_I0_A0_EP3_DIRECTION, (FS_C1_I0_A0_EP3_MAX_PACKET & 0x7ff));
							mUsbEPinHighBandSet(EP3 , FS_C1_I0_A0_EP3_DIRECTION, FS_C1_I0_A0_EP3_MAX_PACKET);
							#endif
							#if (FS_C1_I0_A0_EP_NUMBER >= 0X04)
							//EP0X01
							mUsbEPMap(EP4, FS_C1_I0_A0_EP4_MAP);
							mUsbFIFOMap(FS_C1_I0_A0_EP4_FIFO_START, FS_C1_I0_A0_EP4_FIFO_MAP);
							mUsbFIFOConfig(FS_C1_I0_A0_EP4_FIFO_START, FS_C1_I0_A0_EP4_FIFO_CONFIG);
							
							for(i = FS_C1_I0_A0_EP4_FIFO_START + 1 ;
								i < FS_C1_I0_A0_EP4_FIFO_START + FS_C1_I0_A0_EP4_FIFO_NO ;
							    i ++)
							{
								mUsbFIFOConfig(i, (FS_C1_I0_A0_EP4_FIFO_CONFIG & (~BIT7)) );
							}
							
							mUsbEPMxPtSz(EP4, FS_C1_I0_A0_EP4_DIRECTION, (FS_C1_I0_A0_EP4_MAX_PACKET & 0x7ff));
							mUsbEPinHighBandSet(EP4 , FS_C1_I0_A0_EP4_DIRECTION, FS_C1_I0_A0_EP4_MAX_PACKET);
							#endif
							break;
						#endif
						default:
							break;
					}
					break;
				#endif
				default:
					break;
			}
			break;
		#endif
		default:
			break;
	}
}

#elif((OTG_AP_Satus == IsochronousIN_AP) || (OTG_AP_Satus == IsochronousOUT_AP))
/////////////////////////////////////////////////////
//		vOTGFIFO_EPxCfg_HS(void)
//		Description:
//			1. Configure the FIFO and EPx map
//		input: none
//		output: none
/////////////////////////////////////////////////////
void vOTGFIFO_EPxCfg_HS(void)
{
	int i;
	switch (u8OTGConfigValue)
	{
		#if (HS_CONFIGURATION_NUMBER >= 0X01)
		// Configuration 0X01
		case 0X01:
			switch (u8OTGInterfaceValue)
			{
				#if (HS_C1_INTERFACE_NUMBER >= 0x01)
				// Interface 0
				case 0:
					switch (u8OTGInterfaceAlternateSetting)
					{
						#if (HS_C1_I0_ALT_NUMBER >= 0X01)
						// AlternateSetting 0
						case 0:
							#if (HS_C1_I0_A0_EP_NUMBER >= 0X01)
							//EP0X01
							mUsbEPMap(EP1, HS_C1_I0_A0_EP1_MAP);
							mUsbFIFOMap(HS_C1_I0_A0_EP1_FIFO_START, HS_C1_I0_A0_EP1_FIFO_MAP);
							mUsbFIFOConfig(HS_C1_I0_A0_EP1_FIFO_START, HS_C1_I0_A0_EP1_FIFO_CONFIG);
							
							for(i = HS_C1_I0_A0_EP1_FIFO_START + 1 ;
								i < HS_C1_I0_A0_EP1_FIFO_START + HS_C1_I0_A0_EP1_FIFO_NO ;
							    i ++)
							{
								mUsbFIFOConfig(i, (HS_C1_I0_A0_EP1_FIFO_CONFIG & (~BIT7)) );
							}
							
							mUsbEPMxPtSz(EP1, HS_C1_I0_A0_EP1_DIRECTION, (HS_C1_I0_A0_EP1_MAX_PACKET & 0x7ff) );
							mUsbEPinHighBandSet(EP1 , HS_C1_I0_A0_EP1_DIRECTION , HS_C1_I0_A0_EP1_MAX_PACKET);
							#endif
							break;
						#endif
						default:
							break;
					}
					break;
				#endif
				default:
					break;
			}
			break;
		#endif
		default:
			break;
	}
}

void vOTGFIFO_EPxCfg_FS(void)
{
	int i;
	switch (u8OTGConfigValue)
	{
		#if (FS_CONFIGURATION_NUMBER >= 0X01)
		// Configuration 0X01
		case 0X01:
			switch (u8OTGInterfaceValue)
			{
				#if (FS_C1_INTERFACE_NUMBER >= 0x01)
				// Interface 0
				case 0:
					switch (u8OTGInterfaceAlternateSetting)
					{
						#if (FS_C1_I0_ALT_NUMBER >= 0X01)
						// AlternateSetting 0
						case 0:
							#if (FS_C1_I0_A0_EP_NUMBER >= 0X01)
							//EP0X01
							mUsbEPMap(EP1, FS_C1_I0_A0_EP1_MAP);
							mUsbFIFOMap(FS_C1_I0_A0_EP1_FIFO_START, FS_C1_I0_A0_EP1_FIFO_MAP);
							mUsbFIFOConfig(FS_C1_I0_A0_EP1_FIFO_START, FS_C1_I0_A0_EP1_FIFO_CONFIG);
							
							for(i = FS_C1_I0_A0_EP1_FIFO_START + 1 ;
								i < FS_C1_I0_A0_EP1_FIFO_START + FS_C1_I0_A0_EP1_FIFO_NO ;
							    i ++)
							{
								mUsbFIFOConfig(i, (FS_C1_I0_A0_EP1_FIFO_CONFIG & (~BIT7)) );
							}
							
							mUsbEPMxPtSz(EP1, FS_C1_I0_A0_EP1_DIRECTION, (FS_C1_I0_A0_EP1_MAX_PACKET & 0x7ff));
							mUsbEPinHighBandSet(EP1 , FS_C1_I0_A0_EP1_DIRECTION, FS_C1_I0_A0_EP1_MAX_PACKET);
							#endif
							break;
						#endif
						default:
							break;
					}
					break;
				#endif
				default:
					break;
			}
			break;
		#endif
		default:
			break;
	}
}

#endif