pe_usb_bulk.c

FIC8120方案的 StartCell_Driver

///////////////////////////////////////////////////////////////////////////////
//
//	File name: usb_bulk.c
//	Version: 1.0
//	Date: 2003/8/05
//
//	Author: Andrew
//	Email: [e-mail]
//	Phone: [phone]
//	Company: Faraday Tech. Corp.
//
//	Description: USB Bulk IN OUT test Rountine & relatived subroutine
//
///////////////////////////////////////////////////////////////////////////////
#define USB_BULK_GLOBALS
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
//#include "fLib.h"
#include "Pe_usb.h"
#include "FA510.h"
#include "FOTG200_peripheral.h"
#include "Pe_my_usbtable.h"

MassStorageState eOTGProessCBW(void);
MassStorageState eOTGDataOut(INT16U u16FIFOByteCount);
MassStorageState eOTGDataIn(void);
void vShowCBW(void);
void vShowCSW(void);
void vOTGSendCSW(void);
void vOTG_FIFO_INT_action(MassStorageState eState);

MassStorageState eUsbOTGMassStorageState;
INT8U*   u8VirtOTGMemory = NULL;//[MAX_BUFFER_SIZE];
INT32U*   u32VirtOTGMemory = NULL;

CSW tOTGCSW;
INT32U   u32VirtOTGMemoryIndex;
CBW tOTGCBW;

INT32U	 u32OTGFIFOUseDMA;
INT32U	 u32UseDMAOTGChannel;
INT8U   bOTGDMARunning;

extern void OTGH_Error_Handle(void);
///////////////////////////////////////////////////////////////////////////////
//		vOTG_APInit()
//		Description: User specified circuit (AP) init
//		input: none
//		output: none
///////////////////////////////////////////////////////////////////////////////
void vOTG_APInit(void)
{		
	////// initial Cx Vandor command test //////
	u8CxOUTVandorDataCount = 0;
	u8CxINVandorDataCount = 0;
	
	////// initial Bulk //////
	eUsbOTGMassStorageState = STATE_CBW;	// Init State
	if(u8VirtOTGMemory != NULL)
		free(u8VirtOTGMemory);
	u8VirtOTGMemory = (INT8U *)malloc(MAX_BUFFER_SIZE);

//	for(u16_i = 0; u16_i < MAX_BUFFER_SIZE; u16_i ++)
//  {
//		u8VirtOTGMemory[u16_i] = 0x00;			// Init Buffer
//	}	
	
	if(u32VirtOTGMemory != NULL)
		free(u32VirtOTGMemory);
	u32VirtOTGMemory = (INT32U *)malloc(MAX_BUFFER_SIZE);
	memcpy(u32VirtOTGMemory,u8VirtOTGMemory,MAX_BUFFER_SIZE);
	
	tOTGCSW.u32Signature = CSW_SIGNATE;	// Init u32Signature
	////// initial INT and ISO test ////////////
	u8OTGInterruptCount = 0;
	u32OTGInterrupt_TX_COUNT = 1;	
	u8OTGInterruptOutCount = 0;
	u32OTGInterrupt_RX_COUNT = 1;
	
	u32ISOOTGInTransferCount = 0;
	u32ISOOTGOutTransferCount = 0;	
}

///////////////////////////////////////////////////////////////////////////////
//		vUsb_Bulk_Out()
//		Description: USB FIFO2 interrupt service process
//		input: none
//		output: none
///////////////////////////////////////////////////////////////////////////////
void vUsb_Bulk_Out(INT16U u16FIFOByteCount)
{
	switch(eUsbOTGMassStorageState)
	{
		case STATE_CBW:
			if (u16FIFOByteCount == 31)
				eUsbOTGMassStorageState = eOTGProessCBW();
			else
				mUsbEPoutStallSet(mUsbFIFOMapRd(FIFO2));
			break;
		case STATE_CB_DATA_OUT:
#if 0			
			if((INT16U)tOTGCBW.u32DataTransferLength != u16FIFOByteCount)	
				printf("L%x: Byte Count Error = %d. (Correct = %d)\n", 
					u8LineOTGCount, u16FIFOByteCount, (INT16U)tOTGCBW.u32DataTransferLength);
			else
#endif				
				eUsbOTGMassStorageState = eOTGDataOut(u16FIFOByteCount);
			break;
		default:
			if(u8OTGMessageLevel & (MESS_INFO & MESS_ERROR & MESS_WARNING))
				printf("L%x: Error FIFO2_OUT interrupt.\n", u8LineOTGCount);
			break;
	}
	vOTG_FIFO_INT_action(eUsbOTGMassStorageState);
}

///////////////////////////////////////////////////////////////////////////////
//		vUsb_Bulk_In()
//		Description: USB FIFO0 interrupt service process
//		input: none
//		output: none
///////////////////////////////////////////////////////////////////////////////
void vUsb_Bulk_In(void)
{
	switch(eUsbOTGMassStorageState)
	{
		case STATE_CSW:
			vOTGSendCSW();
			eUsbOTGMassStorageState = STATE_CBW;
			mUsbIntF0INDis();
			break;
		case STATE_CB_DATA_IN:
			eUsbOTGMassStorageState = eOTGDataIn();
			break;
		default:
			if(u8OTGMessageLevel & (MESS_INFO & MESS_ERROR & MESS_WARNING))
				printf("L%x: Error FIFO0_IN interrupt.\n", u8LineOTGCount);
			break;
	}
	if(!bOTGDMARunning)
		vOTG_FIFO_INT_action(eUsbOTGMassStorageState);
}


///////////////////////////////////////////////////////////////////////////////
//		vOTG_FIFO_INT_action()
//		Description: FIFO interrupt enable or not
//					 depend on the STORAGE state
//		input: none
//		output: none
///////////////////////////////////////////////////////////////////////////////
void vOTG_FIFO_INT_action(MassStorageState eState)
{
	switch(eState)
	{
		case STATE_CBW:
		case STATE_CB_DATA_OUT:
			mUsbIntF0INDis();
			break;
		case STATE_CSW:
		case STATE_CB_DATA_IN:
			mUsbIntF0INEn();
			break;
		default:
			break;
	}
}


///////////////////////////////////////////////////////////////////////////////
//		eOTGProessCBW()
//		Description: Process the CBW
//		input: none
//		output: MassStorageState
///////////////////////////////////////////////////////////////////////////////
MassStorageState eOTGProessCBW(void)
{
	MassStorageState eState;
#if(Bulk_Satus == Bulk_FIFO_SingleDir)	
	vOTGDxFRd(FIFO2, (INT8U *)(&tOTGCBW), 12);			// change little endian to big endian
	vOTGDxFRd(FIFO2, (INT8U *)(&(tOTGCBW.u8Flags)), 19);
#elif(Bulk_Satus == Bulk_FIFO_BiDir)	
	vOTGDxFRd(FIFO0, (INT8U *)(&tOTGCBW), 12);			// change little endian to big endian
	vOTGDxFRd(FIFO0, (INT8U *)(&(tOTGCBW.u8Flags)), 19);
#endif
	
#if ShowMassMsg
//	if(u8OTGMessageLevel & MESS_INFO)
		vShowCBW();
#endif
	
	if(tOTGCBW.u32Signature != CBW_SIGNATE)
		eState = STATE_CBW;
	else
	{
		// pass u32DataTransferLength to u32DataResidue
		tOTGCSW.u32DataResidue = tOTGCBW.u32DataTransferLength;
		// pass Tag from CBW to CSW
		tOTGCSW.u32Tag = tOTGCBW.u32Tag;
		// Assume Status is CMD_PASS
		tOTGCSW.u8Status = CSW_STATUS_CMD_PASS;
		// Get Virtual Memory start address.
#if 1		
		u32VirtOTGMemoryIndex = (INT32U)(tOTGCBW.u8CB[0]) | ((INT32U)tOTGCBW.u8CB[1] << 8);
#else
		u32VirtOTGMemoryIndex = ((INT32U)(tOTGCBW.u8CB[0]) | ((INT32U)tOTGCBW.u8CB[1] << 8))>>2;
#endif
		if (tOTGCSW.u32DataResidue == 0)
			eState = STATE_CSW;
		else if (tOTGCBW.u8Flags == 0x00)
			eState = STATE_CB_DATA_OUT;
		else
			eState = STATE_CB_DATA_IN;
	}
	return eState;
}

///////////////////////////////////////////////////////////////////////////////
//		Waiting_For_DMA_Complete()
//		Description: Process the data intput stage
//		input: none
//		output: MassStorageState
///////////////////////////////////////////////////////////////////////////////
#if 0
int Waiting_For_DMA_Complete(INT8U FIFONum)
{

 UINT32 wTemp;
 //Waiting for Complete
 
	while(1)
	{
		wTemp = mUsbIntSrc2Rd();
		if(wTemp & BIT8)
		{
		  mUsbFIFOClr((INT32U)FIFONum);
			mUsbIntDmaErrClr();
			printf("Waiting_For_DMA_Complete => FIFO%d transfer DMA error..\n",FIFONum);
			while(1);
			break;
		}
		if(wTemp & BIT7)
		{
			mUsbIntDmaFinishClr();
			break;
		}
		if((wTemp & 0x00000007)>0)//If (Resume/Suspend/Reset) exit
		{
      mUsbDMARst();
      mUsbFIFOClr((INT32U)FIFONum);
			mUsbIntDmaFinishClr();
			printf("L%x: FIFO%d OUT transfer DMA stop because USB Resume/Suspend/Reset..", u8LineOTGCount ++,FIFONum);
			break;
		}
	}
	mUsbDMA2FIFOSel(FOTG200_DMA2FIFO_Non);
 
 bOTGDMARunning = FALSE;

 vOTGCheckDMA();

return 0;

}
#endif
///////////////////////////////////////////////////////////////////////////////
//		eOTGDataOut()
//		Description: Process the data output stage
//		input: none
//		output: MassStorageState
///////////////////////////////////////////////////////////////////////////////

MassStorageState eOTGDataOut(INT16U u16FIFOByteCount)
{
 //INT32U *u32pData; //Bruce;;Test
 
 if (bOTGDMARunning == TRUE)
     {printf("??? Error (eOTGDataOut during bOTGDMARunning = TRUE )\n");
     OTGH_Error_Handle();
     }
 
 memset(u8VirtOTGMemory, 0xaa, MAX_BUFFER_SIZE);
 
 
 
 
 
#if DCacheEnable 
 CPUCleanInvalidateDCacheAll();
 fLib_DisableDCache();   
#endif
 
#if(Bulk_Satus == Bulk_FIFO_SingleDir)
 mUsbIntF0INDis();
 mUsbIntF2OUTDis();
 u32OTGFIFOUseDMA = FIFO2;
 mUsbDMA2FIFOSel(FOTG200_DMA2FIFO2);
#elif(Bulk_Satus == Bulk_FIFO_BiDir) 
 mUsbIntF0INDis();
 mUsbIntF0OUTDis();
 u32OTGFIFOUseDMA = FIFO0;
 mUsbDMA2FIFOSel(FOTG200_DMA2FIFO0);
#endif
 mUsbDmaConfig(tOTGCSW.u32DataResidue,DIRECTION_OUT);
 mUsbDmaAddr(&u8VirtOTGMemory[u32VirtOTGMemoryIndex]);
 
 if (mUsbIntDmaFinishRd()>0)
     {printf("??? Error (Do not clear mUsbIntDmaFinish during start another DMA )\n");
     OTGH_Error_Handle();
     }

 
  //Bruce;;Move// mUsbDmaStart();

 mUsbIntEP0SetupDis();
 mUsbIntEP0InDis();
 mUsbIntEP0OutDis();
 mUsbIntEP0EndDis();
 bOTGDMARunning = TRUE;

 //u32pData=0x92000138;
 //if ((*u32pData&0x00000003)!=3)
 //    {printf("??? Peripheral can not disable the mask...\n");
     
 //    OTGH_Error_Handle();
 //    }


 //u32pData=0x92000038;//Debug;;Bruce
 //*u32pData=0xAA;//Debug;;Bruce
 
 
 mUsbDmaStart();//Bruce;;Move 
 
#if 0//Bruce;;07152005
 
Waiting_For_DMA_Complete(FIFO0);
 
#endif  

 
 return STATE_CB_DATA_OUT;
}
 



///////////////////////////////////////////////////////////////////////////////
//		eOTGDataIn()
//		Description: Process the data intput stage
//		input: none
//		output: MassStorageState
///////////////////////////////////////////////////////////////////////////////
MassStorageState eOTGDataIn(void)
{

// INT32U *u32pData; //Bruce;;Test
 if (bOTGDMARunning == TRUE)
     {printf("??? Error (eOTGDataIn during bOTGDMARunning = TRUE )\n");
     OTGH_Error_Handle();
     }
 


#if DCacheEnable 
 CPUCleanInvalidateDCacheAll();
 fLib_DisableDCache();   
#endif
 
#if(Bulk_Satus == Bulk_FIFO_SingleDir)
 mUsbIntF0INDis();
 mUsbIntF2OUTDis();
 u32OTGFIFOUseDMA = FIFO2;
#elif(Bulk_Satus == Bulk_FIFO_BiDir) 
 mUsbIntF0INDis();
 mUsbIntF0OUTDis();
 u32OTGFIFOUseDMA = FIFO0;
#endif
 
 mUsbDmaConfig(tOTGCSW.u32DataResidue,DIRECTION_IN);
 mUsbDMA2FIFOSel(FOTG200_DMA2FIFO0);
 mUsbDmaAddr(&u8VirtOTGMemory[u32VirtOTGMemoryIndex]);
 
 if (mUsbIntDmaFinishRd()>0)
     {printf("??? Error (Do not clear mUsbIntDmaFinish during start another DMA )\n");
     OTGH_Error_Handle();
     }
    
//Bruce;;Move  mUsbDmaStart();
 
 mUsbIntEP0SetupDis();
 mUsbIntEP0InDis();
 mUsbIntEP0OutDis();
 mUsbIntEP0EndDis();
 bOTGDMARunning = TRUE;
 u32OTGFIFOUseDMA = FIFO0;


// u32pData=0x92000138;
// if ((*u32pData&0x00000003)!=3)
//     {printf("??? Peripheral can not disable the mask...\n");
     
 //    OTGH_Error_Handle();
 //    }

//  u32pData=0x92000038;//Debug;;Bruce
// *u32pData=0xAA;//Debug;;Bruce
 
 mUsbDmaStart();//Bruce;;Move 
 
 
#if 0//Bruce;;07152005
 
Waiting_For_DMA_Complete(FIFO0);
 
#endif  
 
 
 return STATE_CB_DATA_IN;
}
 


///////////////////////////////////////////////////////////////////////////////
//		vShowCBW()
//		Description: show the whole CBW structure
//		input: none
//		output: none
///////////////////////////////////////////////////////////////////////////////
void vShowCBW(void)
{
	INT8U i;
	INT8U * pp;
	pp = (INT8U *)&tOTGCBW;
	printf("tOTGCBW: \n");
	for (i = 0; i < 16; i ++)
		printf("%02x ", *(pp ++));
	printf("\n");
	for (i = 16; i < 31; i ++)
		printf("%02x ", *(pp ++));
	printf("\n");
}


///////////////////////////////////////////////////////////////////////////////
//		vShowCSW()
//		Description: show the whole CSW structure
//		input: none
//		output: none
///////////////////////////////////////////////////////////////////////////////
void vShowCSW(void)
{
	if(u8OTGMessageLevel & (MESS_INFO))
	{
		INT8U i;
		INT8U * pp;
		pp = (INT8U *)&tOTGCSW;
		printf("tOTGCSW: \n");
		for (i = 0; i < 13; i ++)
			printf("%02x ", *(pp ++));
		printf("\n");
	}
}

///////////////////////////////////////////////////////////////////////////////
//		vOTGSendCSW()
//		Description: Send out the CSW structure to PC
//		input: none
//		output: none
///////////////////////////////////////////////////////////////////////////////
void vOTGSendCSW()
{
	// Send CSW to F0 via DBUS;
#if ShowMassMsg
	vShowCSW();
#endif

	vOTGDxFWr(FIFO0, (INT8U *)(&tOTGCSW			  ) , 13);
	mUsbFIFODone(FIFO0);
}