memmap.s

FIC8120方案的 StartCell_Driver

;/***************************************************************************
;   Copyright ARM Limited 1998 - 2000.  All rights reserved.
;****************************************************************************/

	TTL     Memory map for target-specific MMU setup    > memmap.s
	; -----------------------------------------------------------------
	; This file provides the memory map table for MMU initialization 
	; for the Integrator boards. The SETUP_MMU macro references this
	; table to build the TLBs on power-up.
	;
	; $Revision: 1.1.1.1 $
	;   $Author: ivan $
	;     $Date: 2006/04/18 07:34:53 $
	;
	; This example is more complcated than most as Integrator may have
	; MPU or MMU capable processors. Normal platforms would only have
	; one and the other table would be all zeros.
	;
	; -----------------------------------------------------------------

	;INCLUDE bits.s
	INCLUDE sizes.s
	INCLUDE	board.s
	INCLUDE	mmu_h.s
	INCLUDE	mmumacro.s

	; -----------------------------------------------------------------
	; Note: Tables must end with all zeros
	; WindowsCE uses a table of the same format, but without the access
	; word. If OEMAddressTable exists, but uHAL_Level1Table doesn't, the
	; MMU setup code might (but doesn't yet) use the truncated format.

	; -----------------------------------------------------------------
	; MMU Mapping tables of the format:
	;
	; Virtual Address, Physical Address, Access Permissions, Area Size
	; Level 2 areas are more complex to define: 
	; Virt Addr, L2 Table & type, Phys Addr + L2 Access Perms, Area Size

	AREA    |C$$code$$__mmutable|, CODE, READONLY

	LTORG

	IMPORT	Level2tab_ROM

	EXPORT	uHAL_AddressTable	; Address map for MMUs
	EXPORT	uHAL_MappingTable	; Mapping for MPUs


uHAL_MappingTable

	; Define MPU regions/areas
	; Format is region number, base address, size and access permissions
	;DCD	0,          0x90000000,   MPU_SZ_256M, IO_ACCESS
	;DCD	1,          0, MPU_SZ_256M, DRAM_ACCESS
	;DCD	2, CPE_ROM_BASE, MPU_SZ_128K, FLASH_ACCESS
	
	DCD	0,	0,	0,	0	; End of Table (MUST BE ZEROS!)


uHAL_AddressTable

	; MMU Mapping tables of the format:
	;
	; Virtual Address, Physical Address, Access Permissions, Area Size

	; Map SDRAM to low memory, reassembling discontinuous chunks of RAM.
	; 0x00000000 -> 0x00000000	
	; 0x90000000 -> 0x90000000  (Not writeable, not buffered)
	DCD  CPE_SDRAM_BASE, CPE_SDRAM_BASE
	DCD	DRAM_ACCESS, SZ_2G	


	; Configure Peripheral Register section accesses 
	DCD	0x80000000, 0x80000000
	DCD	IO_ACCESS, SZ_2G



	DCD	0,	0,	0,	0	; End of Table (MUST BE ZEROS!)
	
	END