mmumacro.s

FIC8120方案的 StartCell_Driver

;
	MACRO
	WRMMU_FlushTB	$reg_number
 IF :LNOT: :DEF: HAL_HAS_MMU
	NO_WRMMU_FlushTB	$reg_number
 ENDIF
 IF :DEF: ARM720T
	WRMMU_FlushTB_720T	$reg_number
 ENDIF
 IF :DEF: ARM922
	WRMMU_FlushTB_920T	$reg_number
 ENDIF
 IF :DEF: ARM1020T
	WRMMU_FlushTB_1020T	$reg_number
 ENDIF
 IF :DEF: SA110
	WRMMU_FlushTB_110	$reg_number
 ENDIF
 IF :DEF: XSCALE
	WRMMU_FlushTB_XSCALE	$reg_number
 ENDIF
	MEND

;Flush Instruction TLB 
;
	MACRO
	WRMMU_FlushITB	$reg_number
 IF :LNOT: :DEF: HAL_HAS_MMU
	NO_WRMMU_FlushITB	$reg_number
 ENDIF
 IF :DEF: ARM720T
	WRMMU_FlushITB_720T	$reg_number
 ENDIF
 IF :DEF: ARM922
	WRMMU_FlushITB_920T	$reg_number
 ENDIF
 IF :DEF: ARM1020T
	WRMMU_FlushITB_1020T	$reg_number
 ENDIF
 IF :DEF: SA110
	WRMMU_FlushITB_110	$reg_number
 ENDIF
 IF :DEF: XSCALE
	WRMMU_FlushITB_XSCALE	$reg_number
 ENDIF
	MEND

;Flush Data TLB
;
	MACRO
	WRMMU_FlushDTB	$reg_number
 IF :LNOT: :DEF: HAL_HAS_MMU
	NO_WRMMU_FlushDTB	$reg_number
 ENDIF
 IF :DEF: ARM720T
	WRMMU_FlushDTB_720T	$reg_number
 ENDIF
 IF :DEF: ARM922
	WRMMU_FlushDTB_920T	$reg_number
 ENDIF
 IF :DEF: ARM1020T
	WRMMU_FlushDTB_1020T	$reg_number
 ENDIF
 IF :DEF: SA110
	WRMMU_FlushDTB_110	$reg_number
 ENDIF
 IF :DEF: XSCALE
	WRMMU_FlushDTB_XSCALE	$reg_number
 ENDIF
	MEND

;Coprocessor read of Coprocessor Access Control reg. 
;
	MACRO
	RDCP_Access	$reg_number
 IF :DEF: XSCALE
	RDCP_Access_XSCALE	$reg_number
 ENDIF
	MEND

;Coprocessor write of Coprocessor Access Control reg. 
;
	MACRO
	WRCP_Access	$reg_number
 IF :DEF: XSCALE
	WRCP_Access_XSCALE	$reg_number
 ENDIF
	MEND

;-----------------------------------------------------------
; MPU support macros:

;Coprocessor write of MPU cache bits 
;
	MACRO 
	WRMPU_CacheBits	$reg_number
 IF :LNOT: :DEF: HAL_HAS_MPU
	NO_WRMPU_CacheBits	$reg_number
 ENDIF
 IF :DEF: ARM740T
	WRMPU_CacheBits_740T	$reg_number
 ENDIF
 IF :DEF: ARM940T
	WRMPU_CacheBits_940T	$reg_number
 ENDIF
 IF :DEF: ARM946T
	WRMPU_CacheBits_946T	$reg_number
 ENDIF
	MEND

;Coprocessor write of MPU buffer bits 
;
	MACRO 
	WRMPU_BufferBits	$reg_number
 IF :LNOT: :DEF: HAL_HAS_MPU
	NO_WRMPU_BufferBits	$reg_number
 ENDIF
 IF :DEF: ARM740T
	WRMPU_BufferBits_740T	$reg_number
 ENDIF
 IF :DEF: ARM940T
	WRMPU_BufferBits_940T	$reg_number
 ENDIF
 IF :DEF: ARM946T
	WRMPU_BufferBits_946T	$reg_number
 ENDIF
	MEND

;Coprocessor write of MPU access bits 
;
	MACRO 
	WRMPU_AccessBits	$reg_number
 IF :LNOT: :DEF: HAL_HAS_MPU
	NO_WRMPU_AccessBits	$reg_number
 ENDIF
 IF :DEF: ARM740T
	WRMPU_AccessBits_740T	$reg_number
 ENDIF
 IF :DEF: ARM940T
	WRMPU_AccessBits_940T	$reg_number
 ENDIF
 IF :DEF: ARM946T
	WRMPU_AccessBits_946T	$reg_number
 ENDIF
	MEND

;Coprocessor write of MPU region registors 
;
	MACRO 
	WRMPU_Region	$region, $reg_number
 IF :LNOT: :DEF: HAL_HAS_MPU
	NO_WRMPU_Region	$region, $reg_number
 ENDIF
 IF :DEF: ARM740T
	WRMPU_Region_740T	$region, $reg_number
 ENDIF
 IF :DEF: ARM940T
	WRMPU_Region_940T	$region, $reg_number
 ENDIF
 IF :DEF: ARM946T
	WRMPU_Region_946T	$region, $reg_number
 ENDIF
	MEND

;-----------------------------------------------------------
;Coprocessor cache control 
;Flush I & D Caches
;
	MACRO 
	WRCACHE_FlushIDC	$reg_number
 IF :LNOT: :DEF: HAL_HAS_CACHE
	NO_WRCACHE_FlushIDC	$reg_number
 ENDIF
 IF :DEF: ARM720T
	WRCACHE_FlushIDC_720T	$reg_number
 ENDIF
 IF :DEF: ARM740T
	WRCACHE_FlushIDC_740T	$reg_number
 ENDIF
 IF :DEF: ARM922
	WRCACHE_FlushIDC_920T	$reg_number
 ENDIF
 IF :DEF: ARM940T
	WRCACHE_FlushIDC_940T	$reg_number
 ENDIF
 IF :DEF: ARM946T
	WRCACHE_FlushIDC_946T	$reg_number
 ENDIF
 IF :DEF: ARM1020T
	WRCACHE_FlushIDC_1020T	$reg_number
 ENDIF
 IF :DEF: SA110
	WRCACHE_FlushIDC_110	$reg_number
 ENDIF
 IF :DEF: XSCALE
	WRCACHE_FlushIDC_XSCALE	$reg_number
 ENDIF
	MEND

;Coprocessor cache control 
;Flush ICache
;
	MACRO 
	WRCACHE_FlushIC	$reg_number
 IF :LNOT: :DEF: HAL_HAS_CACHE
	NO_WRCACHE_FlushIC	$reg_number
 ENDIF
 IF :DEF: ARM720T
	WRCACHE_FlushIC_720T	$reg_number
 ENDIF
 IF :DEF: ARM740T
	WRCACHE_FlushIC_740T	$reg_number
 ENDIF
 IF :DEF: ARM922
	WRCACHE_FlushIC_920T	$reg_number
 ENDIF
 IF :DEF: ARM940T
	WRCACHE_FlushIC_940T	$reg_number
 ENDIF
 IF :DEF: ARM946T
	WRCACHE_FlushIC_946T	$reg_number
 ENDIF
 IF :DEF: ARM1020T
	WRCACHE_FlushIC_1020T	$reg_number
 ENDIF
 IF :DEF: SA110
	WRCACHE_FlushIC_110	$reg_number
 ENDIF
 IF :DEF: XSCALE
	WRCACHE_FlushIC_XSCALE	$reg_number
 ENDIF
	MEND

;Coprocessor cache control 
;Flush DCache
;
	MACRO 
	WRCACHE_FlushDC	$reg_number
 IF :LNOT: :DEF: HAL_HAS_CACHE
	NO_WRCACHE_FlushDC	$reg_number
 ENDIF
 IF :DEF: ARM720T
	WRCACHE_FlushDC_720T	$reg_number
 ENDIF
 IF :DEF: ARM740T
	WRCACHE_FlushDC_740T	$reg_number
 ENDIF
 IF :DEF: ARM922
	WRCACHE_FlushDC_920T	$reg_number
 ENDIF
 IF :DEF: ARM940T
	WRCACHE_FlushDC_940T	$reg_number
 ENDIF
 IF :DEF: ARM946T
	WRCACHE_FlushDC_946T	$reg_number
 ENDIF
 IF :DEF: ARM1020T
	WRCACHE_FlushDC_1020T	$reg_number
 ENDIF
 IF :DEF: SA110
	WRCACHE_FlushDC_110	$reg_number
 ENDIF
 IF :DEF: XSCALE
	WRCACHE_FlushDC_XSCALE	$reg_number
 ENDIF
	MEND

;Coprocessor cache control 
;Flush DCache entry
;
	MACRO 
	WRCACHE_CacheFlushDentry	$reg_number
 IF :LNOT: :DEF: HAL_HAS_CACHE
	NO_WRCACHE_CacheFlushDentry	$reg_number
 ENDIF
 IF :DEF: ARM720T
	WRCACHE_CacheFlushDentry_720T	$reg_number
 ENDIF
 IF :DEF: ARM740T
	WRCACHE_CacheFlushDentry_740T	$reg_number
 ENDIF
 IF :DEF: ARM922
	WRCACHE_CacheFlushDentry_920T	$reg_number
 ENDIF
 IF :DEF: ARM940T
	WRCACHE_CacheFlushDentry_940T	$reg_number
 ENDIF
 IF :DEF: ARM946T
	WRCACHE_CacheFlushDentry_946T	$reg_number
 ENDIF
 IF :DEF: ARM1020T
	WRCACHE_CacheFlushDentry_1020T	$reg_number
 ENDIF
 IF :DEF: SA110
	WRCACHE_CacheFlushDentry_110	$reg_number
 ENDIF
 IF :DEF: XSCALE
	WRCACHE_CacheFlushDentry_XSCALE	$reg_number
 ENDIF
	MEND

;Coprocessor cache control 
;Clean DCache entry
;
	MACRO 
	WRCACHE_CleanDCentry	$reg_number
 IF :LNOT: :DEF: HAL_HAS_CACHE
	NO_WRCACHE_CleanDCentry	$reg_number
 ENDIF
 IF :DEF: ARM720T
	WRCACHE_CleanDCentry_720T	$reg_number
 ENDIF
 IF :DEF: ARM740T
	WRCACHE_CleanDCentry_740T	$reg_number
 ENDIF
 IF :DEF: ARM922
	WRCACHE_CleanDCentry_920T	$reg_number
 ENDIF
 IF :DEF: ARM940T
	WRCACHE_CleanDCentry_940T	$reg_number
 ENDIF
 IF :DEF: ARM946T
	WRCACHE_CleanDCentry_946T	$reg_number
 ENDIF
 IF :DEF: ARM1020T
	WRCACHE_CleanDCentry_1020T	$reg_number
 ENDIF
 IF :DEF: SA110
	WRCACHE_CleanDCentry_110	$reg_number
 ENDIF
 IF :DEF: XSCALE
	WRCACHE_CleanDCentry_XSCALE	$reg_number
 ENDIF
	MEND

;Coprocessor cache control 
;Clean + Flush DCache entry
;
	MACRO 
	WRCACHE_Clean_FlushDCentry	$reg_number
 IF :LNOT: :DEF: HAL_HAS_CACHE
	NO_WRCACHE_Clean_FlushDCentry	$reg_number
 ENDIF
 IF :DEF: ARM720T
	WRCACHE_Clean_FlushDCentry_720T	$reg_number
 ENDIF
 IF :DEF: ARM740T
	WRCACHE_Clean_FlushDCentry_740T	$reg_number
 ENDIF
 IF :DEF: ARM922
	WRCACHE_Clean_FlushDCentry_920T	$reg_number
 ENDIF
 IF :DEF: ARM940T
	WRCACHE_Clean_FlushDCentry_940T	$reg_number
 ENDIF
 IF :DEF: ARM946T
	WRCACHE_Clean_FlushDCentry_946T	$reg_number
 ENDIF
 IF :DEF: ARM1020T
	WRCACHE_Clean_FlushDCentry_1020T	$reg_number
 ENDIF
 IF :DEF: SA110
	WRCACHE_Clean_FlushDCentry_110	$reg_number
 ENDIF
 IF :DEF: XSCALE
	WRCACHE_Clean_FlushDCentry_XSCALE	$reg_number
 ENDIF
	MEND

;Drain Write Buffer.
;
	MACRO
	WRCACHE_DrainWriteBuffer	$reg_number
 IF :LNOT: :DEF: HAL_HAS_WBUFFER
	NO_WRCACHE_DrainWriteBuffer	$reg_number
 ENDIF
 IF :DEF: ARM720T
	WRCACHE_DrainWriteBuffer_720T	$reg_number
 ENDIF
 IF :DEF: ARM740T
	WRCACHE_DrainWriteBuffer_740T	$reg_number
 ENDIF
 IF :DEF: ARM922
	WRCACHE_DrainWriteBuffer_920T	$reg_number
 ENDIF
 IF :DEF: ARM940T
	WRCACHE_DrainWriteBuffer_940T	$reg_number
 ENDIF
 IF :DEF: ARM946T
	WRCACHE_DrainWriteBuffer_946T	$reg_number
 ENDIF
 IF :DEF: ARM1020T
	WRCACHE_DrainWriteBuffer_1020T	$reg_number
 ENDIF
 IF :DEF: SA110
	WRCACHE_DrainWriteBuffer_110	$reg_number
 ENDIF
 IF :DEF: XSCALE
	WRCACHE_DrainWriteBuffer_XSCALE	$reg_number
 ENDIF
	MEND

;Clean DCache (only) from address in $reg1 to (excl) addr in $reg2
;
	MACRO
	WRCACHE_CleanDrange	$reg1, $reg2
 IF :LNOT: :DEF: HAL_HAS_CACHE
	NO_WRCACHE_CleanDrange	$reg1, $reg2
 ENDIF
 IF :DEF: ARM720T
	WRCACHE_CleanDrange_720T	$reg1, $reg2
 ENDIF
 IF :DEF: ARM740T
	WRCACHE_CleanDrange_740T	$reg1, $reg2
 ENDIF
 IF :DEF: ARM922
	WRCACHE_CleanDrange_920T	$reg1, $reg2
 ENDIF
 IF :DEF: ARM940T
	WRCACHE_CleanDrange_940T	$reg1, $reg2
 ENDIF
 IF :DEF: ARM946T
	WRCACHE_CleanDrange_946T	$reg1, $reg2
 ENDIF
 IF :DEF: ARM1020T
	WRCACHE_CleanDrange_1020T	$reg1, $reg2
 ENDIF
 IF :DEF: SA110
	WRCACHE_CleanDrange_110	$reg1, $reg2
 ENDIF
 IF :DEF: XSCALE
	WRCACHE_CleanDrange_XSCALE	$reg1, $reg2
 ENDIF
	MEND

;Clean all DCache 
;
	MACRO
	WRCACHE_CleanDCache	$w1, $w2, $w3, $w4, $w5, $w6
 IF :LNOT: :DEF: HAL_HAS_CACHE
	NO_WRCACHE_CleanDCache	$w1, $w2, $w3, $w4, $w5, $w6
 ENDIF
 IF :DEF: ARM720T
	WRCACHE_CleanDCache_720T	$w1, $w2, $w3, $w4, $w5, $w6
 ENDIF
 IF :DEF: ARM740T
	WRCACHE_CleanDCache_740T	$w1, $w2, $w3, $w4, $w5, $w6
 ENDIF
 IF :DEF: ARM922
	WRCACHE_CleanDCache_920T	$w1, $w2, $w3, $w4, $w5, $w6
 ENDIF
 IF :DEF: ARM940T
	WRCACHE_CleanDCache_940T	$w1, $w2, $w3, $w4, $w5, $w6
 ENDIF
 IF :DEF: ARM946T
	WRCACHE_CleanDCache_946T	$w1, $w2, $w3, $w4, $w5, $w6
 ENDIF
 IF :DEF: ARM1020T
	WRCACHE_CleanDCache_1020T	$w1, $w2, $w3, $w4, $w5, $w6
 ENDIF
 IF :DEF: SA110
	WRCACHE_CleanDCache_110	$w1, $w2, $w3, $w4, $w5, $w6
 ENDIF
 IF :DEF: XSCALE
	WRCACHE_CleanDCache_XSCALE	$w1, $w2, $w3, $w4, $w5, $w6
 ENDIF
	MEND

;------------------------------------------------------------------
;Coprocessor test/clock/idle control 
;Enable Clock Switching
;
	MACRO
	WRCLK_EnableClockSW	$reg_number
	NO_WRCLK_EnableClockSW	$reg_number
 IF :DEF: ARM922
	WRCLK_EnableClockSW_920T	$reg_number
 ENDIF
 IF :DEF: ARM940T
	WRCLK_EnableClockSW_940T	$reg_number
 ENDIF
 IF :DEF: ARM946T
	WRCLK_EnableClockSW_946T	$reg_number
 ENDIF
 IF :DEF: SA110
	WRCLK_EnableClockSW_110	$reg_number
 ENDIF
 IF :DEF: XSCALE
	WRCLK_EnableClockSW_XSCALE	$reg_number
 ENDIF
	MEND

;Coprocessor test/clock/idle control 
;Disable Clock Switching
;
	MACRO
	WRCLK_DisableClockSW	$reg_number
	NO_WRCLK_DisableClockSW	$reg_number
 IF :DEF: ARM922
	WRCLK_DisableClockSW_920T	$reg_number
 ENDIF
 IF :DEF: ARM940T
	WRCLK_DisableClockSW_940T	$reg_number
 ENDIF
 IF :DEF: ARM946T
	WRCLK_DisableClockSW_946T	$reg_number
 ENDIF
 IF :DEF: SA110
	WRCLK_DisableClockSW_110	$reg_number
 ENDIF
 IF :DEF: XSCALE
	WRCLK_DisableClockSW_XSCALE	$reg_number
 ENDIF
	MEND

;Coprocessor test/clock/idle control 
;Disable nMCLK output
;
	MACRO
	WRCLK_DisablenMCLK	$reg_number
	NO_WRCLK_DisablenMCLK	$reg_number
 IF :DEF: ARM922
	WRCLK_DisablenMCLK_920T	$reg_number
 ENDIF
 IF :DEF: SA110
	WRCLK_DisablenMCLK_110	$reg_number
 ENDIF
 IF :DEF: XSCALE
	WRCLK_DisablenMCLK_XSCALE	$reg_number
 ENDIF
	MEND

;Coprocessor test/clock/idle control 
;Wait for Interrupt
;
	MACRO
	WRTEST_WaitInt	$reg_number
	NO_WRTEST_WaitInt	$reg_number
 IF :DEF: ARM720T
	WRTEST_WaitInt_720T	$reg_number
 ENDIF
 IF :DEF: ARM740T
	WRTEST_WaitInt_740T	$reg_number
 ENDIF
 IF :DEF: ARM922
	WRTEST_WaitInt_920T	$reg_number
 ENDIF
 IF :DEF: ARM940T
	WRTEST_WaitInt_940T	$reg_number
 ENDIF
 IF :DEF: ARM946T
	WRTEST_WaitInt_946T	$reg_number
 ENDIF
 IF :DEF: ARM1020T
	WRTEST_WaitInt_1020T	$reg_number
 ENDIF
 IF :DEF: SA110
	WRTEST_WaitInt_110	$reg_number
 ENDIF
 IF :DEF: XSCALE
	WRTEST_WaitInt_XSCALE	$reg_number
 ENDIF
	MEND

;-----------------------------------------------------------
; MPU setup macro and variables
;

	MACRO
	SET_MPU_REGION	$num, $address, $size, $access
 IF :LNOT: :DEF: HAL_HAS_MPU
	NO_SET_MPU_REGION	$num, $address, $size, $access
 ENDIF
 IF :DEF: ARM740T
	SET_MPU_REGION_740T	$num, $address, $size, $access
 ENDIF
 IF :DEF: ARM940T
	SET_MPU_REGION_940T	$num, $address, $size, $access
 ENDIF
 IF :DEF: ARM946T
	SET_MPU_REGION_946T	$num, $address, $size, $access
 ENDIF
	MEND

 ENDIF
	END