fa520.c

FIC8120方案的 StartCell_Driver

/***************************************************************************
* Copyright  Faraday Technology Corp 2002-2003.  All rights reserved.      *
*--------------------------------------------------------------------------*
* Name:fa510.c                                                             *
* Description: FA520_FA520_CPU Cache and mmu library routine                           *
* Author: Fred Chien                                                       *
****************************************************************************/

#include "flib.h"
#include "fa520.h"

// When SDRAM size = 256MB, TLB address = 0x07000000
char *MMUTableStr = 
/* table generated to this base address */
"BASE_ADDRESS    0x03000000\n"

/* MMU Level 1 Table generation data */
"LEVEL 1\n"
/* section */
"VIRTUAL 0x00000000 TO 0x07ffffff PHYSICAL 0x00000000 DOMAIN 0 SECTION FULL_ACCESS CACHEABLE AND BUFFERABLE\n"
"VIRTUAL 0x08000000 TO 0xffffffff PHYSICAL 0x08000000 DOMAIN 0 SECTION FULL_ACCESS NOT CACHEABLE AND NOT BUFFERABLE\n"
"\n";


//read FA520_FA520_CPU ID

UINT32 FA520_CPUReadIDReg(void)
{
 UINT32 IdReg;
	__asm
 	{
 	MRC	p15,0,IdReg,c0,c0,0	
 	}	

 	return(IdReg);	
}   
   

UINT32 FA520_CPUReadVendorID(void)
{
 UINT32 IdReg,VendorID;
 
 	IdReg = FA520_CPUReadIDReg();
 	VendorID = (IdReg >>24) & 0xff;
 
 	return(VendorID);	
}	   
   
   
UINT32 FA520_CPUReadArchID(void)
{
 UINT32 IdReg,ArchID;
 
 	IdReg=FA520_CPUReadIDReg();
 	ArchID=(IdReg >>16)&0xff;
 
 	return(ArchID);	
}	   
   
UINT32 FA520_CPUReadPartNum(void)
{
 UINT32 IdReg,PartNum;
 
 	IdReg=FA520_CPUReadIDReg();
 	PartNum=(IdReg >>4)&0xfff;
 	
 	return(PartNum);	
}	   
     
UINT32 FA520_CPUReadVersion(void)
{
 UINT32 IdReg,Version;
 
 	IdReg=FA520_CPUReadIDReg();
 	Version=IdReg & 0xf;
 
 	return(Version);	
}	   
        

//read cache type register

UINT32 FA520_CPUReadCTR(void)
{
UINT32 CtrReg;

 	__asm
 	{
  	MRC	p15,0,CtrReg,c0,c0,1	
 	}	

 	return(CtrReg);			
}

UINT32 FA520_CPUGetICacheLineLength(void)
{	
	CP15CTRRegStruct ctr;
	
	*((UINT32 *)&ctr) = FA520_CPUReadCTR();
	return CPU_CACHE_LINE_LEN(ctr.ILEN);
}

UINT32 FA520_CPUGetDCacheLineLength(void)
{	
	CP15CTRRegStruct ctr;
	
	*((UINT32 *)&ctr) = FA520_CPUReadCTR();
	return CPU_CACHE_LINE_LEN(ctr.DLEN);
}

UINT32 FA520_CPUReadCFG(void)
{
UINT32 CfgReg;

 	__asm
 	{
  	MRC	p15,0,CfgReg,c1,c0,0	
 	}	

	return(CfgReg);			
}



//Configuration Register Operation

void FA520_CPUSetVectorBase(UINT32 VectBase)
{
 UINT32 tmp;
 
 	VectBase=(VectBase << CP15_CFG_VECT_BASE_BIT) & CP15_CFG_VECT_BASE_MASK;
 	
 	__asm
 	{
   	MRC 	p15,0,tmp,c1,c0,0
   	ORR  tmp,tmp,VectBase
   	MCR  p15,0,tmp,c1,c0,0
  	}	
}
        
   
void FA520_CPUSetICacheEnable(UINT32 enable)
{
 UINT32 tmp; 
 
 	__asm
 	{
   	MRC 	p15,0,tmp,c1,c0,0
   	CMP  enable,#0   
   	ORRNE  tmp,tmp,#CP15_CFG_ICACHE_EN_MASK
   	BICEQ    tmp,tmp,#CP15_CFG_ICACHE_EN_MASK
   	MCR  p15,0,tmp,c1,c0,0
  	}
}
              
              
void FA520_CPUSetBTBEnable(UINT32 enable)
{
 UINT32 tmp;

 	__asm
 	{
   	MRC 	p15,0,tmp,c1,c0,0
   	CMP  enable,#0   
   	ORRNE  tmp,tmp,#CP15_CFG_BTB_EN_MASK
   	BICEQ  tmp,tmp,#CP15_CFG_BTB_EN_MASK
  	MCR  p15,0,tmp,c1,c0,0
  	} 	
}              
              
              
              
void FA520_CPUSetBigEndianEnable(UINT32 enable)
{
 UINT32 tmp;
 
 	__asm
 	{
   	MRC 	p15,0,tmp,c1,c0,0
   	CMP  enable,#0   
   	ORRNE  tmp,tmp,#CP15_CFG_BIGENDIAN_EN_MASK
   	BICEQ  tmp,tmp,#CP15_CFG_BIGENDIAN_EN_MASK
   	MCR  p15,0,tmp,c1,c0,0
  	}	
}              



void FA520_CPUSetWriteBufEnable(UINT32 enable)
{
 UINT32 tmp;
  
 	__asm
 	{
   	MRC 	p15,0,tmp,c1,c0,0
   	CMP  enable,#0   
   	ORRNE  tmp,tmp,#CP15_CFG_WRITEBUF_EN_MASK
   	BICEQ  tmp,tmp,#CP15_CFG_WRITEBUF_EN_MASK   
   	MCR  p15,0,tmp,c1,c0,0
  	}
}


void FA520_CPUSetDCacheEnable(UINT32 enable)
{
 UINT32 tmp; 

 	__asm
 	{
   	MRC    p15,0,tmp,c1,c0,0
   	CMP    enable,#0   
   	ORRNE  tmp,tmp,#CP15_CFG_DCACHE_EN_MASK
   	BICEQ  tmp,tmp,#CP15_CFG_DCACHE_EN_MASK
   	
   	//clean cache 
   	MCR    p15,0,tmp,c7,c10,0		
   	
   	MCR    p15,0,tmp,c1,c0,0
  	}
}


void FA520_CPUSetAlignCheckEnable(UINT32 enable)
{
 UINT32 tmp;
  
 	__asm
 	{
   	MRC 	p15,0,tmp,c1,c0,0
  	CMP  enable,#0   
   	ORRNE  tmp,tmp,#CP15_CFG_ALIGN_EN_MASK
   	BICEQ  tmp,tmp,#CP15_CFG_ALIGN_EN_MASK
   	MCR  p15,0,tmp,c1,c0,0
  	}	
}

void FA520_CPUSetTLBBaseAddr(UINT32 addr)
{
 	__asm
 	{
   	MCR 	p15,0,addr,c2,c0,0
  	}	
}

void FA520_CPUSetDomainAccessCtrl(UINT32 domain, UINT32 ctrl)
{
	UINT32 reg, temp;
	
	__asm
 	{
 	mov		temp, #0x3
 	mov		temp, temp, lsl domain
 	mvn		temp, temp
   	MRC 	p15,0,reg,c3,c0,0
   	and		reg, reg,temp
   	mov		ctrl, ctrl, lsl domain
   	orr		reg, reg, ctrl
   	MCR 	p15,0,reg,c3,c0,0
  	}
}

void FA520_CPUSetMMUEnable(UINT32 enable)
{
 UINT32 tmp;
  
 	__asm
 	{
   	MRC 	p15,0,tmp,c1,c0,0
   	CMP  enable,#0   
   	ORRNE  tmp,tmp,#CP15_CFG_MMU_EN_MASK
   	BICEQ  tmp,tmp,#CP15_CFG_MMU_EN_MASK
   	MCR  p15,0,tmp,c1,c0,0
  	}	
}


UINT8 FA520_CPUCheckMMUEnable(void)
{
 UINT8 tmp;
 
 	__asm
 	{
    MRC 	p15,0,tmp,c1,c0,0
 	}   
 	if(tmp&CP15_CFG_MMU_EN_MASK)
 		return TRUE;
 	else
 		return FALSE;
}


UINT8 FA520_CPUCheckDCacheEnable(void)
{
 UINT8 tmp;
 
 	__asm
 	{
    MRC 	p15,0,tmp,c1,c0,0
 	}   
 	if(tmp&CP15_CFG_DCACHE_EN_MASK)
 		return TRUE;
 	else
 		return FALSE;
}



UINT8 FA520_CPUCheckICacheEnable(void)
{
 UINT8 tmp;
 
 	__asm
 	{
    MRC 	p15,0,tmp,c1,c0,0
 	}   
 
 	if(tmp&CP15_CFG_ICACHE_EN_MASK)
 		return TRUE;
 	else
 		return FALSE;
}


UINT8 FA520_CPUCheckWriteBufEnable(void)
{
 UINT8 tmp;
 
 	__asm
 	{
    MRC 	p15,0,tmp,c1,c0,0
 	}   
 	if(tmp&CP15_CFG_WRITEBUF_EN_MASK)
 		return TRUE;
 	else
 		return FALSE;
}


UINT8 FA520_CPUCheckBTBEnable(void)
{
 UINT8 tmp;
 
 	__asm
 	{
    MRC 	p15,0,tmp,c1,c0,0
 	}   
 	if(tmp&CP15_CFG_BTB_EN_MASK)
 		return TRUE;
 	else
 		return FALSE;
}


void FA520_CPUReset(void)
{
UINT32 tmp;

	tmp=2;
	
	__asm
	{
	MCR p8,0,tmp,c1,c0,0
	}
}


void FA520_DeviceReset(void)
{
UINT32 tmp;

	tmp=1;
	__asm
	{
	MCR p8,0,tmp,c1,c0,0
	}
} 


//write buffer operation

void FA520_CPUDrainWriteBuffer(void)
{
 UINT32 tmp;
   tmp = 0;
   
   __asm
   {
    MCR		p15,0,tmp,c7,c10,4
   }
}
  
//#ifdef FA510
//Branch target buffer operation
  
void FA520_CPUFlushBTBAll(void)
{
 UINT32 tmp;
   tmp = 0;
   
   __asm
   {
    MCR		p15,0,tmp,c7,c2,0
   }
}		
//#endif

//Instruction scratchpad RAM operation

void FA520_CPUFlushISpadAll(void)
{
 UINT32 tmp;
   tmp = 0;
   
   __asm
   {
    MCR		p15,0,tmp,c7,c2,1
   }
} 
  
//D-Cache operation

void FA520_CPUInvalidateDCacheAll(void)
{
 UINT32 tmp;
   tmp = 0;
   
	__asm
	{
	 MCR	p15, 0, tmp, c7, c6,0
	 }
}

void FA520_CPUInvalidateDCache(UINT32 addr)
{
	__asm
	{
	 MCR	p15, 0, addr, c7, c6, 1
	 }
}


void FA520_CPUCleanDCacheAll(void)
{
 UINT32 tmp;
   tmp = 0;
   
	__asm
	{
	 MCR 	p15,0,tmp,c7,c10,0
	}
}


void FA520_CPUCleanDCache(UINT32 addr)
{
	__asm
	{
	 MCR 	p15,0,addr,c7,c10,1
	}
}


void FA520_CPUCleanInvalidateDCache(UINT32 addr)
{
	__asm
	{
	MCR	p15,0,addr,c7,c14,1
	}
}


//I-Cache operation 

void FA520_CPUInvalidateICacheAll(void)
{
 UINT32 tmp;
   tmp = 0;

 	__asm
    {
	 MCR p15, 0, tmp, c7, c0, 0
	 }	        
}

void FA520_CPUInvalidateICache(UINT32 addr)
{
 	__asm
	{
	 MCR p15, 0, addr, c7, c0, 1
	 }
}

void FA520_CPUPrefetchICache(UINT32 addr)
{
	__asm
	{
	 MCR	p15, 0, addr, c7, c13,1
	 }
}



void FA520_CPULockDCache(void)
{
  UINT32 tmp;
  
	__asm
	{
     MOV    tmp,#0
	 ORR    tmp,tmp,#0x80000000	
	 MCR	p15, 0, tmp, c9, c0, 0
	}
}

void FA520_CPUUnlockDCache(void)
{
 UINT32 tmp;
   tmp = 0;
   
	__asm
	{
	MCR	p15, 0, tmp, c9, c0, 0
	}
}

void FA520_CPULockICache(void)
{
  UINT32 tmp;
  
	__asm
	{
	 MOV    tmp,#0
	 ORR    tmp,tmp,#0x80000000	 
	 MCR	p15, 0, tmp, c9, c0, 1
	 }
}

void FA520_CPUUnlockICache(void)
{
 UINT32 tmp;
   tmp = 0;
   
	__asm
	{
	 MCR	p15, 0, tmp, c9, c0, 1
	 }
}

 


void FA520_CPUSetExtEnable(UINT32 enable)
{

UINT32 tmp;
 
 	__asm
 	{
   	MRC 	p15,0,tmp,c14,c0,0
   	CMP  enable,#0   
   	ORRNE  tmp,tmp,#CP15_EXT_ECE_EN_MASK
   	BICEQ  tmp,tmp,#CP15_EXT_ECE_EN_MASK
   	MCR  p15,0,tmp,c14,c0,0
  	}	
}

void FA520_EnterIdleMode()
{
	__asm
	{
		mov	 r0, #0x0
  		MCR  p15,0,r0,c7,c8,2   //enter idle mode 
 	}
}

void FA520_EnterSleepMode()
{
	__asm
	{
		mov	 r0, #0x0
  		MCR  p15,0,r0,c7,c0,4   //enter sleep mode 
 	}
}

void FA520_EnterPowerSaving(UINT32 mode)
{
	if(mode== IDLE)
		EnterIdleMode();
	else
		EnterSleepMode();
}

void FLib_FA520InitMMU()
{
	UINT32 mmu_address;
	
	if(mmugen(&mmu_address, MMUTableStr))
	{
		FA520_CPUSetTLBBaseAddr(mmu_address);
		FA520_CPUSetDomainAccessCtrl(0, 1);
		FA520_CPUSetICacheEnable(ENABLE);
		FA520_CPUSetDCacheEnable(ENABLE);
		FA520_CPUSetMMUEnable(ENABLE);	
	}
}