fa520.h

FIC8120方案的 StartCell_Driver

/***************************************************************************
* Copyright  Faraday Technology Corp 2002-2003.  All rights reserved.      *
*--------------------------------------------------------------------------*
* Name:fa510.h                                                             *
* Description: CPU Cache and mmu library define                            *
* Author: Fred Chien                                                       *
****************************************************************************/

#include "fa510.h"

#define DISABLE			0
#define ENABLE			1

#define UNCACHEABLE		0
#define CACHEABLE		1

#define UNBUFFERABLE	0
#define BUFFERABLE		1

//protection mode
#define NO_ACCESS		0x0
#define PRIV_ONLY		0x1
#define USER_RONLY		0x2
#define RW_ALL			0x3	


#define CP15_IPR_DPR_ACCESS_RIGHT_BITS		2


/* region base/size register */
#define CP15_RBS_MEM_REGION_SIZE_LOC		1
#define CP15_RBS_MEM_REGION_ENABLE			0x00000001
#define CP15_RBS_MEM_REGION_SIZE_BITS		0x0000003E
#define CP15_RBS_MEM_REGION_BASE_BITS		0xFFFFF000


#define MEM_REGION_4K						0x0B
#define MEM_REGION_8K						0x0C
#define MEM_REGION_16K						0x0D
#define MEM_REGION_32K						0x0E
#define MEM_REGION_64K						0x0F
#define MEM_REGION_128K						0x10
#define MEM_REGION_256K						0x11
#define MEM_REGION_512K						0x12
#define MEM_REGION_1M						0x13
#define MEM_REGION_2M						0x14
#define MEM_REGION_4M						0x15
#define MEM_REGION_8M						0x16
#define MEM_REGION_16M						0x17
#define MEM_REGION_32M						0x18
#define MEM_REGION_64M						0x19
#define MEM_REGION_128M						0x1A
#define MEM_REGION_256M						0x1B
#define MEM_REGION_512M						0x1C
#define MEM_REGION_1G						0x1D
#define MEM_REGION_2G						0x1E
#define MEM_REGION_4G						0x1F

#define CP15_EXT_ECE_EN_BIT			0
#define CP15_EXT_PDMS_EN_BIT		1


#define CP15_CFG_MMU_EN_BIT			0
#define CP15_CFG_ALIGN_EN_BIT		1
#define CP15_CFG_DCACHE_EN_BIT		2
#define CP15_CFG_WRITEBUF_EN_BIT	3
#define CP15_CFG_BIGENDIAN_EN_BIT	7
#define CP15_CFG_BTB_EN_BIT			11
#define CP15_CFG_ICACHE_EN_BIT		12
#define CP15_CFG_VECT_BASE_BIT		13


#define CP15_EXT_ECE_EN_MASK		(1<<CP15_EXT_ECE_EN_BIT)
#define CP15_EXT_PDMS_EN_MASK		(1<<CP15_EXT_PDMS_EN_BIT)


#define CP15_CFG_MMU_EN_MASK		(1<<CP15_CFG_MMU_EN_BIT)
#define CP15_CFG_ALIGN_EN_MASK		(1<<CP15_CFG_ALIGN_EN_BIT)
#define CP15_CFG_DCACHE_EN_MASK		(1<<CP15_CFG_DCACHE_EN_BIT)
#define CP15_CFG_WRITEBUF_EN_MASK	(1<<CP15_CFG_WRITEBUF_EN_BIT)
#define CP15_CFG_BIGENDIAN_EN_MASK	(1<<CP15_CFG_BIGENDIAN_EN_BIT)
#define CP15_CFG_BTB_EN_MASK		(1<<CP15_CFG_BTB_EN_BIT)
#define CP15_CFG_ICACHE_EN_MASK		(1<<CP15_CFG_ICACHE_EN_BIT) 
#define CP15_CFG_VECT_BASE_MASK		(1<<CP15_CFG_VECT_BASE_BIT)

/* CP15 CTR register */
typedef struct
{
	UINT32 ILEN:2;
	UINT32 Reserved0:1;
	UINT32 IASS:3;
	UINT32 ISize:3;
	UINT32 Reserved1:3;
	
	UINT32 DLEN:2;
	UINT32 Reserved2:1;
	UINT32 DASS:3;
	UINT32 DSize:3;
	UINT32 Reserved3:11;
}CP15CTRRegStruct;

#define CPU_CACHE_LINE_LEN(x)	((1 << (x + 1)) * 4) /* byte size */
#define CPU_CACHE_ASS(x)		(1 << (x + 1))
#define CPU_CACHE_SIZE(x)		(512 * (1 << x))

//power saving
#define  ECE_EN			1
#define  IDLE			0
#define  SLEEP          1

//scratch pad size
#define  SCR_1K			0x8
#define  SCR_2K         0x9
#define  SCR_4K         0xA  



//external routine
extern UINT32 FA520_CPUReadIDReg(void);
extern UINT32 FA520_CPUReadCTR(void);
extern UINT32 FA520_CPUGetICacheLineLength(void);
extern UINT32 FA520_CPUGetDCacheLineLength(void);

extern UINT32 FA520_CPUReadCFG(void);
extern void FA520_CPUInvalidateICacheAll(void);
extern void FA520_CPUInvalidateICache(UINT32 addr);
extern void FA520_CPUPrefetchICache(UINT32 addr);
extern void FA520_CPULockICache(void);
extern void FA520_CPUUnlockICache(void);
extern void FA520_CPUInvalidateDCacheAll(void);
extern void FA520_CPUInvalidateDCache(UINT32 addr);
extern void FA520_CPUCleanDCacheAll(void);
extern void FA520_CPUCleanDCache(UINT32 addr);
extern void FA520_CPUCleanInvalidateDCache(UINT32 addr);
extern void FA520_CPULockDCache(void);
extern void FA520_CPUUnlockDCache(void);
extern void FA520_CPUDrainWriteBuffer(void);
extern void FA520_CPUFlushBTBAll(void);
extern void FA520_CPUFlushISpadAll(void);
extern UINT32 FA520_CPUReadVendorID(void);

extern UINT32 FA520_CPUReadPartNum(void);     
extern UINT32 FA520_CPUReadVersion(void);
extern void FA520_CPUSetVectorBase(UINT32 VectBase);
extern void FA520_CPUSetICacheEnable(UINT32 enable);
extern void FA520_CPUSetBTBEnable(UINT32 enable);
extern void FA520_CPUSetBigEndianEnable(UINT32 enable);
extern void FA520_CPUSetWriteBufEnable(UINT32 enable);
extern void FA520_CPUSetDCacheEnable(UINT32 enable);
extern void FA520_CPUSetAlignCheckEnable(UINT32 enable);
extern void FA520_CPUSetMMUEnable(UINT32 enable);
extern void FA520_CPUSetExtEnable(UINT32 enable);
extern UINT8 FA520_CPUCheckMMUEnable(void);
extern UINT8 FA520_CPUCheckDCacheEnable(void);
extern UINT8 FA520_CPUCheckICacheEnable(void);
extern UINT8 FA520_CPUCheckWriteBufEnable(void);
extern UINT8 FA520_CPUCheckBTBEnable(void);
extern void FA520_EnterPowerSaving(UINT32 mode);
extern void FA520_CPUReset(void); 
extern void FA520_DeviceReset(void);
extern int mmugen(unsigned long *mmu_addr, char *mmutab_str);
extern void FLib_FA520InitMMU(void);