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📄 fa510_old.c

📁 FIC8120方案的 StartCell_Driver
💻 C
字号:
🔍 
/***************************************************************************
* Copyright  Faraday Technology Corp 2002-2003.  All rights reserved.      *
*--------------------------------------------------------------------------*
* Name:fa510.c                                                             *
* Description: CPU Cache and mmu library routine                           *
* Author: Fred Chien                                                       *
****************************************************************************/

#include "flib.h"
#include "fa510.h"


  
//read CPU ID

UINT32 CPUReadIDReg(void)
{
 UINT32 IdReg;
	__asm
 	{
 	MRC	p15,0,IdReg,c0,c0,0	
 	}	

 	return(IdReg);	
}   
   

UINT32 CPUReadVendorID(void)
{
 UINT32 IdReg,VendorID;
 
 	IdReg = CPUReadIDReg();
 	VendorID = (IdReg >>24) & 0xff;
 
 	return(VendorID);	
}	   
   
   
UINT32 CPUReadArchID(void)
{
 UINT32 IdReg,ArchID;
 
 	IdReg=CPUReadIDReg();
 	ArchID=(IdReg >>16)&0xff;
 
 	return(ArchID);	
}	   
   
UINT32 CPUReadPartNum(void)
{
 UINT32 IdReg,PartNum;
 
 	IdReg=CPUReadIDReg();
 	PartNum=(IdReg >>4)&0xfff;
 	
 	return(PartNum);	
}	   
     
UINT32 CPUReadVersion(void)
{
 UINT32 IdReg,Version;
 
 	IdReg=CPUReadIDReg();
 	Version=IdReg & 0xf;
 
 	return(Version);	
}	   
        

//read cache type register

UINT32 CPUReadCTR(void)
{
UINT32 CtrReg;

 	__asm
 	{
  	MRC	p15,0,CtrReg,c0,c0,1	
 	}	

 	return(CtrReg);			
}


UINT32 CPUReadCFG(void)
{
UINT32 CfgReg;

 	__asm
 	{
  	MRC	p15,0,CfgReg,c1,c0,0	
 	}	

	return(CfgReg);			
}



//Configuration Register Operation

void CPUSetVectorBase(UINT32 VectBase)
{
 UINT32 tmp;
 
 	VectBase=(VectBase << CP15_CFG_VECT_BASE_BIT) & CP15_CFG_VECT_BASE_MASK;
 	
 	__asm
 	{
   	MRC 	p15,0,tmp,c1,c0,0
   	ORR  tmp,tmp,VectBase
   	MCR  p15,0,tmp,c1,c0,0
  	}	
}
        
   
void CPUSetICacheEnable(UINT32 enable)
{
 UINT32 tmp; 
 
 	__asm
 	{
   	MRC 	p15,0,tmp,c1,c0,0
   	CMP  enable,#0   
   	ORRNE  tmp,tmp,#CP15_CFG_ICACHE_EN_MASK
   	BICEQ    tmp,tmp,#CP15_CFG_ICACHE_EN_MASK
   	MCR  p15,0,tmp,c1,c0,0
  	}
}
              
              
void CPUSetBTBEnable(UINT32 enable)
{
 UINT32 tmp;

 	__asm
 	{
   	MRC 	p15,0,tmp,c1,c0,0
   	CMP  enable,#0   
   	ORRNE  tmp,tmp,#CP15_CFG_BTB_EN_MASK
   	BICEQ  tmp,tmp,#CP15_CFG_BTB_EN_MASK
  	MCR  p15,0,tmp,c1,c0,0
  	} 	
}              
              
              
              
void CPUSetBigEndianEnable(UINT32 enable)
{
 UINT32 tmp;
 
 	__asm
 	{
   	MRC 	p15,0,tmp,c1,c0,0
   	CMP  enable,#0   
   	ORRNE  tmp,tmp,#CP15_CFG_BIGENDIAN_EN_MASK
   	BICEQ  tmp,tmp,#CP15_CFG_BIGENDIAN_EN_MASK
   	MCR  p15,0,tmp,c1,c0,0
  	}	
}              



void CPUSetWriteBufEnable(UINT32 enable)
{
 UINT32 tmp;
  
 	__asm
 	{
   	MRC 	p15,0,tmp,c1,c0,0
   	CMP  enable,#0   
   	ORRNE  tmp,tmp,#CP15_CFG_WRITEBUF_EN_MASK
   	BICEQ  tmp,tmp,#CP15_CFG_WRITEBUF_EN_MASK   
   	
   	//drain
   	MCR	 p15,0,tmp,c7,c10,4
   	   	
   	MCR  p15,0,tmp,c1,c0,0
  	}
}


void CPUSetDCacheEnable(UINT32 enable)
{
 UINT32 tmp; 

 	__asm
 	{
   	MRC    p15,0,tmp,c1,c0,0
   	CMP    enable,#0   
   	ORRNE  tmp,tmp,#CP15_CFG_DCACHE_EN_MASK
   	BICEQ  tmp,tmp,#CP15_CFG_DCACHE_EN_MASK
   	
   	//clean cache 
   	MCR    p15,0,tmp,c7,c10,0		
   	
   	MCR    p15,0,tmp,c1,c0,0
  	}
}


void CPUSetAlignCheckEnable(UINT32 enable)
{
 UINT32 tmp;
  
 	__asm
 	{
   	MRC 	p15,0,tmp,c1,c0,0
  	CMP  enable,#0   
   	ORRNE  tmp,tmp,#CP15_CFG_ALIGN_EN_MASK
   	BICEQ  tmp,tmp,#CP15_CFG_ALIGN_EN_MASK
   	MCR  p15,0,tmp,c1,c0,0
  	}	
}


void CPUSetMMUEnable(UINT32 enable)
{
 UINT32 tmp;
  
 	__asm
 	{
   	MRC 	p15,0,tmp,c1,c0,0
   	CMP  enable,#0   
   	ORRNE  tmp,tmp,#CP15_CFG_MMU_EN_MASK
   	BICEQ  tmp,tmp,#CP15_CFG_MMU_EN_MASK
   	MCR  p15,0,tmp,c1,c0,0
  	}	
}


UINT8 CPUCheckMMUEnable(void)
{
 UINT8 tmp;
 
 	__asm
 	{
    MRC 	p15,0,tmp,c1,c0,0
 	}   
 	if(tmp&CP15_CFG_MMU_EN_MASK)
 		return TRUE;
 	else
 		return FALSE;
}


UINT8 CPUCheckDCacheEnable(void)
{
 UINT8 tmp;
 
 	__asm
 	{
    MRC 	p15,0,tmp,c1,c0,0
 	}   
 	if(tmp&CP15_CFG_DCACHE_EN_MASK)
 		return TRUE;
 	else
 		return FALSE;
}



UINT8 CPUCheckICacheEnable(void)
{
 UINT8 tmp;
 
 	__asm
 	{
    MRC 	p15,0,tmp,c1,c0,0
 	}   
 
 	if(tmp&CP15_CFG_ICACHE_EN_MASK)
 		return TRUE;
 	else
 		return FALSE;
}


UINT8 CPUCheckWriteBufEnable(void)
{
 UINT8 tmp;
 
 	__asm
 	{
    MRC 	p15,0,tmp,c1,c0,0
 	}   
 	if(tmp&CP15_CFG_WRITEBUF_EN_MASK)
 		return TRUE;
 	else
 		return FALSE;
}


UINT8 CPUCheckBTBEnable(void)
{
 UINT8 tmp;
 
 	__asm
 	{
    MRC 	p15,0,tmp,c1,c0,0
 	}   
 	if(tmp&CP15_CFG_BTB_EN_MASK)
 		return TRUE;
 	else
 		return FALSE;
}


void CPUReset(void)
{
UINT32 tmp;

	tmp=2;
	
	__asm
	{
	MCR p8,0,tmp,c1,c0,0
	}
}


void DeviceReset(void)
{
UINT32 tmp;

	tmp=1;
	__asm
	{
	MCR p8,0,tmp,c1,c0,0
	}
} 


//D-Cache Control operation

void CPUSetDCacheCacheable(UINT32 region,UINT32 cacheable)
{
 UINT32 tmp,val;
 
  	val=1<<region;
 
  	__asm
 	{	
  	MRC	p15,0,tmp,c2,c0,0
  	CMP   cacheable,#0
  	ORRNE  tmp,tmp,val
  	BICEQ  tmp,tmp,val  
  	MCR   p15,0,tmp,c2,c0,0
  	}
}
 
 	
//I-Cache Control operation

void CPUSetICacheCacheable(UINT32 region,UINT32 cacheable)
{
 UINT32 tmp,val;
 
 	val=1<<region;
 
	__asm
 	{
  	MRC	p15,0,tmp,c2,c0,1
  	CMP   cacheable,#0  
  	ORRNE   tmp,tmp,val
  	BICEQ   tmp,tmp,val
  	MCR   p15,0,tmp,c2,c0,1
  	}
}
 
	
//Write-Buffer Control operation

void CPUSetWriteBufable(UINT32 region,UINT32 bufferable)
{
 UINT32 tmp,val;
 
 	val|=1<<region;
 
 	__asm
 	{
  	MRC	p15,0,tmp,c3,c0,0
  	CMP   bufferable,#0
  	ORRNE   tmp,tmp,val
  	BICEQ   tmp,tmp,val
  	MCR   p15,0,tmp,c3,c0,0
  	}
}
 


//Instruction Region Protection operation
 
UINT32 ReadInstrRegionProtectReg(void)
{
 UINT32 val;	
 
 	__asm
 	{
   	MRC 	p15,0,val,c5,c0,1	
  	}
  
 	return(val);
} 

void WriteInstrRegionProtectReg(UINT32 val)
{
 	__asm
 	{
  	MCR	p15,0,val,c5,c0,1
  	}	
}

 
 //Data Region Protection operation
 
UINT32 ReadDataRegionProtectReg(void)
{
 UINT32 val;	
 
 	__asm
 	{
   	MRC 	p15,0,val,c5,c0,0	
  	}
  
 	return(val);
} 

void WriteDataRegionProtectReg(UINT32 val)
{
 	__asm
 	{
  	MCR	p15,0,val,c5,c0,0
  	}	
}
 
 
void CPUSetDataRegionProtect(UINT32 region,UINT32 mode)
{
 UINT32 tmp;
 
 	tmp=ReadDataRegionProtectReg();
 
 	tmp&=~(3<<(CP15_IPR_DPR_ACCESS_RIGHT_BITS * region));
 	tmp|=mode<<(CP15_IPR_DPR_ACCESS_RIGHT_BITS * region);

 	WriteDataRegionProtectReg(tmp);
	
}
 
 
void CPUSetInstrRegionProtect(UINT32 region,UINT32 mode)
{
 UINT32 tmp;
 
 	tmp=ReadInstrRegionProtectReg();
 
 	tmp&=~(3<<(CP15_IPR_DPR_ACCESS_RIGHT_BITS * region));
 	tmp|=mode<<(CP15_IPR_DPR_ACCESS_RIGHT_BITS * region);

 	WriteInstrRegionProtectReg(tmp);	
}

 
  
 
 //Data Region Base /Size operation
 
UINT32 ReadDataRegionBaseSizeReg(UINT32 Region)
{
	UINT32 val;
	switch(Region)
	{
		case 0:
			__asm{MRC	p15, 0, val, c6, c0, 0}
			break;
		case 1:
			__asm{MRC	p15, 0, val, c6, c1, 0}
			break;
		case 2:
			__asm{MRC	p15, 0, val, c6, c2, 0}
			break;
		case 3:
			__asm{MRC	p15, 0, val, c6, c3, 0}
			break;
		case 4:
			__asm{MRC	p15, 0, val, c6, c4, 0}
			break;
		case 5:
			__asm{MRC	p15, 0, val, c6, c5, 0}
			break;
		case 6:
			__asm{MRC	p15, 0, val, c6, c6, 0}
			break;
		case 7:
			__asm{MRC	p15, 0, val, c6, c7, 0}
			break;
	}
	return val;
}

void WriteDataRegionBaseSizeReg(UINT32 Region, UINT32 val)
{
	switch(Region)
	{
		case 0:
			__asm { MCR	p15, 0, val, c6, c0, 0}
			break;
		case 1:
			__asm { MCR	p15, 0, val, c6, c1, 0}
			break;
		case 2:
			__asm { MCR	p15, 0, val, c6, c2, 0}
			break;
		case 3:
			__asm { MCR	p15, 0, val, c6, c3, 0}
			break;
		case 4:
			__asm { MCR	p15, 0, val, c6, c4, 0}
			break;
		case 5:
			__asm { MCR	p15, 0, val, c6, c5, 0}
			break;
		case 6:
			__asm { MCR	p15, 0, val, c6, c6, 0}
			break;
		case 7:
			__asm { MCR	p15, 0, val, c6, c7, 0}
			break;
	}
}
 


void CPUSetDataRegionBaseSize(UINT32 region,UINT32 addr,UINT32 size,UINT32 enable) 
{
    UINT32 tmp;
 
	addr &= CP15_RBS_MEM_REGION_BASE_BITS;	
	size = (size << CP15_RBS_MEM_REGION_SIZE_LOC)&CP15_RBS_MEM_REGION_SIZE_BITS;;
	enable &=CP15_RBS_MEM_REGION_ENABLE;
	
	tmp = ReadDataRegionBaseSizeReg(region);
	//clear unused bits
	tmp &= ~(CP15_RBS_MEM_REGION_BASE_BITS | CP15_RBS_MEM_REGION_SIZE_BITS);
	tmp |= (addr | size|enable);
	
	WriteDataRegionBaseSizeReg(region,tmp);	
}
	 
 
 
 //Instruction Region Base /Size operation
 
UINT32 ReadInstrRegionBaseSizeReg(UINT32 Region)
{
	UINT32 val;
	switch(Region)
	{
		case 0:
			__asm{MRC	p15, 0, val, c6, c0, 1}
			break;
		case 1:
			__asm{MRC	p15, 0, val, c6, c1, 1}
			break;
		case 2:
			__asm{MRC	p15, 0, val, c6, c2, 1}
			break;
		case 3:
			__asm{MRC	p15, 0, val, c6, c3, 1}
			break;
		case 4:
			__asm{MRC	p15, 0, val, c6, c4, 1}
			break;
		case 5:
			__asm{MRC	p15, 0, val, c6, c5, 1}
			break;
		case 6:
			__asm{MRC	p15, 0, val, c6, c6, 1}
			break;
		case 7:
			__asm{MRC	p15, 0, val, c6, c7, 1}
			break;
	}
	return val;
}

void WriteInstrRegionBaseSizeReg(UINT32 Region, UINT32 val)
{
	switch(Region)
	{
		case 0:
			__asm { MCR	p15, 0, val, c6, c0, 1}
			break;
		case 1:
			__asm { MCR	p15, 0, val, c6, c1, 1}
			break;
		case 2:
			__asm { MCR	p15, 0, val, c6, c2, 1}
			break;
		case 3:
			__asm { MCR	p15, 0, val, c6, c3, 1}
			break;
		case 4:
			__asm { MCR	p15, 0, val, c6, c4, 1}
			break;
		case 5:
			__asm { MCR	p15, 0, val, c6, c5, 1}
			break;
		case 6:
			__asm { MCR	p15, 0, val, c6, c6, 1}
			break;
		case 7:
			__asm { MCR	p15, 0, val, c6, c7, 1}
			break;
	}
}
   
 

void CPUSetInstrRegionBaseSize(UINT32 region,UINT32 addr,UINT32 size,UINT32 enable) 
{
 UINT32 tmp;
 
	addr &= CP15_RBS_MEM_REGION_BASE_BITS;	
	size = (size << CP15_RBS_MEM_REGION_SIZE_LOC)&CP15_RBS_MEM_REGION_SIZE_BITS;;
	enable &=CP15_RBS_MEM_REGION_ENABLE;
	
	tmp = ReadInstrRegionBaseSizeReg(region);
	//clear unused bits
	tmp &= ~(CP15_RBS_MEM_REGION_BASE_BITS | CP15_RBS_MEM_REGION_SIZE_BITS);
	tmp |= (addr | size|enable);
	
	WriteInstrRegionBaseSizeReg(region,tmp);
	
}
	 


//write buffer operation

void CPUDrainWriteBuffer(void)
{
 UINT32 tmp;
   tmp = 0;
   
   __asm
   {
    MCR		p15,0,tmp,c7,c10,4
   }
}
  
//#ifdef FA510
//Branch target buffer operation
  
void CPUFlushBTBAll(void)
{
 UINT32 tmp;
   tmp = 0;
   
   __asm
   {
    MCR		p15,0,tmp,c7,c2,0
   }
}		
//#endif

//Instruction scratchpad RAM operation

void CPUFlushISpadAll(void)
{
 UINT32 tmp;
   tmp = 0;
   
   __asm
   {
    MCR		p15,0,tmp,c7,c2,1
   }
} 
  
//D-Cache operation

void CPUInvalidateDCacheAll(void)
{
 UINT32 tmp;
   tmp = 0;
   
	__asm
	{
	 MCR	p15, 0, tmp, c7, c6,0
	 }
}

void CPUInvalidateDCache(UINT32 addr)
{
	__asm
	{
	 MCR	p15, 0, addr, c7, c6, 1
	 }
}


void CPUCleanDCacheAll(void)
{
 UINT32 tmp;
   tmp = 0;
   
	__asm
	{
	 MCR 	p15,0,tmp,c7,c10,0
	}
}


void CPUCleanDCache(UINT32 addr)
{
	__asm
	{
	 MCR 	p15,0,addr,c7,c10,1
	}
}


void CPUCleanInvalidateDCacheAll(void)
{
 UINT32 tmp;
   tmp = 0;
   
	__asm
	{
	MCR	p15,0,tmp,c7,c14,0
	}
}


void CPUCleanInvalidateDCache(UINT32 addr)
{
	__asm
	{
	MCR	p15,0,addr,c7,c14,1
	}
}


//I-Cache operation 

void CPUInvalidateICacheAll(void)
{
 UINT32 tmp;
   tmp = 0;

 	__asm
    {
	 MCR p15, 0, tmp, c7, c0, 0
	 }	        
}

void CPUInvalidateICache(UINT32 addr)
{
 	__asm
	{
	 MCR p15, 0, addr, c7, c0, 1
	 }
}

void CPUPrefetchICache(UINT32 addr)
{
	__asm
	{
	 MCR	p15, 0, addr, c7, c13,1
	 }
}



void CPULockDCache(void)
{
  UINT32 tmp;
  
	__asm
	{
     MOV    tmp,#0
	 ORR    tmp,tmp,#0x80000000	
	 MCR	p15, 0, tmp, c9, c0, 0
	}
}

void CPUUnlockDCache(void)
{
 UINT32 tmp;
   tmp = 0;
   
	__asm
	{
	MCR	p15, 0, tmp, c9, c0, 0
	}
}

void CPULockICache(void)
{
  UINT32 tmp;
  
	__asm
	{
	 MOV    tmp,#0
	 ORR    tmp,tmp,#0x80000000	 
	 MCR	p15, 0, tmp, c9, c0, 1
	 }
}

void CPUUnlockICache(void)
{
 UINT32 tmp;
   tmp = 0;
   
	__asm
	{
	 MCR	p15, 0, tmp, c9, c0, 1
	 }
}

 
void EnableDataScratchpad(UINT32 base,UINT32 size) 
{
 UINT32 tmp;
 
 	tmp=base+(size<<4)+1;
 
 	__asm
 	{
  	MCR p15,0,tmp,c11,c0,0 
 	} 
}
 
 
void DisableDataScratchpad(void)
{
 UINT32 tmp;
 
 	tmp=0;
	__asm
 	{
  	MCR p15,0,tmp,c11,c0,0 
 	}
}
 

void EnableInstrScratchpad(UINT32 base,UINT32 size) 
{
 UINT32 tmp;
 
 	tmp=base+(size<<4)+1;

 	 __asm
 	{
 	MCR p15,0,tmp,c11,c0,1 
 	} 
}
 
 
void DisableInstrScratchpad(void)
{
 UINT32 tmp;
 
 	tmp=0;
 
	__asm
 	{
  	MCR p15,0,tmp,c11,c0,1 
 	}
}
 

void CPUSetExtEnable(UINT32 enable)
{

UINT32 tmp;
 
 	__asm
 	{
   	MRC 	p15,0,tmp,c14,c0,0
   	CMP  enable,#0   
   	ORRNE  tmp,tmp,#CP15_EXT_ECE_EN_MASK
   	BICEQ  tmp,tmp,#CP15_EXT_ECE_EN_MASK
   	MCR  p15,0,tmp,c14,c0,0
  	}	
}

void EnterIdleMode()
{
	__asm
	{
		mov	 r0, #0x0
  		MCR  p15,0,r0,c7,c8,2   //enter idle mode 
 	}
}

void EnterSleepMode()
{
	__asm
	{
		mov	 r0, #0x0
  		MCR  p15,0,r0,c7,c8,1   //enter sleep mode 
 	}
}

void EnterPowerSaving(UINT32 mode)
{
	if(mode== IDLE)
		EnterIdleMode();
	else
		EnterSleepMode();
}

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