📄 board_old.c
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/***************************************************************************
* Copyright Faraday Technology Corp 2002-2003. All rights reserved. *
*--------------------------------------------------------------------------*
* Name:board.c *
* Description: CPE board specfic routine *
* Author: Fred Chien *
****************************************************************************/
#include "cpe.h"
#include "fLib.h"
#include "stdio.h"
#include "swi.h"
#include "chipset.h"
#include "rtc.h"
#include "serial.h"
#include "gpio.h"
#include "fa510.h"
#include "arm922.h"
extern __rt_lib_init(int,int);
extern _fp_init(void);
extern int BaseOfFreeMemory;
extern int TopOfFreeMemory;
void Timer1_Tick(void);
void Timer2_Tick(void);
void Timer3_Tick(void);
void Init_CLib(void);
fLib_Date Curr_Date;
fLib_Time Curr_Time;
UINT32 CPU_TYPE;
UINT64 T1_Tick = 0,T2_Tick = 0, T3_Tick = 0;
UINT64 fLib_CurrentT1Tick()
{
return T1_Tick;
}
UINT64 fLib_CurrentT2Tick()
{
return T2_Tick;
}
UINT64 fLib_CurrentT3Tick()
{
return T3_Tick;
}
/*============================================================================
*
* routine: fLib_HardwareInit()
*
* parameters: void
*
* description: this routine does platform specific system initialization.
*
* calls: none
*
* returns: void
*
*============================================================================*/
extern unsigned int PMU_get_chipid(void);
unsigned int ChipIDCode;
void fLib_HardwareInit(void)
{
ChipIDCode = PMU_get_chipid();
fLib_InitFileSystem();
Init_CLib();
// Reset interrupt state
fLib_Int_Init();
fLib_SetSerialMode(DebugSerialPort, SERIAL_MDR_UART);
fLib_SerialInit(DebugSerialPort, (int)DEFAULT_HOST_BAUD, PARITY_NONE, 0, 8);
fLib_SetSerialFifoCtrl(DebugSerialPort, 0, 0, ENABLE, ENABLE); //V1.20//ADA10022002
fLib_SetSerialMode(SystemSerialPort, SERIAL_MDR_UART);
fLib_SerialInit(SystemSerialPort, (int)DEFAULT_HOST_BAUD, PARITY_NONE, 0, 8);
fLib_SetSerialFifoCtrl(SystemSerialPort, 0, 0, ENABLE, ENABLE);
fLib_RTC_Init();
// fLib_Timer_Init(1,1000,Timer1_Tick);
}
void Show_Number(UINT32 number)
{
int i;
UINT32 *debug_port=(volatile UINT32*)CPE_DBG_ALPHA;
i=number % 100;
i=(i/10)*16 + i%10;
*debug_port=i;
}
void Show_HexNumber(UINT32 number)
{
int i;
UINT32 *debug_port=(volatile UINT32*)CPE_DBG_ALPHA;
i= number % 0x100;
*debug_port=i;
}
void Do_Delay(UINT32 num)
{
UINT32 i;
for(i=num;i>0;i--);
}
UINT32 inw(UINT32 *port)
{
return *((volatile UINT32*)port);
}
void outw(UINT32 *port,UINT32 data)
{
*((volatile UINT32*)port)=data;
}
UINT16 inhw(UINT16 *port)
{
return *((volatile UINT16*)port);
}
void outhw(UINT16 *port,UINT16 data)
{
*((volatile UINT16*)port)=data;
}
UINT8 inb(UINT8 *port)
{
return *((volatile UINT8*)port);
}
void outb(UINT8 *port,UINT8 data)
{
*((volatile UINT8*)port)=data;
}
void InitMMU()
{
CPU_TYPE = CPUReadIDReg() & 0xFFFF;
switch(CPU_TYPE)
{
case 0x5001:
case 0x9401:
//enable instruction region
//DRAM code region
CPUSetInstrRegionBaseSize(0,0,MEM_REGION_2G,ENABLE);
CPUSetInstrRegionProtect(0,RW_ALL);
CPUSetICacheCacheable(0,CACHEABLE);
//Rom /Flash Region
CPUSetInstrRegionBaseSize(1,0x80000000,MEM_REGION_256M,ENABLE);
CPUSetInstrRegionProtect(1,RW_ALL);
CPUSetICacheCacheable(1,CACHEABLE);
//enable data region
CPUSetDataRegionBaseSize(0,0x0,MEM_REGION_2G,ENABLE);
CPUSetDataRegionProtect(0,RW_ALL);
CPUSetDCacheCacheable(0,CACHEABLE);
CPUSetWriteBufable(0,BUFFERABLE);
//enable rom/sram region
CPUSetDataRegionBaseSize(1,0x80000000,MEM_REGION_256M,ENABLE);
CPUSetDataRegionProtect(1,RW_ALL);
CPUSetDCacheCacheable(1,UNCACHEABLE);
CPUSetWriteBufable(1,UNBUFFERABLE);
// I/O Region
CPUSetDataRegionBaseSize(2,0x90000000,MEM_REGION_256M,ENABLE);
CPUSetDataRegionProtect(2,RW_ALL);
CPUSetDCacheCacheable(2,UNCACHEABLE);
CPUSetWriteBufable(2,UNBUFFERABLE);
//enable control register
CPUSetVectorBase(0);
CPUSetICacheEnable(ENABLE);
//CPUSetICacheEnable(DISABLE);
CPUSetExtEnable(ENABLE);
CPUSetBTBEnable(ENABLE);
CPUSetBigEndianEnable(DISABLE);
//before enable the write buffer the ECR bit 0 must be set
CPUSetWriteBufEnable(ENABLE);
CPUSetDCacheEnable(ENABLE);
//CPUSetDCacheEnable(DISABLE);
//CPUSetAlignCheckEnable(ENABLE);
CPUSetAlignCheckEnable(DISABLE);
CPUSetMMUEnable(ENABLE);
//clean and invaildtae all cache
CPUInvalidateICacheAll();
CPUCleanInvalidateDCacheAll();
CPUFlushBTBAll();
break;
case 0x9220:
uHALr_ResetMMU() ;
//Enabling the MMU and all caches
uHALr_InitMMU(IC_ON | DC_ON | WB_ON | EnableMMU) ;
// Disable the caches
uHALr_DisableCache() ;
// Finally, enable all of the caches
uHALr_EnableCache() ;
break;
}
}
UINT32 fLib_SysElapseTime()
{
UINT32 temp_sec;
temp_sec = inw(CPE_RTC_BASE + RtcSecond);
temp_sec += (inw(CPE_RTC_BASE + RtcMinute)) * 60;
temp_sec += (inw(CPE_RTC_BASE + RtcHour)) * 3600;
temp_sec += (inw(CPE_RTC_BASE + RtcDays)) * 86400;
return temp_sec;
}
/////////////////////////////////////////////////////
//
// Only for detail function call subroutine
//
/////////////////////////////////////////////////////
void Timer1_Tick()
{
#if 0
if( ChipIDCode ==FPLAT_CPE120_ID || ChipIDCode == FPLAT_CPE120_ID2)
fLib_ClearInt(19);
else
fLib_ClearInt(FIQ_TIMER1);
#endif
fLib_ClearInt(IRQ_TIMER1);
T1_Tick++;
}
void Timer2_Tick()
{
fLib_ClearInt(IRQ_TIMER2);
T2_Tick++;
}
void Timer3_Tick()
{
fLib_ClearInt(IRQ_TIMER3);
T3_Tick++;
}
void Init_CLib()
{
__rt_lib_init(BaseOfFreeMemory,TopOfFreeMemory);//edit by fred 0502
//__rt_lib_init((fLib_BaseOfFreeMemory,fLib_TopOfFreeMemory));
_fp_init();
}
//LED routines
/* Initialise the LED(s) to given value - usually 0 */
void fLib_SetLEDs(UINT32 value)
{
volatile UINT32 *LedBank = (UINT32 *) LED_BASE;
*LedBank = value;
}
/* Set the state of the specified LED */
int fLib_WriteLEDState(UINT32 number, UINT32 state)
{
UINT32 mask;
volatile UINT32 *LedBank = (UINT32 *) LED_BASE;
mask = 1 << (number + 15);
/* Want to turn LED on, determine which way we need to flip the bit */
if (state)
*LedBank &= ~mask; /* Set the bit */
else
*LedBank |= mask; /* Reset the bit */
return (1);
}
// End of file - board.c
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