fa510_old.h

FIC8120方案的 StartCell_Driver

/***************************************************************************
* Copyright  Faraday Technology Corp 2002-2003.  All rights reserved.      *
*--------------------------------------------------------------------------*
* Name:fa510.h                                                             *
* Description: CPU Cache and mmu library define                            *
* Author: Fred Chien                                                       *
****************************************************************************/
#ifndef __FA510_H
#define __FA510_H

#define DISABLE			0
#define ENABLE			1

#define UNCACHEABLE		0
#define CACHEABLE		1

#define UNBUFFERABLE	0
#define BUFFERABLE		1

//protection mode
#define NO_ACCESS		0x0
#define PRIV_ONLY		0x1
#define USER_RONLY		0x2
#define RW_ALL			0x3	


#define CP15_IPR_DPR_ACCESS_RIGHT_BITS		2


/* region base/size register */
#define CP15_RBS_MEM_REGION_SIZE_LOC		1
#define CP15_RBS_MEM_REGION_ENABLE			0x00000001
#define CP15_RBS_MEM_REGION_SIZE_BITS		0x0000003E
#define CP15_RBS_MEM_REGION_BASE_BITS		0xFFFFF000


#define MEM_REGION_4K						0x0B
#define MEM_REGION_8K						0x0C
#define MEM_REGION_16K						0x0D
#define MEM_REGION_32K						0x0E
#define MEM_REGION_64K						0x0F
#define MEM_REGION_128K						0x10
#define MEM_REGION_256K						0x11
#define MEM_REGION_512K						0x12
#define MEM_REGION_1M						0x13
#define MEM_REGION_2M						0x14
#define MEM_REGION_4M						0x15
#define MEM_REGION_8M						0x16
#define MEM_REGION_16M						0x17
#define MEM_REGION_32M						0x18
#define MEM_REGION_64M						0x19
#define MEM_REGION_128M						0x1A
#define MEM_REGION_256M						0x1B
#define MEM_REGION_512M						0x1C
#define MEM_REGION_1G						0x1D
#define MEM_REGION_2G						0x1E
#define MEM_REGION_4G						0x1F

#define CP15_EXT_ECE_EN_BIT			0
#define CP15_EXT_PDMS_EN_BIT		1


#define CP15_CFG_MMU_EN_BIT			0
#define CP15_CFG_ALIGN_EN_BIT		1
#define CP15_CFG_DCACHE_EN_BIT		2
#define CP15_CFG_WRITEBUF_EN_BIT	3
#define CP15_CFG_BIGENDIAN_EN_BIT	7
#define CP15_CFG_BTB_EN_BIT			11
#define CP15_CFG_ICACHE_EN_BIT		12
#define CP15_CFG_VECT_BASE_BIT		13


#define CP15_EXT_ECE_EN_MASK		(1<<CP15_EXT_ECE_EN_BIT)
#define CP15_EXT_PDMS_EN_MASK		(1<<CP15_EXT_PDMS_EN_BIT)


#define CP15_CFG_MMU_EN_MASK		(1<<CP15_CFG_MMU_EN_BIT)
#define CP15_CFG_ALIGN_EN_MASK		(1<<CP15_CFG_ALIGN_EN_BIT)
#define CP15_CFG_DCACHE_EN_MASK		(1<<CP15_CFG_DCACHE_EN_BIT)
#define CP15_CFG_WRITEBUF_EN_MASK	(1<<CP15_CFG_WRITEBUF_EN_BIT)
#define CP15_CFG_BIGENDIAN_EN_MASK	(1<<CP15_CFG_BIGENDIAN_EN_BIT)
#define CP15_CFG_BTB_EN_MASK		(1<<CP15_CFG_BTB_EN_BIT)
#define CP15_CFG_ICACHE_EN_MASK		(1<<CP15_CFG_ICACHE_EN_BIT) 
#define CP15_CFG_VECT_BASE_MASK		(1<<CP15_CFG_VECT_BASE_BIT)


//power saving
#define  ECE_EN			1
#define  IDLE			0
#define  SLEEP          1

//scratch pad size
#define  SCR_1K			0x8
#define  SCR_2K         0x9
#define  SCR_4K         0xA  



//external routine
extern UINT32 CPUReadIDReg(void);
extern UINT32 CPUReadCTR(void);
extern UINT32 CPUReadCFG(void);
extern void CPUInvalidateICacheAll(void);
extern void CPUInvalidateICache(UINT32 addr);
extern void CPUPrefetchICache(UINT32 addr);
extern void CPULockICache(void);
extern void CPUUnlockICache(void);
extern void CPUInvalidateDCacheAll(void);
extern void CPUInvalidateDCache(UINT32 addr);
extern void CPUCleanDCacheAll(void);
extern void CPUCleanDCache(UINT32 addr);
extern void CPUCleanInvalidateDCacheAll(void);
extern void CPUCleanInvalidateDCache(UINT32 addr);
extern void CPULockDCache(void);
extern void CPUUnlockDCache(void);
extern void CPUDrainWriteBuffer(void);
extern void CPUFlushBTBAll(void);
extern void CPUFlushISpadAll(void);
extern UINT32 CPUReadVendorID(void);
extern UINT32 CPUReadArchID(void);
extern UINT32 CPUReadPartNum(void);     
extern UINT32 CPUReadVersion(void);
extern void CPUSetVectorBase(UINT32 VectBase);
extern void CPUSetICacheEnable(UINT32 enable);
extern void CPUSetBTBEnable(UINT32 enable);
extern void CPUSetBigEndianEnable(UINT32 enable);
extern void CPUSetWriteBufEnable(UINT32 enable);
extern void CPUSetDCacheEnable(UINT32 enable);
extern void CPUSetAlignCheckEnable(UINT32 enable);
extern void CPUSetMMUEnable(UINT32 enable);
extern void CPUSetExtEnable(UINT32 enable);
extern UINT8 CPUCheckMMUEnable(void);
extern UINT8 CPUCheckDCacheEnable(void);
extern UINT8 CPUCheckICacheEnable(void);
extern UINT8 CPUCheckWriteBufEnable(void);
extern UINT8 CPUCheckBTBEnable(void);
extern void CPUSetDCacheCacheable(UINT32 region,UINT32 cacheable);
extern void CPUSetICacheCacheable(UINT32 region,UINT32 cacheable);
extern void CPUSetWriteBufable(UINT32 region,UINT32 enable);
extern void CPUSetDataRegionBaseSize(UINT32 region,UINT32 addr,UINT32 size,UINT32 enable) ;
extern void CPUSetInstrRegionBaseSize(UINT32 region,UINT32 addr,UINT32 size,UINT32 enable) ;
extern void CPUSetDataRegionProtect(UINT32 region,UINT32 mode);
extern void CPUSetInstrRegionProtect(UINT32 region,UINT32 mode);
extern void EnterPowerSaving(UINT32 mode);
extern void EnableDataScratchpad(UINT32 base,UINT32 size);
extern void DisableDataScratchpad(void);
extern void EnableInstrScratchpad(UINT32 base,UINT32 size);
extern void DisableInstrScratchpad(void); 
extern void CPUReset(void); 
extern void DeviceReset(void);

#endif