📄 pic18xx2.h
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static volatile near bit LD0 @ ((unsigned)&LATD*8)+0;
static volatile near bit LD1 @ ((unsigned)&LATD*8)+1;
static volatile near bit LD2 @ ((unsigned)&LATD*8)+2;
static volatile near bit LD3 @ ((unsigned)&LATD*8)+3;
static volatile near bit LD4 @ ((unsigned)&LATD*8)+4;
static volatile near bit LD5 @ ((unsigned)&LATD*8)+5;
static volatile near bit LD6 @ ((unsigned)&LATD*8)+6;
static volatile near bit LD7 @ ((unsigned)&LATD*8)+7;
static volatile near bit LE0 @ ((unsigned)&LATE*8)+0;
static volatile near bit LE1 @ ((unsigned)&LATE*8)+1;
static volatile near bit LE2 @ ((unsigned)&LATE*8)+2;
#endif
static volatile near bit LA0 @ ((unsigned)&LATA*8)+0;
static volatile near bit LA1 @ ((unsigned)&LATA*8)+1;
static volatile near bit LA2 @ ((unsigned)&LATA*8)+2;
static volatile near bit LA3 @ ((unsigned)&LATA*8)+3;
static volatile near bit LA4 @ ((unsigned)&LATA*8)+4;
static volatile near bit LA5 @ ((unsigned)&LATA*8)+5;
static volatile near bit LA6 @ ((unsigned)&LATA*8)+6;
static volatile near bit LA7 @ ((unsigned)&LATA*8)+7;
static volatile near bit LB0 @ ((unsigned)&LATB*8)+0;
static volatile near bit LB1 @ ((unsigned)&LATB*8)+1;
static volatile near bit LB2 @ ((unsigned)&LATB*8)+2;
static volatile near bit LB3 @ ((unsigned)&LATB*8)+3;
static volatile near bit LB4 @ ((unsigned)&LATB*8)+4;
static volatile near bit LB5 @ ((unsigned)&LATB*8)+5;
static volatile near bit LB6 @ ((unsigned)&LATB*8)+6;
static volatile near bit LB7 @ ((unsigned)&LATB*8)+7;
static volatile near bit LC0 @ ((unsigned)&LATC*8)+0;
static volatile near bit LC1 @ ((unsigned)&LATC*8)+1;
static volatile near bit LC2 @ ((unsigned)&LATC*8)+2;
static volatile near bit LC3 @ ((unsigned)&LATC*8)+3;
static volatile near bit LC4 @ ((unsigned)&LATC*8)+4;
static volatile near bit LC5 @ ((unsigned)&LATC*8)+5;
static volatile near bit LC6 @ ((unsigned)&LATC*8)+6;
static volatile near bit LC7 @ ((unsigned)&LATC*8)+7;
static near bit SCS @ ((unsigned)&OSCCON*8)+0;
static near bit LVDL0 @ ((unsigned)&LVDCON*8)+0;
static near bit LVDL1 @ ((unsigned)&LVDCON*8)+1;
static near bit LVDL2 @ ((unsigned)&LVDCON*8)+2;
static near bit LVDL3 @ ((unsigned)&LVDCON*8)+3;
static near bit LVDEN @ ((unsigned)&LVDCON*8)+4;
static volatile near bit IRVST @ ((unsigned)&LVDCON*8)+5;
static near bit GIE @ ((unsigned)&INTCON*8)+7;
static near bit GIEH @ ((unsigned)&INTCON*8)+7;
static near bit PEIE @ ((unsigned)&INTCON*8)+6;
static near bit GIEL @ ((unsigned)&INTCON*8)+6;
static near bit TMR0IE @ ((unsigned)&INTCON*8)+5;
static near bit INT0IE @ ((unsigned)&INTCON*8)+4;
static near bit RBIE @ ((unsigned)&INTCON*8)+3;
static volatile near bit TMR0IF @ ((unsigned)&INTCON*8)+2;
static volatile near bit INT0IF @ ((unsigned)&INTCON*8)+1;
static volatile near bit RBIF @ ((unsigned)&INTCON*8)+0;
static near bit ADCS1 @ ((unsigned)&ADCON0*8)+7;
static near bit ADCS0 @ ((unsigned)&ADCON0*8)+6;
static near bit CHS2 @ ((unsigned)&ADCON0*8)+5;
static near bit CHS1 @ ((unsigned)&ADCON0*8)+4;
static near bit CHS0 @ ((unsigned)&ADCON0*8)+3;
static volatile near bit GODONE @ ((unsigned)&ADCON0*8)+2;
static near bit ADON @ ((unsigned)&ADCON0*8)+0;
static near bit PCFG0 @ ((unsigned)&ADCON1*8)+0;
static near bit PCFG1 @ ((unsigned)&ADCON1*8)+1;
static near bit PCFG2 @ ((unsigned)&ADCON1*8)+2;
static near bit PCFG3 @ ((unsigned)&ADCON1*8)+3;
static near bit ADCS2 @ ((unsigned)&ADCON1*8)+6;
static near bit ADFM @ ((unsigned)&ADCON1*8)+7;
static near bit CCP1M0 @ ((unsigned)&CCP1CON*8)+0;
static near bit CCP1M1 @ ((unsigned)&CCP1CON*8)+1;
static near bit CCP1M2 @ ((unsigned)&CCP1CON*8)+2;
static near bit CCP1M3 @ ((unsigned)&CCP1CON*8)+3;
static volatile near bit DC1B0 @ ((unsigned)&CCP1CON*8)+4;
static volatile near bit DC1B1 @ ((unsigned)&CCP1CON*8)+5;
static near bit CCP2M0 @ ((unsigned)&CCP2CON*8)+0;
static near bit CCP2M1 @ ((unsigned)&CCP2CON*8)+1;
static near bit CCP2M2 @ ((unsigned)&CCP2CON*8)+2;
static near bit CCP2M3 @ ((unsigned)&CCP2CON*8)+3;
static volatile near bit DC2B0 @ ((unsigned)&CCP2CON*8)+4;
static volatile near bit DC2B1 @ ((unsigned)&CCP2CON*8)+5;
static near bit RBPU @ ((unsigned)&INTCON2*8)+7;
static near bit INTEDG0 @ ((unsigned)&INTCON2*8)+6;
static near bit INTEDG1 @ ((unsigned)&INTCON2*8)+5;
static near bit INTEDG2 @ ((unsigned)&INTCON2*8)+4;
static near bit TMR0IP @ ((unsigned)&INTCON2*8)+2;
static near bit RBIP @ ((unsigned)&INTCON2*8)+0;
static volatile near bit INT1IF @ ((unsigned)&INTCON3*8)+0;
static volatile near bit INT2IF @ ((unsigned)&INTCON3*8)+1;
static near bit INT1IE @ ((unsigned)&INTCON3*8)+3;
static near bit INT2IE @ ((unsigned)&INTCON3*8)+4;
static near bit INT1IP @ ((unsigned)&INTCON3*8)+6;
static near bit INT2IP @ ((unsigned)&INTCON3*8)+7;
static near bit TMR0ON @ ((unsigned)&T0CON*8)+7;
static near bit T08BIT @ ((unsigned)&T0CON*8)+6;
static near bit T0CS @ ((unsigned)&T0CON*8)+5;
static near bit T0SE @ ((unsigned)&T0CON*8)+4;
static near bit PSA @ ((unsigned)&T0CON*8)+3;
static near bit T0PS2 @ ((unsigned)&T0CON*8)+2;
static near bit T0PS1 @ ((unsigned)&T0CON*8)+1;
static near bit T0PS0 @ ((unsigned)&T0CON*8)+0;
static near bit IPEN @ ((unsigned)&RCON*8)+7;
static near bit LWRT @ ((unsigned)&RCON*8)+6;
static volatile near bit RI @ ((unsigned)&RCON*8)+4;
static volatile near bit TO @ ((unsigned)&RCON*8)+3;
static volatile near bit PD @ ((unsigned)&RCON*8)+2;
static volatile near bit POR @ ((unsigned)&RCON*8)+1;
static volatile near bit BOR @ ((unsigned)&RCON*8)+0;
static volatile near bit PSPIF @ ((unsigned)&PIR1*8)+7;
static volatile near bit ADIF @ ((unsigned)&PIR1*8)+6;
static volatile near bit RCIF @ ((unsigned)&PIR1*8)+5;
static volatile near bit TXIF @ ((unsigned)&PIR1*8)+4;
static volatile near bit SSPIF @ ((unsigned)&PIR1*8)+3;
static volatile near bit CCP1IF @ ((unsigned)&PIR1*8)+2;
static volatile near bit TMR2IF @ ((unsigned)&PIR1*8)+1;
static volatile near bit TMR1IF @ ((unsigned)&PIR1*8)+0;
static volatile near bit BCLIF @ ((unsigned)&PIR2*8)+3;
static volatile near bit LVDIF @ ((unsigned)&PIR2*8)+2;
static volatile near bit TMR3IF @ ((unsigned)&PIR2*8)+1;
static volatile near bit CCP2IF @ ((unsigned)&PIR2*8)+0;
static near bit PSPIE @ ((unsigned)&PIE1*8)+7;
static near bit ADIE @ ((unsigned)&PIE1*8)+6;
static near bit RCIE @ ((unsigned)&PIE1*8)+5;
static near bit TXIE @ ((unsigned)&PIE1*8)+4;
static near bit SSPIE @ ((unsigned)&PIE1*8)+3;
static near bit CCP1IE @ ((unsigned)&PIE1*8)+2;
static near bit TMR2IE @ ((unsigned)&PIE1*8)+1;
static near bit TMR1IE @ ((unsigned)&PIE1*8)+0;
static near bit BCLIE @ ((unsigned)&PIE2*8)+3;
static near bit LVDIE @ ((unsigned)&PIE2*8)+2;
static near bit TMR3IE @ ((unsigned)&PIE2*8)+1;
static near bit CCP2IE @ ((unsigned)&PIE2*8)+0;
static near bit PSPIP @ ((unsigned)&IPR1*8)+7;
static near bit ADIP @ ((unsigned)&IPR1*8)+6;
static near bit RCIP @ ((unsigned)&IPR1*8)+5;
static near bit TXIP @ ((unsigned)&IPR1*8)+4;
static near bit SSPIP @ ((unsigned)&IPR1*8)+3;
static near bit CCP1IP @ ((unsigned)&IPR1*8)+2;
static near bit TMR2IP @ ((unsigned)&IPR1*8)+1;
static near bit TMR1IP @ ((unsigned)&IPR1*8)+0;
static near bit BCLIP @ ((unsigned)&IPR2*8)+3;
static near bit LVDIP @ ((unsigned)&IPR2*8)+2;
static near bit TMR3IP @ ((unsigned)&IPR2*8)+1;
static near bit CCP2IP @ ((unsigned)&IPR2*8)+0;
static volatile near bit TRISA6 @ ((unsigned)&TRISA*8)+6;
static volatile near bit TRISA5 @ ((unsigned)&TRISA*8)+5;
static volatile near bit TRISA4 @ ((unsigned)&TRISA*8)+4;
static volatile near bit TRISA3 @ ((unsigned)&TRISA*8)+3;
static volatile near bit TRISA2 @ ((unsigned)&TRISA*8)+2;
static volatile near bit TRISA1 @ ((unsigned)&TRISA*8)+1;
static volatile near bit TRISA0 @ ((unsigned)&TRISA*8)+0;
static volatile near bit TRISB7 @ ((unsigned)&TRISB*8)+7;
static volatile near bit TRISB6 @ ((unsigned)&TRISB*8)+6;
static volatile near bit TRISB5 @ ((unsigned)&TRISB*8)+5;
static volatile near bit TRISB4 @ ((unsigned)&TRISB*8)+4;
static volatile near bit TRISB3 @ ((unsigned)&TRISB*8)+3;
static volatile near bit TRISB2 @ ((unsigned)&TRISB*8)+2;
static volatile near bit TRISB1 @ ((unsigned)&TRISB*8)+1;
static volatile near bit TRISB0 @ ((unsigned)&TRISB*8)+0;
static volatile near bit TRISC7 @ ((unsigned)&TRISC*8)+7;
static volatile near bit TRISC6 @ ((unsigned)&TRISC*8)+6;
static volatile near bit TRISC5 @ ((unsigned)&TRISC*8)+5;
static volatile near bit TRISC4 @ ((unsigned)&TRISC*8)+4;
static volatile near bit TRISC3 @ ((unsigned)&TRISC*8)+3;
static volatile near bit TRISC2 @ ((unsigned)&TRISC*8)+2;
static volatile near bit TRISC1 @ ((unsigned)&TRISC*8)+1;
static volatile near bit TRISC0 @ ((unsigned)&TRISC*8)+0;
#if defined(_18C442) || defined(_18C452)
static volatile near bit TRISD7 @ ((unsigned)&TRISD*8)+7;
static volatile near bit TRISD6 @ ((unsigned)&TRISD*8)+6;
static volatile near bit TRISD5 @ ((unsigned)&TRISD*8)+5;
static volatile near bit TRISD4 @ ((unsigned)&TRISD*8)+4;
static volatile near bit TRISD3 @ ((unsigned)&TRISD*8)+3;
static volatile near bit TRISD2 @ ((unsigned)&TRISD*8)+2;
static volatile near bit TRISD1 @ ((unsigned)&TRISD*8)+1;
static volatile near bit TRISD0 @ ((unsigned)&TRISD*8)+0;
static volatile near bit IBF @ ((unsigned)&TRISE*8)+7;
static volatile near bit OBF @ ((unsigned)&TRISE*8)+6;
static volatile near bit IBOV @ ((unsigned)&TRISE*8)+5;
static volatile near bit PSPMODE @ ((unsigned)&TRISE*8)+4;
static volatile near bit TRISE2 @ ((unsigned)&TRISE*8)+2;
static volatile near bit TRISE1 @ ((unsigned)&TRISE*8)+1;
static volatile near bit TRISE0 @ ((unsigned)&TRISE*8)+0;
#endif
#if defined(_18C242) || defined(_18C442)
#define ROMSIZE 16384
#else
#define ROMSIZE 32768
#endif
/* Configuration bit values */
#define OSCSEN 0xDFFF /* oscillator system clock switch enable */
#define OSCSDIS 0xFFFF
#define RCIO 0xFFFF /* oscillator types */
#define HSPLL 0xFEFF
#define ECIO 0xFDFF
#define EC 0xFCFF
#define RC 0xFBFF
#define HS 0xFAFF
#define XT 0xF9FF
#define LP 0xF8FF
#define UNPROTECT 0xFFFF /* code protection */
#define PROTECT 0xFF00
#define WDTPS128 0xFFFF /* watchdog timer postscale select */
#define WDTPS64 0xFDFF
#define WDTPS32 0xFBFF
#define WDTPS16 0xF9FF
#define WDTPS8 0xF7FF
#define WDTPS4 0xF5FF
#define WDTPS2 0xF3FF
#define WDTPS1 0xF1FF
#define WDTEN 0xFFFF /* watchdog timer enable */
#define WDTDIS 0xFEFF
#define BORV25 0xFFFF /* brown out reset voltage */
#define BORV27 0xFFFB
#define BORV42 0xFFF7
#define BORV45 0xFFF3
#define BOREN 0xFFFF /* brown out reset enable */
#define BORDIS 0xFFFD
#define PWRTEN 0xFFFE /* power-up timer enable */
#define PWRTDIS 0xFFFF
#define CCP2RC1 0xFFFF /* CCP2 MUX bit */
#define CCP2RB3 0xFEFF
#define STVREN 0xFFFF /* stack full/underflow reset enable */
#define STVRDIS 0xFFFE
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