pic18fxx20.h

PIC单片机PICC环境下PIC18FXX20系列通用头文件

static volatile	near bit	RF0	@ ((unsigned)&PORTF*8)+0;

// PORTE Register
static volatile	near bit	RE7	@ ((unsigned)&PORTE*8)+7;
static volatile	near bit	RE6	@ ((unsigned)&PORTE*8)+6;
static volatile	near bit	RE5	@ ((unsigned)&PORTE*8)+5;
static volatile	near bit	RE4	@ ((unsigned)&PORTE*8)+4;
static volatile	near bit	RE3	@ ((unsigned)&PORTE*8)+3;
static volatile	near bit	RE2	@ ((unsigned)&PORTE*8)+2;
static volatile	near bit	RE1	@ ((unsigned)&PORTE*8)+1;
static volatile	near bit	RE0	@ ((unsigned)&PORTE*8)+0;

// PORTD Register
static volatile	near bit	RD7	@ ((unsigned)&PORTD*8)+7;
static volatile	near bit	RD6	@ ((unsigned)&PORTD*8)+6;
static volatile	near bit	RD5	@ ((unsigned)&PORTD*8)+5;
static volatile	near bit	RD4	@ ((unsigned)&PORTD*8)+4;
static volatile	near bit	RD3	@ ((unsigned)&PORTD*8)+3;
static volatile	near bit	RD2	@ ((unsigned)&PORTD*8)+2;
static volatile	near bit	RD1	@ ((unsigned)&PORTD*8)+1;
static volatile	near bit	RD0	@ ((unsigned)&PORTD*8)+0;

// PORTC Register
static volatile	near bit	RC7	@ ((unsigned)&PORTC*8)+7;
static volatile	near bit	RC6	@ ((unsigned)&PORTC*8)+6;
static volatile	near bit	RC5	@ ((unsigned)&PORTC*8)+5;
static volatile	near bit	RC4	@ ((unsigned)&PORTC*8)+4;
static volatile	near bit	RC3	@ ((unsigned)&PORTC*8)+3;
static volatile	near bit	RC2	@ ((unsigned)&PORTC*8)+2;
static volatile	near bit	RC1	@ ((unsigned)&PORTC*8)+1;
static volatile	near bit	RC0	@ ((unsigned)&PORTC*8)+0;

// PORTB Register
static volatile	near bit	RB7	@ ((unsigned)&PORTB*8)+7;
static volatile	near bit	RB6	@ ((unsigned)&PORTB*8)+6;
static volatile	near bit	RB5	@ ((unsigned)&PORTB*8)+5;
static volatile	near bit	RB4	@ ((unsigned)&PORTB*8)+4;
static volatile	near bit	RB3	@ ((unsigned)&PORTB*8)+3;
static volatile	near bit	RB2	@ ((unsigned)&PORTB*8)+2;
static volatile	near bit	RB1	@ ((unsigned)&PORTB*8)+1;
static volatile	near bit	RB0	@ ((unsigned)&PORTB*8)+0;

// PORTA Register
static volatile	near bit	RA7	@ ((unsigned)&PORTA*8)+7;
static volatile	near bit	RA6	@ ((unsigned)&PORTA*8)+6;
static volatile	near bit	RA5	@ ((unsigned)&PORTA*8)+5;
static volatile	near bit	RA4	@ ((unsigned)&PORTA*8)+4;
static volatile	near bit	RA3	@ ((unsigned)&PORTA*8)+3;
static volatile	near bit	RA2	@ ((unsigned)&PORTA*8)+2;
static volatile	near bit	RA1	@ ((unsigned)&PORTA*8)+1;
static volatile	near bit	RA0	@ ((unsigned)&PORTA*8)+0;

// T4CON Register
static 		near bit	T4OUTPS3	@ ((unsigned)&T4CON*8)+6;
static 		near bit	T4OUTPS2	@ ((unsigned)&T4CON*8)+5;
static 		near bit	T4OUTPS1	@ ((unsigned)&T4CON*8)+4;
static 		near bit	T4OUTPS0	@ ((unsigned)&T4CON*8)+3;
static		near bit	TMR4ON		@ ((unsigned)&T4CON*8)+2;
static		near bit	T4CKPS1		@ ((unsigned)&T4CON*8)+1;
static 		near bit	T4CKPS0		@ ((unsigned)&T4CON*8)+0;

// CCP4CON Register
static volatile	near bit	DCCP4X	@ ((unsigned)&CCP4CON*8)+5;	// PWM duty cycle LSBs
static volatile	near bit	DCCP4Y	@ ((unsigned)&CCP4CON*8)+4;
static		near bit	CCP4M3	@ ((unsigned)&CCP4CON*8)+3;	// CCP4 mode select bits
static		near bit	CCP4M2	@ ((unsigned)&CCP4CON*8)+2;
static		near bit	CCP4M1	@ ((unsigned)&CCP4CON*8)+1;
static		near bit	CCP4M0	@ ((unsigned)&CCP4CON*8)+0;

// CCP5CON Register
static volatile	near bit	DCCP5X	@ ((unsigned)&CCP5CON*8)+5;	// PWM duty cycle LSBs
static volatile	near bit	DCCP5Y	@ ((unsigned)&CCP5CON*8)+4;
static		near bit	CCP5M3	@ ((unsigned)&CCP5CON*8)+3;	// CCP5 mode select bits
static		near bit	CCP5M2	@ ((unsigned)&CCP5CON*8)+2;
static		near bit	CCP5M1	@ ((unsigned)&CCP5CON*8)+1;
static		near bit	CCP5M0	@ ((unsigned)&CCP5CON*8)+0;

// TXSTA2 Register
static		near bit	CSRC2	@ ((unsigned)&TXSTA2*8)+7;	// CLK source select
static		near bit	TX92	@ ((unsigned)&TXSTA2*8)+6;	// 8/9 bit TX data select
static		near bit	TXEN2	@ ((unsigned)&TXSTA2*8)+5;	// transmit enable bit
static		near bit	SYNC2	@ ((unsigned)&TXSTA2*8)+4;	// USART mode select
static		near bit	BRGH2	@ ((unsigned)&TXSTA2*8)+2;	// high baud rate select
static volatile	near bit	TRMT2	@ ((unsigned)&TXSTA2*8)+1;	// TX shift reg. status bit
static		near bit	TX9D2	@ ((unsigned)&TXSTA2*8)+0;	// 9th Bit of TX data

// RCSTA2 Register
static		near bit	SPEN2	@ ((unsigned)&RCSTA2*8)+7;	// serial port enable
static		near bit	RX92	@ ((unsigned)&RCSTA2*8)+6;	// 8/9 bit data reception
static		near bit	SREN2	@ ((unsigned)&RCSTA2*8)+5;	// single recieve enable
static		near bit	CREN2	@ ((unsigned)&RCSTA2*8)+4;	// continuous recieve enable
static		near bit	ADDEN2	@ ((unsigned)&RCSTA2*8)+3;	// address detect enable
static volatile	near bit	FERR2	@ ((unsigned)&RCSTA2*8)+2;	// framing error
static volatile	near bit	OERR2	@ ((unsigned)&RCSTA2*8)+1;	// overrun error
static volatile	near bit	RX9D2	@ ((unsigned)&RCSTA2*8)+0;	// 9th Bit of RX data


#define EEPROM_SIZE	1024

#ifdef __PIC18FX520
#define ROMSIZE 32768
#elif defined(__PIC18FX620)
#define ROMSIZE 65536
#else
#define ROMSIZE 131072
#endif

// Configuration Bit Values

// config. register 1
// oscillator system clock switch
#define OSCSEN		0xDFFF	// enable
#define OSCSDIS		0xFFFF	// disable
// oscillator configuration types
#define RCRA6		0xFFFF	// RC with osc2 = RA6
#define HSPLL		0xFEFF	// HS with PLL enabled
#define ECRA6		0xFDFF	// EC with osc2 = RA6
#define ECDB4		0xFCFF	// EC with osc2 = div by 4 clk out
#define RC		0xFBFF
#define HS		0xFAFF
#define XT		0xF9FF
#define LP		0xF8FF

// config. register 2
// power-up timer
#define PWRTEN		0xFFFE	// enable
#define PWRTDIS		0xFFFF	// disable
// brown-out reset voltage
#define BORV25		0xFFFF	// 2.5 volts
#define BORV27		0xFFFB	// 2.7 volts
#define BORV42		0xFFF7	// 4.2 volts
#define BORV45		0xFFF3	// 4.5 volts
#define BORDIS		0xFFFD	// disabled
// watchdog postscale
#define WDTPS128	0xFFFF	// 1:128
#define WDTPS64		0xFDFF	// 1:64
#define WDTPS32		0xFBFF	// 1:32
#define WDTPS16		0xF9FF	// 1:16
#define WDTPS8		0xF7FF	// 1:8
#define WDTPS4		0xF5FF	// 1:4
#define WDTPS2		0xF3FF	// 1:2
#define WDTPS1		0xF1FF	// 1:1
// watchdog timer
#define WDTEN		0xFFFF	// enable
#define WDTDIS		0xFEFF	// disable

// config. register 3
#ifndef __PIC18F6X20 
// external bus data wait enable
#define WAITEN		0x7FFF	// WAIT mode active & determined by WAIT1:WAIT0 bits
#define WAITDIS		0xFFFF	// WAIT mode inactive
// microcontroller/processor operation mode
#define MCU		0xFFFF	// select microcontroller mode
#define MPU		0xFFFE	// select microprocessor mode
#define MPUBB		0xFFFD	// select microprocessor mode with boot block mode
#define XMCU		0xFFFC	// select extended microcontroller mode
#endif
// CCP2 multiplex selection
#define CCP2RC1		0xFFFF	// CCP2 multiplexed to RC1
#define CCP2RE7		0xFEFF	// CCP2 multiplexed to RE7
#ifdef __PIC18F8X20
#define CCP2RB3		0xFEFF	// CCP2 multiplexed to RB3
#endif
#ifdef __PIC18FX520
// Timer1 oscillation mode bit
#define T1OSCSTD	0xFFFF	// Standard (Legacy) Timer1 operation
#define T1OSCLP		0xFDFF	// Low poer Timer1 operation when MCU is in SLEEP mode
#endif

// config. register 4
// background debugger
#define DEBUGEN		0xFF7F	// enable
#define DEBUGDIS	0xFFFF	// disable
// low voltage ICSP
#define LVPEN		0xFFFF	// enable
#define LVPDIS		0xFFFB	// disable
// stack full/underflow reset enable
#define STVREN		0xFFFF	// stack full/under will cause reset
#define STVRDIS		0xFFFE	// stack full/under will not cause reset

// config. register 5
// general code protection
#ifdef __PIC18FX720
#define CPALL		0x3F00	// protect all blocks (incl. boot, data, config)
#define CPA		0xFF00	// protect 000200-01FFFFh
#define CP7		0xFF7F	// protect 01C000-01FFFFh
#define CP6		0xFFBF	// protect 018000-01BFFFh
#define CP5		0xFFDF	// protect 014000-017FFFh
#define CP4		0xFFEF	// protect 010000-013FFFh
#else
#define CPALL		0x3FF0	// protect all blocks (incl. boot, data, config)
#define CPA		0xFFF0	// protect 000200-00FFFFh (0800-7FFF in 18Fx520)
#endif
#define CP3		0xFFF7	// protect 00C000-00FFFFh (6000-7FFF in 18Fx520)
#define CP2		0xFFFB	// protect 008000-00BFFFh (4000-5FFF in 18Fx520)
#define CP1		0xFFFD	// protect 004000-007FFFh (2000-3FFF in 18Fx520)
#define CP0		0xFFFE	// protect 000200-003FFFh (0800-1FFF in 18Fx520)
#define UNPROTECT	0xFFFF	// unprotected code
// protect EEPROM data
#define CPD		0x7FFF	// protect EEPROM data
// protect boot block
#define CPB		0xBFFF	// protect boot code 00000-001FFh

// config. register 6
// write protection
#if defined(__PIC18FX720)
#define WPALL		0x1F00	// protect all blocks (incl. boot, data, config)
#define WPA		0xFF00	// protect 000200-01FFFFh
#define WP7		0xFF7F	// protect 01C000-01FFFFh
#define WP6		0xFFBF	// protect 018000-01BFFFh
#define WP5		0xFFDF	// protect 014000-017FFFh
#define WP4		0xFFEF	// protect 010000-013FFFh
#else
#define WPALL		0x1FF0	// protect all blocks (incl. boot, data, config)
#define WPA		0xFFF0	// protect 000200-00FFFFh
#endif
#define WP3		0xFFF7	// protect 00C000-00FFFFh (6000-7FFF in 18Fx520)
#define WP2		0xFFFB	// protect 008000-00BFFFh (4000-5FFF in 18Fx520)
#define WP1		0xFFFD	// protect 004000-007FFFh (2000-3FFF in 18Fx520)
#define WP0		0xFFFE	// protect 000200-003FFFh (0800-1FFF in 18Fx520)
// unprotect
#define WPU		0xFFFF	// write enabled
#define WRTEN		0xFFFF	// alternate definition
// write protection EEPROM data
#define WPD		0x7FFF	// write protect EEPROM data
// write protection boot section
#define WPB		0xBFFF	// write protect boot section
// write protection configuration registers
#define WPC		0xDFFF	// write protect config. regs

// config. register 7
//  table read protection
#if defined(__PIC18FX720)
#define TRPALL		0xBF00	// protect all blocks (incl. boot, data, config)
#define TRPA		0xFF00	// protect 000200-01FFFFh
#define TRP7		0xFF7F	// protect 01C000-01FFFFh
#define TRP6		0xFFBF	// protect 018000-01BFFFh
#define TRP5		0xFFDF	// protect 014000-017FFFh
#define TRP4		0xFFEF	// protect 010000-013FFFh
#else
#define TRPALL		0xBFF0	// protect all blocks (incl. boot, data, config)
#define TRPA		0xFFF0	// protect 000200-00FFFFh
#endif
#define TRP3		0xFFF7	// protect 00C000-00FFFFh (6000-7FFF in 18Fx520)
#define TRP2		0xFFFB	// protect 008000-00BFFFh (4000-5FFF in 18Fx520)
#define TRP1		0xFFFD	// protect 004000-007FFFh (2000-3FFF in 18Fx520)
#define TRP0		0xFFFE	// protect 000200-003FFFh (0800-1FFF in 18Fx520)
#define TRPB		0xBFFF	// Protect Boot Block
#define TRU		0xFFFF	// table read unprotected