📄 pic18fxx20.h
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static near bit TMR2IP @ ((unsigned)&IPR1*8)+1; // TMR2 - PR2 match interrupt priority
static near bit TMR1IP @ ((unsigned)&IPR1*8)+0; // TMR1 overflow interrupt priority
// Alternate definitions for compatibility with mono USART devices
static near bit RCIP @ ((unsigned)&IPR1*8)+5; // USART RX interrupt priority
static near bit TXIP @ ((unsigned)&IPR1*8)+4; // USART TX interrupt priority
// PIR1 Register
static volatile near bit PSPIF @ ((unsigned)&PIR1*8)+7; // para. slave port rd/wr interrupt flag
static volatile near bit ADIF @ ((unsigned)&PIR1*8)+6; // AD conv. interrupt flag
static volatile near bit RC1IF @ ((unsigned)&PIR1*8)+5; // USART RX interrupt flag
static volatile near bit TX1IF @ ((unsigned)&PIR1*8)+4; // USART TX interrupt flag
static volatile near bit SSPIF @ ((unsigned)&PIR1*8)+3; // master SSP interrupt flag
static volatile near bit CCP1IF @ ((unsigned)&PIR1*8)+2; // CCP1 interrupt flag
static volatile near bit TMR2IF @ ((unsigned)&PIR1*8)+1; // TMR2 - PR2 match interrupt flag
static volatile near bit TMR1IF @ ((unsigned)&PIR1*8)+0; // TMR1 overflow interrupt flag
// Alternate definitions for compatibility with mono USART devices
static volatile near bit RCIF @ ((unsigned)&PIR1*8)+5; // USART RX interrupt flag
static volatile near bit TXIF @ ((unsigned)&PIR1*8)+4; // USART TX interrupt flag
// PIE1 Register
static near bit PSPIE @ ((unsigned)&PIE1*8)+7; // para. slave port rd/wr interrupt enable
static near bit ADIE @ ((unsigned)&PIE1*8)+6; // AD conv. interrupt enable
static near bit RC1IE @ ((unsigned)&PIE1*8)+5; // USART RX interrupt enable
static near bit TX1IE @ ((unsigned)&PIE1*8)+4; // USART TX interrupt enable
static near bit SSPIE @ ((unsigned)&PIE1*8)+3; // master SSP interrupt enable
static near bit CCP1IE @ ((unsigned)&PIE1*8)+2; // CCP1 interrupt enable
static near bit TMR2IE @ ((unsigned)&PIE1*8)+1; // TMR2 - PR2 match interrupt enable
static near bit TMR1IE @ ((unsigned)&PIE1*8)+0; // TMR1 overflow interrupt enable
// Alternate definitions for compatibility with mono USART devices
static near bit RCIE @ ((unsigned)&PIE1*8)+5; // USART RX interrupt enable
static near bit TXIE @ ((unsigned)&PIE1*8)+4; // USART TX interrupt enable
#if defined(__PIC18F8X20)
// MEMCON Register
static near bit EBDIS @ ((unsigned)&MEMCON*8)+7; // external bus disable bit
static near bit WAIT1 @ ((unsigned)&MEMCON*8)+5; // table rd/bus cycle wait counts
static near bit WAIT0 @ ((unsigned)&MEMCON*8)+4; //
static near bit WM1 @ ((unsigned)&MEMCON*8)+1; // TABLWT 16-bit bus bits
static near bit WM0 @ ((unsigned)&MEMCON*8)+0; //
// TRISJ Register
static volatile near bit TRISJ7 @ ((unsigned)&TRISJ*8)+7;
static volatile near bit TRISJ6 @ ((unsigned)&TRISJ*8)+6;
static volatile near bit TRISJ5 @ ((unsigned)&TRISJ*8)+5;
static volatile near bit TRISJ4 @ ((unsigned)&TRISJ*8)+4;
static volatile near bit TRISJ3 @ ((unsigned)&TRISJ*8)+3;
static volatile near bit TRISJ2 @ ((unsigned)&TRISJ*8)+2;
static volatile near bit TRISJ1 @ ((unsigned)&TRISJ*8)+1;
static volatile near bit TRISJ0 @ ((unsigned)&TRISJ*8)+0;
// TRISH Register
static volatile near bit TRISH7 @ ((unsigned)&TRISH*8)+7;
static volatile near bit TRISH6 @ ((unsigned)&TRISH*8)+6;
static volatile near bit TRISH5 @ ((unsigned)&TRISH*8)+5;
static volatile near bit TRISH4 @ ((unsigned)&TRISH*8)+4;
static volatile near bit TRISH3 @ ((unsigned)&TRISH*8)+3;
static volatile near bit TRISH2 @ ((unsigned)&TRISH*8)+2;
static volatile near bit TRISH1 @ ((unsigned)&TRISH*8)+1;
static volatile near bit TRISH0 @ ((unsigned)&TRISH*8)+0;
#endif
// TRISG Register
static volatile near bit TRISG4 @ ((unsigned)&TRISG*8)+4;
static volatile near bit TRISG3 @ ((unsigned)&TRISG*8)+3;
static volatile near bit TRISG2 @ ((unsigned)&TRISG*8)+2;
static volatile near bit TRISG1 @ ((unsigned)&TRISG*8)+1;
static volatile near bit TRISG0 @ ((unsigned)&TRISG*8)+0;
// TRISF Register
static volatile near bit TRISF7 @ ((unsigned)&TRISF*8)+7;
static volatile near bit TRISF6 @ ((unsigned)&TRISF*8)+6;
static volatile near bit TRISF5 @ ((unsigned)&TRISF*8)+5;
static volatile near bit TRISF4 @ ((unsigned)&TRISF*8)+4;
static volatile near bit TRISF3 @ ((unsigned)&TRISF*8)+3;
static volatile near bit TRISF2 @ ((unsigned)&TRISF*8)+2;
static volatile near bit TRISF1 @ ((unsigned)&TRISF*8)+1;
static volatile near bit TRISF0 @ ((unsigned)&TRISF*8)+0;
// TRISE Register
static volatile near bit TRISE7 @ ((unsigned)&TRISE*8)+7;
static volatile near bit TRISE6 @ ((unsigned)&TRISE*8)+6;
static volatile near bit TRISE5 @ ((unsigned)&TRISE*8)+5;
static volatile near bit TRISE4 @ ((unsigned)&TRISE*8)+4;
static volatile near bit TRISE3 @ ((unsigned)&TRISE*8)+3;
static volatile near bit TRISE2 @ ((unsigned)&TRISE*8)+2;
static volatile near bit TRISE1 @ ((unsigned)&TRISE*8)+1;
static volatile near bit TRISE0 @ ((unsigned)&TRISE*8)+0;
// TRISD Register
static volatile near bit TRISD7 @ ((unsigned)&TRISD*8)+7;
static volatile near bit TRISD6 @ ((unsigned)&TRISD*8)+6;
static volatile near bit TRISD5 @ ((unsigned)&TRISD*8)+5;
static volatile near bit TRISD4 @ ((unsigned)&TRISD*8)+4;
static volatile near bit TRISD3 @ ((unsigned)&TRISD*8)+3;
static volatile near bit TRISD2 @ ((unsigned)&TRISD*8)+2;
static volatile near bit TRISD1 @ ((unsigned)&TRISD*8)+1;
static volatile near bit TRISD0 @ ((unsigned)&TRISD*8)+0;
// TRISC Register
static volatile near bit TRISC7 @ ((unsigned)&TRISC*8)+7;
static volatile near bit TRISC6 @ ((unsigned)&TRISC*8)+6;
static volatile near bit TRISC5 @ ((unsigned)&TRISC*8)+5;
static volatile near bit TRISC4 @ ((unsigned)&TRISC*8)+4;
static volatile near bit TRISC3 @ ((unsigned)&TRISC*8)+3;
static volatile near bit TRISC2 @ ((unsigned)&TRISC*8)+2;
static volatile near bit TRISC1 @ ((unsigned)&TRISC*8)+1;
static volatile near bit TRISC0 @ ((unsigned)&TRISC*8)+0;
// TRISB Register
static volatile near bit TRISB7 @ ((unsigned)&TRISB*8)+7;
static volatile near bit TRISB6 @ ((unsigned)&TRISB*8)+6;
static volatile near bit TRISB5 @ ((unsigned)&TRISB*8)+5;
static volatile near bit TRISB4 @ ((unsigned)&TRISB*8)+4;
static volatile near bit TRISB3 @ ((unsigned)&TRISB*8)+3;
static volatile near bit TRISB2 @ ((unsigned)&TRISB*8)+2;
static volatile near bit TRISB1 @ ((unsigned)&TRISB*8)+1;
static volatile near bit TRISB0 @ ((unsigned)&TRISB*8)+0;
// TRISA Register
static volatile near bit TRISA6 @ ((unsigned)&TRISA*8)+6;
static volatile near bit TRISA5 @ ((unsigned)&TRISA*8)+5;
static volatile near bit TRISA4 @ ((unsigned)&TRISA*8)+4;
static volatile near bit TRISA3 @ ((unsigned)&TRISA*8)+3;
static volatile near bit TRISA2 @ ((unsigned)&TRISA*8)+2;
static volatile near bit TRISA1 @ ((unsigned)&TRISA*8)+1;
static volatile near bit TRISA0 @ ((unsigned)&TRISA*8)+0;
#if defined(__PIC18F8X20)
// LATJ Register
static volatile near bit LATJ7 @ ((unsigned)&LATJ*8)+7;
static volatile near bit LATJ6 @ ((unsigned)&LATJ*8)+6;
static volatile near bit LATJ5 @ ((unsigned)&LATJ*8)+5;
static volatile near bit LATJ4 @ ((unsigned)&LATJ*8)+4;
static volatile near bit LATJ3 @ ((unsigned)&LATJ*8)+3;
static volatile near bit LATJ2 @ ((unsigned)&LATJ*8)+2;
static volatile near bit LATJ1 @ ((unsigned)&LATJ*8)+1;
static volatile near bit LATJ0 @ ((unsigned)&LATJ*8)+0;
// LATH Register
static volatile near bit LATH7 @ ((unsigned)&LATH*8)+7;
static volatile near bit LATH6 @ ((unsigned)&LATH*8)+6;
static volatile near bit LATH5 @ ((unsigned)&LATH*8)+5;
static volatile near bit LATH4 @ ((unsigned)&LATH*8)+4;
static volatile near bit LATH3 @ ((unsigned)&LATH*8)+3;
static volatile near bit LATH2 @ ((unsigned)&LATH*8)+2;
static volatile near bit LATH1 @ ((unsigned)&LATH*8)+1;
static volatile near bit LATH0 @ ((unsigned)&LATH*8)+0;
#endif
// LATG Register
static volatile near bit LATG4 @ ((unsigned)&LATG*8)+4;
static volatile near bit LATG3 @ ((unsigned)&LATG*8)+3;
static volatile near bit LATG2 @ ((unsigned)&LATG*8)+2;
static volatile near bit LATG1 @ ((unsigned)&LATG*8)+1;
static volatile near bit LATG0 @ ((unsigned)&LATG*8)+0;
// LATF Register
static volatile near bit LATF7 @ ((unsigned)&LATF*8)+7;
static volatile near bit LATF6 @ ((unsigned)&LATF*8)+6;
static volatile near bit LATF5 @ ((unsigned)&LATF*8)+5;
static volatile near bit LATF4 @ ((unsigned)&LATF*8)+4;
static volatile near bit LATF3 @ ((unsigned)&LATF*8)+3;
static volatile near bit LATF2 @ ((unsigned)&LATF*8)+2;
static volatile near bit LATF1 @ ((unsigned)&LATF*8)+1;
static volatile near bit LATF0 @ ((unsigned)&LATF*8)+0;
// LATE Register
static volatile near bit LATE7 @ ((unsigned)&LATE*8)+7;
static volatile near bit LATE6 @ ((unsigned)&LATE*8)+6;
static volatile near bit LATE5 @ ((unsigned)&LATE*8)+5;
static volatile near bit LATE4 @ ((unsigned)&LATE*8)+4;
static volatile near bit LATE3 @ ((unsigned)&LATE*8)+3;
static volatile near bit LATE2 @ ((unsigned)&LATE*8)+2;
static volatile near bit LATE1 @ ((unsigned)&LATE*8)+1;
static volatile near bit LATE0 @ ((unsigned)&LATE*8)+0;
// LATD Register
static volatile near bit LATD7 @ ((unsigned)&LATD*8)+7;
static volatile near bit LATD6 @ ((unsigned)&LATD*8)+6;
static volatile near bit LATD5 @ ((unsigned)&LATD*8)+5;
static volatile near bit LATD4 @ ((unsigned)&LATD*8)+4;
static volatile near bit LATD3 @ ((unsigned)&LATD*8)+3;
static volatile near bit LATD2 @ ((unsigned)&LATD*8)+2;
static volatile near bit LATD1 @ ((unsigned)&LATD*8)+1;
static volatile near bit LATD0 @ ((unsigned)&LATD*8)+0;
// LATC Register
static volatile near bit LATC7 @ ((unsigned)&LATC*8)+7;
static volatile near bit LATC6 @ ((unsigned)&LATC*8)+6;
static volatile near bit LATC5 @ ((unsigned)&LATC*8)+5;
static volatile near bit LATC4 @ ((unsigned)&LATC*8)+4;
static volatile near bit LATC3 @ ((unsigned)&LATC*8)+3;
static volatile near bit LATC2 @ ((unsigned)&LATC*8)+2;
static volatile near bit LATC1 @ ((unsigned)&LATC*8)+1;
static volatile near bit LATC0 @ ((unsigned)&LATC*8)+0;
// LATB Register
static volatile near bit LATB7 @ ((unsigned)&LATB*8)+7;
static volatile near bit LATB6 @ ((unsigned)&LATB*8)+6;
static volatile near bit LATB5 @ ((unsigned)&LATB*8)+5;
static volatile near bit LATB4 @ ((unsigned)&LATB*8)+4;
static volatile near bit LATB3 @ ((unsigned)&LATB*8)+3;
static volatile near bit LATB2 @ ((unsigned)&LATB*8)+2;
static volatile near bit LATB1 @ ((unsigned)&LATB*8)+1;
static volatile near bit LATB0 @ ((unsigned)&LATB*8)+0;
// LATA Register
static volatile near bit LATA6 @ ((unsigned)&LATA*8)+6;
static volatile near bit LATA5 @ ((unsigned)&LATA*8)+5;
static volatile near bit LATA4 @ ((unsigned)&LATA*8)+4;
static volatile near bit LATA3 @ ((unsigned)&LATA*8)+3;
static volatile near bit LATA2 @ ((unsigned)&LATA*8)+2;
static volatile near bit LATA1 @ ((unsigned)&LATA*8)+1;
static volatile near bit LATA0 @ ((unsigned)&LATA*8)+0;
#if defined(__PIC18F8X20)
// PORTJ Register
static volatile near bit RJ7 @ ((unsigned)&PORTJ*8)+7;
static volatile near bit RJ6 @ ((unsigned)&PORTJ*8)+6;
static volatile near bit RJ5 @ ((unsigned)&PORTJ*8)+5;
static volatile near bit RJ4 @ ((unsigned)&PORTJ*8)+4;
static volatile near bit RJ3 @ ((unsigned)&PORTJ*8)+3;
static volatile near bit RJ2 @ ((unsigned)&PORTJ*8)+2;
static volatile near bit RJ1 @ ((unsigned)&PORTJ*8)+1;
static volatile near bit RJ0 @ ((unsigned)&PORTJ*8)+0;
// PORTH Register
static volatile near bit RH7 @ ((unsigned)&PORTH*8)+7;
static volatile near bit RH6 @ ((unsigned)&PORTH*8)+6;
static volatile near bit RH5 @ ((unsigned)&PORTH*8)+5;
static volatile near bit RH4 @ ((unsigned)&PORTH*8)+4;
static volatile near bit RH3 @ ((unsigned)&PORTH*8)+3;
static volatile near bit RH2 @ ((unsigned)&PORTH*8)+2;
static volatile near bit RH1 @ ((unsigned)&PORTH*8)+1;
static volatile near bit RH0 @ ((unsigned)&PORTH*8)+0;
#endif
// PORTG Register
static volatile near bit RG4 @ ((unsigned)&PORTG*8)+4;
static volatile near bit RG3 @ ((unsigned)&PORTG*8)+3;
static volatile near bit RG2 @ ((unsigned)&PORTG*8)+2;
static volatile near bit RG1 @ ((unsigned)&PORTG*8)+1;
static volatile near bit RG0 @ ((unsigned)&PORTG*8)+0;
// PORTF Register
static volatile near bit RF7 @ ((unsigned)&PORTF*8)+7;
static volatile near bit RF6 @ ((unsigned)&PORTF*8)+6;
static volatile near bit RF5 @ ((unsigned)&PORTF*8)+5;
static volatile near bit RF4 @ ((unsigned)&PORTF*8)+4;
static volatile near bit RF3 @ ((unsigned)&PORTF*8)+3;
static volatile near bit RF2 @ ((unsigned)&PORTF*8)+2;
static volatile near bit RF1 @ ((unsigned)&PORTF*8)+1;
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