pic18fxx20.h

PIC单片机PICC环境下PIC18FXX20系列通用头文件

// LVDCON Register
static volatile	near bit	IRVST	@ ((unsigned)&LVDCON*8)+5;	// input reference voltage stable status
static		near bit	LVDEN	@ ((unsigned)&LVDCON*8)+4;	// low voltage detect enable
static		near bit	LVDL3	@ ((unsigned)&LVDCON*8)+3;	// low voltage detection limits
static		near bit	LVDL2	@ ((unsigned)&LVDCON*8)+2;
static		near bit	LVDL1	@ ((unsigned)&LVDCON*8)+1;
static		near bit	LVDL0	@ ((unsigned)&LVDCON*8)+0;

// WDTCON Register
static		near bit	SWDTEN	@ ((unsigned)&WDTCON*8)+0;	// software watchdog timer enable

// RCON Register
static		near bit	IPEN	@ ((unsigned)&RCON*8)+7;	// interrupt priority enable
static volatile	near bit	RI	@ ((unsigned)&RCON*8)+4;	// RESET instruction status
static volatile	near bit	TO	@ ((unsigned)&RCON*8)+3;	// watchdog timeout flag
static volatile	near bit	PD	@ ((unsigned)&RCON*8)+2;	// power-down detection
static volatile	near bit	POR	@ ((unsigned)&RCON*8)+1;	// power-on reset status
static volatile	near bit	BOR	@ ((unsigned)&RCON*8)+0;	// brown-our reset status

// T1CON Register
static		near bit	RD16	@ ((unsigned)&T1CON*8)+7;	// 16 Bit Read/Write Enable
static		near bit	T1RD16	@ ((unsigned)&T1CON*8)+7;	// 16 Bit Read/Write Enable
static		near bit	T1CKPS1	@ ((unsigned)&T1CON*8)+5;	// Prescaler
static		near bit	T1CKPS0	@ ((unsigned)&T1CON*8)+4;
static		near bit	T1OSCEN	@ ((unsigned)&T1CON*8)+3;	// Oscillator Enable
static		near bit	T1SYNC	@ ((unsigned)&T1CON*8)+2;	// Sync Selct
static		near bit	TMR1CS	@ ((unsigned)&T1CON*8)+1;	// TMR Clock Source Select
static		near bit	TMR1ON	@ ((unsigned)&T1CON*8)+0;	// TMR on/off

// T2CON Register
static		near bit	T2OUTPS3	@ ((unsigned)&T2CON*8)+6;	// Postscale
static		near bit	T2OUTPS2	@ ((unsigned)&T2CON*8)+5;
static		near bit	T2OUTPS1	@ ((unsigned)&T2CON*8)+4;
static		near bit	T2OUTPS0	@ ((unsigned)&T2CON*8)+3;
static		near bit	TMR2ON		@ ((unsigned)&T2CON*8)+2;	// TMR2 On/Off
static		near bit	T2CKPS1		@ ((unsigned)&T2CON*8)+1;	// Prescale
static		near bit	T2CKPS0		@ ((unsigned)&T2CON*8)+0;

// SSPSTAT Register
static volatile	near bit	SMP	@ ((unsigned)&SSPSTAT*8)+7;	// Sample Bit
static		near bit	CKE	@ ((unsigned)&SSPSTAT*8)+6;	// SPI Clk Edge Select
static volatile	near bit	DA	@ ((unsigned)&SSPSTAT*8)+5;	// Data/Address Bit
static volatile	near bit	STOP	@ ((unsigned)&SSPSTAT*8)+4;	// STOP Bit detected
static volatile	near bit	START	@ ((unsigned)&SSPSTAT*8)+3;	// START Bit detected
static volatile	near bit	RW	@ ((unsigned)&SSPSTAT*8)+2;	// Read/Write bit Information
static volatile	near bit	UA	@ ((unsigned)&SSPSTAT*8)+1;	// Update Adress
static volatile	near bit	BF	@ ((unsigned)&SSPSTAT*8)+0;	// Buffer Full Status bit

// SSPCON1 Register
static volatile	near bit	WCOL	@ ((unsigned)&SSPCON1*8)+7;	// write collision detect
static volatile	near bit	SSPOV	@ ((unsigned)&SSPCON1*8)+6;	// recieve overflow indicator
static		near bit	SSPEN	@ ((unsigned)&SSPCON1*8)+5;	// SSP enable
static		near bit	CKP	@ ((unsigned)&SSPCON1*8)+4;	// clock polarity select
static		near bit	SSPM3	@ ((unsigned)&SSPCON1*8)+3;	// SSP mode select
static		near bit	SSPM2	@ ((unsigned)&SSPCON1*8)+2;
static		near bit	SSPM1	@ ((unsigned)&SSPCON1*8)+1;
static		near bit	SSPM0	@ ((unsigned)&SSPCON1*8)+0;

// SSPCON2 Register
static		near bit	GCEN	@ ((unsigned)&SSPCON2*8)+7;	// general call enable
static volatile	near bit	ACKSTAT	@ ((unsigned)&SSPCON2*8)+6;	// acknowledge status bit
static volatile	near bit	ACKDT	@ ((unsigned)&SSPCON2*8)+5;	// acknowledge data bit
static volatile	near bit	ACKEN	@ ((unsigned)&SSPCON2*8)+4;	// acknowledge sequence enable
static		near bit	RCEN	@ ((unsigned)&SSPCON2*8)+3;	// recieve enable bit
static volatile	near bit	PEN	@ ((unsigned)&SSPCON2*8)+2;	// STOP condition enable
static volatile	near bit	RSEN	@ ((unsigned)&SSPCON2*8)+1;	// repeated START enable
static volatile	near bit	SEN	@ ((unsigned)&SSPCON2*8)+0;	// START condition enable

// ADCON0 Register
static		near bit	CHS3	@ ((unsigned)&ADCON0*8)+5;	// channel select
static		near bit	CHS2	@ ((unsigned)&ADCON0*8)+4;
static		near bit	CHS1	@ ((unsigned)&ADCON0*8)+3;
static		near bit	CHS0	@ ((unsigned)&ADCON0*8)+2;
static volatile	near bit	GODONE	@ ((unsigned)&ADCON0*8)+1;	// AD conversion status
static		near bit	ADON	@ ((unsigned)&ADCON0*8)+0;	// AD on status

// ADCON1 Register
static		near bit	VCFG1	@ ((unsigned)&ADCON1*8)+5;	// 
static		near bit	VCFG0	@ ((unsigned)&ADCON1*8)+4;	// 
static		near bit	PCFG3	@ ((unsigned)&ADCON1*8)+3;	// AD port config bits
static		near bit	PCFG2	@ ((unsigned)&ADCON1*8)+2;
static		near bit	PCFG1	@ ((unsigned)&ADCON1*8)+1;
static		near bit	PCFG0	@ ((unsigned)&ADCON1*8)+0;

// ADCON2 Register
static		near bit	ADFM	@ ((unsigned)&ADCON2*8)+7;	// AD result format
static		near bit	ADCS2	@ ((unsigned)&ADCON2*8)+2;	// AD conv. clock select bits
static		near bit	ADCS1	@ ((unsigned)&ADCON2*8)+1;	// AD conv. clock select bits
static		near bit	ADCS0	@ ((unsigned)&ADCON2*8)+0;	// AD conv. clock select bits

// CCP1CON Register
static volatile	near bit	DC1B1	@ ((unsigned)&CCP1CON*8)+5;	// Duty Cycle Bits 1 & 0
static volatile	near bit	DC1B0	@ ((unsigned)&CCP1CON*8)+4;
static		near bit	CCP1M3	@ ((unsigned)&CCP1CON*8)+3;	// Mode Select Bits
static		near bit	CCP1M2	@ ((unsigned)&CCP1CON*8)+2;
static		near bit	CCP1M1	@ ((unsigned)&CCP1CON*8)+1;
static		near bit	CCP1M0	@ ((unsigned)&CCP1CON*8)+0;

// CCP2CON Register
static volatile	near bit	DC2B1	@ ((unsigned)&CCP2CON*8)+5;	// PWM duty cycle LSBs
static volatile	near bit	DC2B0	@ ((unsigned)&CCP2CON*8)+4;
static		near bit	CCP2M3	@ ((unsigned)&CCP2CON*8)+3;	// CCP2 mode select bits
static		near bit	CCP2M2	@ ((unsigned)&CCP2CON*8)+2;
static		near bit	CCP2M1	@ ((unsigned)&CCP2CON*8)+1;
static		near bit	CCP2M0	@ ((unsigned)&CCP2CON*8)+0;

// CCP3CON Register
static volatile	near bit	DCCP3X	@ ((unsigned)&CCP3CON*8)+5;	// PWM duty cycle LSBs
static volatile	near bit	DCCP3Y	@ ((unsigned)&CCP3CON*8)+4;
static		near bit	CCP3M3	@ ((unsigned)&CCP3CON*8)+3;	// CCP3 mode select bits
static		near bit	CCP3M2	@ ((unsigned)&CCP3CON*8)+2;
static		near bit	CCP3M1	@ ((unsigned)&CCP3CON*8)+1;
static		near bit	CCP3M0	@ ((unsigned)&CCP3CON*8)+0;

// CVRCON Register
static		near bit	CVREN	@ ((unsigned)&CVRCON*8)+7;	// comparator voltage reference enable
static		near bit	CVROE	@ ((unsigned)&CVRCON*8)+6;	// comparator VREF output enable
static		near bit	CVRR	@ ((unsigned)&CVRCON*8)+5;	// comparator VREF range select
static		near bit	CVRSS	@ ((unsigned)&CVRCON*8)+4;	// comparator VREF source select
static		near bit	CVR3	@ ((unsigned)&CVRCON*8)+3;	// comparator VREF value selection
static		near bit	CVR2	@ ((unsigned)&CVRCON*8)+2;
static		near bit	CVR1	@ ((unsigned)&CVRCON*8)+1;
static		near bit	CVR0	@ ((unsigned)&CVRCON*8)+0;

// CMCON Comparator module register
static volatile	near bit	C2OUT	@ ((unsigned)&CMCON*8)+7;	// comparator 2 output
static volatile	near bit	C1OUT	@ ((unsigned)&CMCON*8)+6;	// comparator 1 output
static		near bit	C2INV	@ ((unsigned)&CMCON*8)+5;	// select to invert comp2 output
static		near bit	C1INV	@ ((unsigned)&CMCON*8)+4;	// select to invert comp1 output
static		near bit	CIS	@ ((unsigned)&CMCON*8)+3;	// comp input switch bit
static		near bit	CM2	@ ((unsigned)&CMCON*8)+2;	// comp mode select bits
static		near bit	CM1	@ ((unsigned)&CMCON*8)+1;
static		near bit	CM0	@ ((unsigned)&CMCON*8)+0;

// T3CON Register
static		near bit	T3RD16	@ ((unsigned)&T3CON*8)+7;	// 16-Bit Read/Write select
static		near bit	T3CCP2	@ ((unsigned)&T3CON*8)+6;	// TMR3 & TMR1 CCPx Enable
static		near bit	T3CKPS1	@ ((unsigned)&T3CON*8)+5;	// Prescaler
static		near bit	T3CKPS0	@ ((unsigned)&T3CON*8)+4;
static		near bit	T3CCP1	@ ((unsigned)&T3CON*8)+3;	// TMR3 & TMR1 CCPx Enable
static		near bit	T3SYNC	@ ((unsigned)&T3CON*8)+2;	// Sync Select
static		near bit	TMR3CS	@ ((unsigned)&T3CON*8)+1;	// TMR3 source Select
static		near bit	TMR3ON	@ ((unsigned)&T3CON*8)+0;	// TMR3 on/off

// PSPCON Register
static volatile	near bit	IBF	@ ((unsigned)&PSPCON*8)+7;	// input buffer full status
static volatile	near bit	OBF	@ ((unsigned)&PSPCON*8)+6;	// output buffer full status
static volatile	near bit	IBOV	@ ((unsigned)&PSPCON*8)+5;	// input buffer overflow
static		near bit	PSPMODE	@ ((unsigned)&PSPCON*8)+4;	// parallel slave port mode select

// TXSTA Register
static		near bit	CSRC1	@ ((unsigned)&TXSTA1*8)+7;	// CLK source select
static		near bit	TX91	@ ((unsigned)&TXSTA1*8)+6;	// 8/9-bit TX data select
static		near bit	TXEN1	@ ((unsigned)&TXSTA1*8)+5;	// transmit enable bit
static		near bit	SYNC1	@ ((unsigned)&TXSTA1*8)+4;	// USART mode select
static		near bit	BRGH1	@ ((unsigned)&TXSTA1*8)+2;	// high baud rate select
static volatile	near bit	TRMT1	@ ((unsigned)&TXSTA1*8)+1;	// TX shift reg. status bit
static		near bit	TX9D1	@ ((unsigned)&TXSTA1*8)+0;	// 9th Bit of TX data
// Alternate definitions for compatibility with mono USART devices
static		near bit	CSRC	@ ((unsigned)&TXSTA1*8)+7;	// CLK source select
static		near bit	TX9	@ ((unsigned)&TXSTA1*8)+6;	// 8/9-bit TX data select
static		near bit	TXEN	@ ((unsigned)&TXSTA1*8)+5;	// transmit enable bit
static		near bit	SYNC	@ ((unsigned)&TXSTA1*8)+4;	// USART mode select
static		near bit	BRGH	@ ((unsigned)&TXSTA1*8)+2;	// high baud rate select
static volatile	near bit	TRMT	@ ((unsigned)&TXSTA1*8)+1;	// TX shift reg. status bit
static		near bit	TX9D	@ ((unsigned)&TXSTA1*8)+0;	// 9th Bit of TX data

// RCSTA Register
static		near bit	SPEN1	@ ((unsigned)&RCSTA1*8)+7;	// serial port enable
static		near bit	RX91	@ ((unsigned)&RCSTA1*8)+6;	// 8/9-bit data reception
static		near bit	SREN1	@ ((unsigned)&RCSTA1*8)+5;	// single recieve enable
static		near bit	CREN1	@ ((unsigned)&RCSTA1*8)+4;	// continuous recieve enable
static		near bit	ADDEN1	@ ((unsigned)&RCSTA1*8)+3;	// address detect enable
static volatile	near bit	FERR1	@ ((unsigned)&RCSTA1*8)+2;	// framing error
static volatile	near bit	OERR1	@ ((unsigned)&RCSTA1*8)+1;	// overrun error
static volatile	near bit	RX9D1	@ ((unsigned)&RCSTA1*8)+0;	// 9th Bit of RX data
// Alternate definitions for compatibility with mono USART devices
static		near bit	SPEN	@ ((unsigned)&RCSTA1*8)+7;	// serial port enable
static		near bit	RX9	@ ((unsigned)&RCSTA1*8)+6;	// 8/9-bit data reception
static		near bit	SREN	@ ((unsigned)&RCSTA1*8)+5;	// single recieve enable
static		near bit	CREN	@ ((unsigned)&RCSTA1*8)+4;	// continuous recieve enable
static		near bit	ADDEN	@ ((unsigned)&RCSTA1*8)+3;	// address detect enable
static volatile	near bit	FERR	@ ((unsigned)&RCSTA1*8)+2;	// framing error
static volatile	near bit	OERR	@ ((unsigned)&RCSTA1*8)+1;	// overrun error
static volatile	near bit	RX9D	@ ((unsigned)&RCSTA1*8)+0;	// 9th Bit of RX data

// EECON1 Register
static		near bit	EEPGD	@ ((unsigned)&EECON1*8)+7;	// FLASH/EEPROM select
static		near bit	CFGS	@ ((unsigned)&EECON1*8)+6;	// access config regs./access FLASH-EEPROM
// alternate definition
static		near bit	EEFS	@ ((unsigned)&EECON1*8)+6;	// access config regs./access FLASH-EEPROM
static volatile	near bit	FREE	@ ((unsigned)&EECON1*8)+4;	// FLASH row erase enable
static volatile	near bit	WRERR	@ ((unsigned)&EECON1*8)+3;	// write error flag
static		near bit	WREN	@ ((unsigned)&EECON1*8)+2;	// write enable
static volatile	near bit	WR	@ ((unsigned)&EECON1*8)+1;	// write control
static volatile	near bit	RD	@ ((unsigned)&EECON1*8)+0;	// read control

// IPR3 Register
static		near bit 	RC2IP	@ ((unsigned)&IPR3*8)+5;	// RX buffer 2 interrupt priority
static		near bit 	TX2IP	@ ((unsigned)&IPR3*8)+4;	// TX buffer 2 interrupt priority
static		near bit 	TMR4IP	@ ((unsigned)&IPR3*8)+3;	// timer 4 interrupt priority
static		near bit 	CCP5IP	@ ((unsigned)&IPR3*8)+2;	// CCP 5 interrupt priority
static		near bit 	CCP4IP	@ ((unsigned)&IPR3*8)+1;	// CCP 4 interrupt priority
static		near bit 	CCP3IP	@ ((unsigned)&IPR3*8)+0;	// CCP 3 interrupt priority	     

// PIR3 Register
static volatile	near bit	RC2IF	@ ((unsigned)&PIR3*8)+5;	// RX buffer 2 interrupt flag
static volatile	near bit	TX2IF	@ ((unsigned)&PIR3*8)+4;	// TX buffer 2 interrupt flag
static volatile	near bit	TMR4IF	@ ((unsigned)&PIR3*8)+3;	// timer 4 interrupt flag
static volatile	near bit	CCP5IF	@ ((unsigned)&PIR3*8)+2;	// CCP 5 interrupt flag
static volatile	near bit	CCP4IF	@ ((unsigned)&PIR3*8)+1;	// CCP 4 interrupt flag
static volatile	near bit	CCP3IF	@ ((unsigned)&PIR3*8)+0;	// CCP 3 interrupt flag	  		

// PIE3 Register
static		near bit 	RC2IE	@ ((unsigned)&PIE3*8)+5;	// RX buffer 2 interrupt enable
static		near bit 	TX2IE	@ ((unsigned)&PIE3*8)+4;	// TX buffer 2 interrupt enable
static		near bit 	TMR4IE	@ ((unsigned)&PIE3*8)+3;	// timer 4 interrupt enable
static		near bit 	CCP5IE	@ ((unsigned)&PIE3*8)+2;	// CCP 5 interrupt enable
static		near bit 	CCP4IE	@ ((unsigned)&PIE3*8)+1;	// CCP 4 interrupt enable
static		near bit 	CCP3IE	@ ((unsigned)&PIE3*8)+0;	// CCP 3 interrupt enable	  	     

// IPR2 Register
static		near bit 	CMIP	@ ((unsigned)&IPR2*8)+6;	// comparator interrupt priority		
static		near bit 	EEIP	@ ((unsigned)&IPR2*8)+4;	// EEPROM write interrupt priority
static		near bit 	BCLIP	@ ((unsigned)&IPR2*8)+3;	// bus collision interrupt priority
static		near bit 	LVDIP	@ ((unsigned)&IPR2*8)+2;	// low voltage detect interrupt priority
static		near bit 	TMR3IP	@ ((unsigned)&IPR2*8)+1;	// TMR3 overflow interrupt priority
static		near bit 	CCP2IP	@ ((unsigned)&IPR2*8)+0;	// CCP2 interrupt priority

// PIR2 Register
static volatile	near bit	CMIF 	@ ((unsigned)&PIR2*8)+6;	// comparator interrupt flag		
static volatile	near bit	EEIF 	@ ((unsigned)&PIR2*8)+4;	// EEPROM write interrupt flag
static volatile	near bit	BCLIF 	@ ((unsigned)&PIR2*8)+3;	// bus collision interrupt flag
static volatile	near bit	LVDIF 	@ ((unsigned)&PIR2*8)+2;	// low voltage detect interrupt flag
static volatile	near bit	TMR3IF 	@ ((unsigned)&PIR2*8)+1;	// TMR3 overflow interrupt flag
static volatile	near bit	CCP2IF	@ ((unsigned)&PIR2*8)+0;	// CCP2 interrupt flag

// PIE2 Register
static		near bit 	CMIE 	@ ((unsigned)&PIE2*8)+6;	// comparator interrupt enable		
static		near bit 	EEIE 	@ ((unsigned)&PIE2*8)+4;	// EEPROM write interrupt enable
static		near bit 	BCLIE 	@ ((unsigned)&PIE2*8)+3;	// bus collision interrupt enable
static		near bit 	LVDIE 	@ ((unsigned)&PIE2*8)+2;	// low voltage detect interrupt enable
static		near bit 	TMR3IE 	@ ((unsigned)&PIE2*8)+1;	// TMR3 overflow interrupt enable
static		near bit 	CCP2IE	@ ((unsigned)&PIE2*8)+0;	// CCP2 interrupt enable

// IPR1 Register
static		near bit 	PSPIP	@ ((unsigned)&IPR1*8)+7;	// para. slave port rd/wr interrupt priority
static		near bit 	ADIP	@ ((unsigned)&IPR1*8)+6;	// AD conv. interrupt priority
static		near bit 	RC1IP	@ ((unsigned)&IPR1*8)+5;	// USART RX interrupt priority
static		near bit 	TX1IP	@ ((unsigned)&IPR1*8)+4;	// USART TX interrupt priority
static		near bit 	SSPIP	@ ((unsigned)&IPR1*8)+3;	// master SSP interrupt priority
static		near bit 	CCP1IP	@ ((unsigned)&IPR1*8)+2;	// CCP1 interrupt priority