cont2060.tan.qmsg

学EDA 的时候做的

{ "Info" "ITDB_FULL_TCO_RESULT" "CLK CQH\[0\] lpm_counter:CQI_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[4\] 40.300 ns register " "Info: tco from clock \"CLK\" to destination pin \"CQH\[0\]\" through register \"lpm_counter:CQI_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[4\]\" is 40.300 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 1.900 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to source register is 1.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns CLK 1 CLK PIN_79 8 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 8; CLK Node = 'CLK'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "cont2060.vhd" "" { Text "D:/Quartus/cont2060/cont2060.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(0.000 ns) 1.900 ns lpm_counter:CQI_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[4\] 2 REG LC5_H34 22 " "Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC5_H34; Fanout = 22; REG Node = 'lpm_counter:CQI_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[4\]'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "1.400 ns" { CLK lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[4] } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "d:/program files/quartus7.1/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 289 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.500 ns ( 26.32 % ) " "Info: Total cell delay = 0.500 ns ( 26.32 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.400 ns ( 73.68 % ) " "Info: Total interconnect delay = 1.400 ns ( 73.68 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { CLK lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[4] } "NODE_NAME" } } { "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "1.900 ns" { CLK CLK~out lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[4] } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "alt_counter_f10ke.tdf" "" { Text "d:/program files/quartus7.1/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 289 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "37.300 ns + Longest register pin " "Info: + Longest register to pin delay is 37.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_counter:CQI_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[4\] 1 REG LC5_H34 22 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC5_H34; Fanout = 22; REG Node = 'lpm_counter:CQI_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[4\]'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[4] } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "d:/program files/quartus7.1/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 289 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.800 ns) + CELL(2.200 ns) 4.000 ns LessThan2~66 2 COMB LC6_H36 2 " "Info: 2: + IC(1.800 ns) + CELL(2.200 ns) = 4.000 ns; Loc. = LC6_H36; Fanout = 2; COMB Node = 'LessThan2~66'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "4.000 ns" { lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[4] LessThan2~66 } "NODE_NAME" } } { "cont2060.vhd" "" { Text "D:/Quartus/cont2060/cont2060.vhd" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.000 ns) + CELL(1.700 ns) 9.700 ns CQ~370 3 COMB LC2_J17 8 " "Info: 3: + IC(4.000 ns) + CELL(1.700 ns) = 9.700 ns; Loc. = LC2_J17; Fanout = 8; COMB Node = 'CQ~370'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "5.700 ns" { LessThan2~66 CQ~370 } "NODE_NAME" } } { "cont2060.vhd" "" { Text "D:/Quartus/cont2060/cont2060.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.100 ns) + CELL(2.200 ns) 14.000 ns Selector3~171 4 COMB LC1_J24 1 " "Info: 4: + IC(2.100 ns) + CELL(2.200 ns) = 14.000 ns; Loc. = LC1_J24; Fanout = 1; COMB Node = 'Selector3~171'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "4.300 ns" { CQ~370 Selector3~171 } "NODE_NAME" } } { "cont2060.vhd" "" { Text "D:/Quartus/cont2060/cont2060.vhd" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.800 ns) + CELL(1.700 ns) 17.500 ns Selector3~172 5 COMB LC1_J25 1 " "Info: 5: + IC(1.800 ns) + CELL(1.700 ns) = 17.500 ns; Loc. = LC1_J25; Fanout = 1; COMB Node = 'Selector3~172'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "3.500 ns" { Selector3~171 Selector3~172 } "NODE_NAME" } } { "cont2060.vhd" "" { Text "D:/Quartus/cont2060/cont2060.vhd" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.100 ns) + CELL(1.500 ns) 20.100 ns Selector3~180 6 COMB LC5_J26 1 " "Info: 6: + IC(1.100 ns) + CELL(1.500 ns) = 20.100 ns; Loc. = LC5_J26; Fanout = 1; COMB Node = 'Selector3~180'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "2.600 ns" { Selector3~172 Selector3~180 } "NODE_NAME" } } { "cont2060.vhd" "" { Text "D:/Quartus/cont2060/cont2060.vhd" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 22.000 ns Selector3~175 7 COMB LC6_J26 2 " "Info: 7: + IC(0.000 ns) + CELL(1.900 ns) = 22.000 ns; Loc. = LC6_J26; Fanout = 2; COMB Node = 'Selector3~175'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { Selector3~180 Selector3~175 } "NODE_NAME" } } { "cont2060.vhd" "" { Text "D:/Quartus/cont2060/cont2060.vhd" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.300 ns) + CELL(1.700 ns) 28.000 ns CQH\[0\]~0 8 COMB LC8_E10 1 " "Info: 8: + IC(4.300 ns) + CELL(1.700 ns) = 28.000 ns; Loc. = LC8_E10; Fanout = 1; COMB Node = 'CQH\[0\]~0'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { Selector3~175 CQH[0]~0 } "NODE_NAME" } } { "cont2060.vhd" "" { Text "D:/Quartus/cont2060/cont2060.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.700 ns) + CELL(8.600 ns) 37.300 ns CQH\[0\] 9 PIN PIN_131 0 " "Info: 9: + IC(0.700 ns) + CELL(8.600 ns) = 37.300 ns; Loc. = PIN_131; Fanout = 0; PIN Node = 'CQH\[0\]'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "9.300 ns" { CQH[0]~0 CQH[0] } "NODE_NAME" } } { "cont2060.vhd" "" { Text "D:/Quartus/cont2060/cont2060.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "21.500 ns ( 57.64 % ) " "Info: Total cell delay = 21.500 ns ( 57.64 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "15.800 ns ( 42.36 % ) " "Info: Total interconnect delay = 15.800 ns ( 42.36 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "37.300 ns" { lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[4] LessThan2~66 CQ~370 Selector3~171 Selector3~172 Selector3~180 Selector3~175 CQH[0]~0 CQH[0] } "NODE_NAME" } } { "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "37.300 ns" { lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[4] LessThan2~66 CQ~370 Selector3~171 Selector3~172 Selector3~180 Selector3~175 CQH[0]~0 CQH[0] } { 0.000ns 1.800ns 4.000ns 2.100ns 1.800ns 1.100ns 0.000ns 4.300ns 0.700ns } { 0.000ns 2.200ns 1.700ns 2.200ns 1.700ns 1.500ns 1.900ns 1.700ns 8.600ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { CLK lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[4] } "NODE_NAME" } } { "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "1.900 ns" { CLK CLK~out lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[4] } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } "" } } { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "37.300 ns" { lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[4] LessThan2~66 CQ~370 Selector3~171 Selector3~172 Selector3~180 Selector3~175 CQH[0]~0 CQH[0] } "NODE_NAME" } } { "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "37.300 ns" { lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[4] LessThan2~66 CQ~370 Selector3~171 Selector3~172 Selector3~180 Selector3~175 CQH[0]~0 CQH[0] } { 0.000ns 1.800ns 4.000ns 2.100ns 1.800ns 1.100ns 0.000ns 4.300ns 0.700ns } { 0.000ns 2.200ns 1.700ns 2.200ns 1.700ns 1.500ns 1.900ns 1.700ns 8.600ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "SEL COUT 15.800 ns Longest " "Info: Longest tpd from source pin \"SEL\" to destination pin \"COUT\" is 15.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns SEL 1 PIN PIN_78 4 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_78; Fanout = 4; PIN Node = 'SEL'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SEL } "NODE_NAME" } } { "cont2060.vhd" "" { Text "D:/Quartus/cont2060/cont2060.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.800 ns) + CELL(2.000 ns) 4.300 ns Equal0~57 2 COMB LC2_H35 1 " "Info: 2: + IC(1.800 ns) + CELL(2.000 ns) = 4.300 ns; Loc. = LC2_H35; Fanout = 1; COMB Node = 'Equal0~57'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "3.800 ns" { SEL Equal0~57 } "NODE_NAME" } } { "d:/program files/quartus7.1/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/program files/quartus7.1/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.900 ns) 6.400 ns Equal0~58 3 COMB LC3_H35 1 " "Info: 3: + IC(0.200 ns) + CELL(1.900 ns) = 6.400 ns; Loc. = LC3_H35; Fanout = 1; COMB Node = 'Equal0~58'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "2.100 ns" { Equal0~57 Equal0~58 } "NODE_NAME" } } { "d:/program files/quartus7.1/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/program files/quartus7.1/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.800 ns) + CELL(8.600 ns) 15.800 ns COUT 4 PIN PIN_30 0 " "Info: 4: + IC(0.800 ns) + CELL(8.600 ns) = 15.800 ns; Loc. = PIN_30; Fanout = 0; PIN Node = 'COUT'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "9.400 ns" { Equal0~58 COUT } "NODE_NAME" } } { "cont2060.vhd" "" { Text "D:/Quartus/cont2060/cont2060.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "13.000 ns ( 82.28 % ) " "Info: Total cell delay = 13.000 ns ( 82.28 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.800 ns ( 17.72 % ) " "Info: Total interconnect delay = 2.800 ns ( 17.72 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "15.800 ns" { SEL Equal0~57 Equal0~58 COUT } "NODE_NAME" } } { "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "15.800 ns" { SEL SEL~out Equal0~57 Equal0~58 COUT } { 0.000ns 0.000ns 1.800ns 0.200ns 0.800ns } { 0.000ns 0.500ns 2.000ns 1.900ns 8.600ns } "" } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "lpm_counter:CQI_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\] EN CLK 0.100 ns register " "Info: th for register \"lpm_counter:CQI_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\]\" (data pin = \"EN\", clock pin = \"CLK\") is 0.100 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 1.900 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to destination register is 1.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns CLK 1 CLK PIN_79 8 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 8; CLK Node = 'CLK'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "cont2060.vhd" "" { Text "D:/Quartus/cont2060/cont2060.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(0.000 ns) 1.900 ns lpm_counter:CQI_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\] 2 REG LC1_H34 7 " "Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC1_H34; Fanout = 7; REG Node = 'lpm_counter:CQI_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\]'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "1.400 ns" { CLK lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "d:/program files/quartus7.1/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 289 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.500 ns ( 26.32 % ) " "Info: Total cell delay = 0.500 ns ( 26.32 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.400 ns ( 73.68 % ) " "Info: Total interconnect delay = 1.400 ns ( 73.68 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { CLK lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } } { "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "1.900 ns" { CLK CLK~out lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.900 ns + " "Info: + Micro hold delay of destination is 0.900 ns" {  } { { "alt_counter_f10ke.tdf" "" { Text "d:/program files/quartus7.1/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 289 2 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.700 ns - Shortest pin register " "Info: - Shortest pin to register delay is 2.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns EN 1 PIN PIN_182 22 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_182; Fanout = 22; PIN Node = 'EN'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { EN } "NODE_NAME" } } { "cont2060.vhd" "" { Text "D:/Quartus/cont2060/cont2060.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.900 ns) + CELL(0.300 ns) 2.700 ns lpm_counter:CQI_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\] 2 REG LC1_H34 7 " "Info: 2: + IC(1.900 ns) + CELL(0.300 ns) = 2.700 ns; Loc. = LC1_H34; Fanout = 7; REG Node = 'lpm_counter:CQI_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\]'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "2.200 ns" { EN lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "d:/program files/quartus7.1/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 289 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.800 ns ( 29.63 % ) " "Info: Total cell delay = 0.800 ns ( 29.63 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.900 ns ( 70.37 % ) " "Info: Total interconnect delay = 1.900 ns ( 70.37 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "2.700 ns" { EN lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } } { "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "2.700 ns" { EN EN~out lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } { 0.000ns 0.000ns 1.900ns } { 0.000ns 0.500ns 0.300ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { CLK lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } } { "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "1.900 ns" { CLK CLK~out lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } "" } } { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "2.700 ns" { EN lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } } { "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "2.700 ns" { EN EN~out lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } { 0.000ns 0.000ns 1.900ns } { 0.000ns 0.500ns 0.300ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "114 " "Info: Allocated 114 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Sun Nov 11 16:19:25 2007 " "Info: Processing ended: Sun Nov 11 16:19:25 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}