cont2060.tan.rpt

学EDA 的时候做的

; N/A           ; None        ; -6.000 ns ; SEL  ; lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[3] ; CLK      ;
; N/A           ; None        ; -6.000 ns ; SEL  ; lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[2] ; CLK      ;
; N/A           ; None        ; -6.000 ns ; SEL  ; lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[5] ; CLK      ;
; N/A           ; None        ; -6.000 ns ; SEL  ; lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[4] ; CLK      ;
; N/A           ; None        ; -6.000 ns ; SEL  ; lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[7] ; CLK      ;
; N/A           ; None        ; -6.000 ns ; SEL  ; lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[6] ; CLK      ;
+---------------+-------------+-----------+------+-----------------------------------------------------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.1 Build 156 04/30/2007 SJ Full Version
    Info: Processing started: Sun Nov 11 16:19:23 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off cont2060 -c cont2060
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "CLK" is an undefined clock
Info: Clock "CLK" has Internal fmax of 74.63 MHz between source register "lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[2]" and destination register "lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[0]" (period= 13.4 ns)
    Info: + Longest register to register delay is 11.600 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC3_H34; Fanout = 22; REG Node = 'lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[2]'
        Info: 2: + IC(1.100 ns) + CELL(2.000 ns) = 3.100 ns; Loc. = LC5_H35; Fanout = 1; COMB Node = 'Equal0~59'
        Info: 3: + IC(0.200 ns) + CELL(1.900 ns) = 5.200 ns; Loc. = LC6_H35; Fanout = 1; COMB Node = 'LessThan0~407'
        Info: 4: + IC(0.200 ns) + CELL(1.900 ns) = 7.300 ns; Loc. = LC7_H35; Fanout = 1; COMB Node = 'LessThan0~408'
        Info: 5: + IC(0.200 ns) + CELL(1.700 ns) = 9.200 ns; Loc. = LC1_H35; Fanout = 8; COMB Node = 'lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[7]~1'
        Info: 6: + IC(1.100 ns) + CELL(1.300 ns) = 11.600 ns; Loc. = LC1_H34; Fanout = 7; REG Node = 'lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[0]'
        Info: Total cell delay = 8.800 ns ( 75.86 % )
        Info: Total interconnect delay = 2.800 ns ( 24.14 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "CLK" to destination register is 1.900 ns
            Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 8; CLK Node = 'CLK'
            Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC1_H34; Fanout = 7; REG Node = 'lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[0]'
            Info: Total cell delay = 0.500 ns ( 26.32 % )
            Info: Total interconnect delay = 1.400 ns ( 73.68 % )
        Info: - Longest clock path from clock "CLK" to source register is 1.900 ns
            Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 8; CLK Node = 'CLK'
            Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC3_H34; Fanout = 22; REG Node = 'lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[2]'
            Info: Total cell delay = 0.500 ns ( 26.32 % )
            Info: Total interconnect delay = 1.400 ns ( 73.68 % )
    Info: + Micro clock to output delay of source is 1.100 ns
    Info: + Micro setup delay of destination is 0.700 ns
Info: tsu for register "lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[0]" (data pin = "SEL", clock pin = "CLK") is 11.500 ns
    Info: + Longest pin to register delay is 12.700 ns
        Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_78; Fanout = 4; PIN Node = 'SEL'
        Info: 2: + IC(1.800 ns) + CELL(1.900 ns) = 4.200 ns; Loc. = LC5_H35; Fanout = 1; COMB Node = 'Equal0~59'
        Info: 3: + IC(0.200 ns) + CELL(1.900 ns) = 6.300 ns; Loc. = LC6_H35; Fanout = 1; COMB Node = 'LessThan0~407'
        Info: 4: + IC(0.200 ns) + CELL(1.900 ns) = 8.400 ns; Loc. = LC7_H35; Fanout = 1; COMB Node = 'LessThan0~408'
        Info: 5: + IC(0.200 ns) + CELL(1.700 ns) = 10.300 ns; Loc. = LC1_H35; Fanout = 8; COMB Node = 'lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[7]~1'
        Info: 6: + IC(1.100 ns) + CELL(1.300 ns) = 12.700 ns; Loc. = LC1_H34; Fanout = 7; REG Node = 'lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[0]'
        Info: Total cell delay = 9.200 ns ( 72.44 % )
        Info: Total interconnect delay = 3.500 ns ( 27.56 % )
    Info: + Micro setup delay of destination is 0.700 ns
    Info: - Shortest clock path from clock "CLK" to destination register is 1.900 ns
        Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 8; CLK Node = 'CLK'
        Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC1_H34; Fanout = 7; REG Node = 'lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[0]'
        Info: Total cell delay = 0.500 ns ( 26.32 % )
        Info: Total interconnect delay = 1.400 ns ( 73.68 % )
Info: tco from clock "CLK" to destination pin "CQH[0]" through register "lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[4]" is 40.300 ns
    Info: + Longest clock path from clock "CLK" to source register is 1.900 ns
        Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 8; CLK Node = 'CLK'
        Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC5_H34; Fanout = 22; REG Node = 'lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[4]'
        Info: Total cell delay = 0.500 ns ( 26.32 % )
        Info: Total interconnect delay = 1.400 ns ( 73.68 % )
    Info: + Micro clock to output delay of source is 1.100 ns
    Info: + Longest register to pin delay is 37.300 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC5_H34; Fanout = 22; REG Node = 'lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[4]'
        Info: 2: + IC(1.800 ns) + CELL(2.200 ns) = 4.000 ns; Loc. = LC6_H36; Fanout = 2; COMB Node = 'LessThan2~66'
        Info: 3: + IC(4.000 ns) + CELL(1.700 ns) = 9.700 ns; Loc. = LC2_J17; Fanout = 8; COMB Node = 'CQ~370'
        Info: 4: + IC(2.100 ns) + CELL(2.200 ns) = 14.000 ns; Loc. = LC1_J24; Fanout = 1; COMB Node = 'Selector3~171'
        Info: 5: + IC(1.800 ns) + CELL(1.700 ns) = 17.500 ns; Loc. = LC1_J25; Fanout = 1; COMB Node = 'Selector3~172'
        Info: 6: + IC(1.100 ns) + CELL(1.500 ns) = 20.100 ns; Loc. = LC5_J26; Fanout = 1; COMB Node = 'Selector3~180'
        Info: 7: + IC(0.000 ns) + CELL(1.900 ns) = 22.000 ns; Loc. = LC6_J26; Fanout = 2; COMB Node = 'Selector3~175'
        Info: 8: + IC(4.300 ns) + CELL(1.700 ns) = 28.000 ns; Loc. = LC8_E10; Fanout = 1; COMB Node = 'CQH[0]~0'
        Info: 9: + IC(0.700 ns) + CELL(8.600 ns) = 37.300 ns; Loc. = PIN_131; Fanout = 0; PIN Node = 'CQH[0]'
        Info: Total cell delay = 21.500 ns ( 57.64 % )
        Info: Total interconnect delay = 15.800 ns ( 42.36 % )
Info: Longest tpd from source pin "SEL" to destination pin "COUT" is 15.800 ns
    Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_78; Fanout = 4; PIN Node = 'SEL'
    Info: 2: + IC(1.800 ns) + CELL(2.000 ns) = 4.300 ns; Loc. = LC2_H35; Fanout = 1; COMB Node = 'Equal0~57'
    Info: 3: + IC(0.200 ns) + CELL(1.900 ns) = 6.400 ns; Loc. = LC3_H35; Fanout = 1; COMB Node = 'Equal0~58'
    Info: 4: + IC(0.800 ns) + CELL(8.600 ns) = 15.800 ns; Loc. = PIN_30; Fanout = 0; PIN Node = 'COUT'
    Info: Total cell delay = 13.000 ns ( 82.28 % )
    Info: Total interconnect delay = 2.800 ns ( 17.72 % )
Info: th for register "lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[0]" (data pin = "EN", clock pin = "CLK") is 0.100 ns
    Info: + Longest clock path from clock "CLK" to destination register is 1.900 ns
        Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 8; CLK Node = 'CLK'
        Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC1_H34; Fanout = 7; REG Node = 'lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[0]'
        Info: Total cell delay = 0.500 ns ( 26.32 % )
        Info: Total interconnect delay = 1.400 ns ( 73.68 % )
    Info: + Micro hold delay of destination is 0.900 ns
    Info: - Shortest pin to register delay is 2.700 ns
        Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_182; Fanout = 22; PIN Node = 'EN'
        Info: 2: + IC(1.900 ns) + CELL(0.300 ns) = 2.700 ns; Loc. = LC1_H34; Fanout = 7; REG Node = 'lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[0]'
        Info: Total cell delay = 0.800 ns ( 29.63 % )
        Info: Total interconnect delay = 1.900 ns ( 70.37 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Allocated 114 megabytes of memory during processing
    Info: Processing ended: Sun Nov 11 16:19:25 2007
    Info: Elapsed time: 00:00:02