prev_cmp_cont2060.qmsg

学EDA 的时候做的

{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 0 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "168 " "Info: Allocated 168 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Sun Nov 11 16:19:15 2007 " "Info: Processing ended: Sun Nov 11 16:19:15 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:11 " "Info: Elapsed time: 00:00:11" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.1 Build 156 04/30/2007 SJ Full Version " "Info: Version 7.1 Build 156 04/30/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Nov 11 16:19:16 2007 " "Info: Processing started: Sun Nov 11 16:19:16 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off cont2060 -c cont2060 " "Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off cont2060 -c cont2060" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Info: Assembler is generating device programming files" {  } {  } 0 0 "Assembler is generating device programming files" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "135 " "Info: Allocated 135 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Sun Nov 11 16:19:22 2007 " "Info: Processing ended: Sun Nov 11 16:19:22 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Info: Elapsed time: 00:00:06" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.1 Build 156 04/30/2007 SJ Full Version " "Info: Version 7.1 Build 156 04/30/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Nov 11 16:19:23 2007 " "Info: Processing started: Sun Nov 11 16:19:23 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off cont2060 -c cont2060 " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off cont2060 -c cont2060" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0 "" 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "CLK " "Info: Assuming node \"CLK\" is an undefined clock" {  } { { "cont2060.vhd" "" { Text "D:/Quartus/cont2060/cont2060.vhd" 5 -1 0 } } { "d:/program files/quartus7.1/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/quartus7.1/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLK" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK register lpm_counter:CQI_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[2\] register lpm_counter:CQI_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\] 74.63 MHz 13.4 ns Internal " "Info: Clock \"CLK\" has Internal fmax of 74.63 MHz between source register \"lpm_counter:CQI_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[2\]\" and destination register \"lpm_counter:CQI_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\]\" (period= 13.4 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.600 ns + Longest register register " "Info: + Longest register to register delay is 11.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_counter:CQI_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[2\] 1 REG LC3_H34 22 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC3_H34; Fanout = 22; REG Node = 'lpm_counter:CQI_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[2\]'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[2] } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "d:/program files/quartus7.1/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 289 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.100 ns) + CELL(2.000 ns) 3.100 ns Equal0~59 2 COMB LC5_H35 1 " "Info: 2: + IC(1.100 ns) + CELL(2.000 ns) = 3.100 ns; Loc. = LC5_H35; Fanout = 1; COMB Node = 'Equal0~59'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "3.100 ns" { lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[2] Equal0~59 } "NODE_NAME" } } { "d:/program files/quartus7.1/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/program files/quartus7.1/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.900 ns) 5.200 ns LessThan0~407 3 COMB LC6_H35 1 " "Info: 3: + IC(0.200 ns) + CELL(1.900 ns) = 5.200 ns; Loc. = LC6_H35; Fanout = 1; COMB Node = 'LessThan0~407'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "2.100 ns" { Equal0~59 LessThan0~407 } "NODE_NAME" } } { "d:/program files/quartus7.1/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/program files/quartus7.1/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1473 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.900 ns) 7.300 ns LessThan0~408 4 COMB LC7_H35 1 " "Info: 4: + IC(0.200 ns) + CELL(1.900 ns) = 7.300 ns; Loc. = LC7_H35; Fanout = 1; COMB Node = 'LessThan0~408'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "2.100 ns" { LessThan0~407 LessThan0~408 } "NODE_NAME" } } { "d:/program files/quartus7.1/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/program files/quartus7.1/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1473 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.700 ns) 9.200 ns lpm_counter:CQI_rtl_0\|alt_counter_f10ke:wysi_counter\|counter_cell\[7\]~1 5 COMB LC1_H35 8 " "Info: 5: + IC(0.200 ns) + CELL(1.700 ns) = 9.200 ns; Loc. = LC1_H35; Fanout = 8; COMB Node = 'lpm_counter:CQI_rtl_0\|alt_counter_f10ke:wysi_counter\|counter_cell\[7\]~1'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { LessThan0~408 lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[7]~1 } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "d:/program files/quartus7.1/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 329 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.100 ns) + CELL(1.300 ns) 11.600 ns lpm_counter:CQI_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\] 6 REG LC1_H34 7 " "Info: 6: + IC(1.100 ns) + CELL(1.300 ns) = 11.600 ns; Loc. = LC1_H34; Fanout = 7; REG Node = 'lpm_counter:CQI_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\]'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "2.400 ns" { lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[7]~1 lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "d:/program files/quartus7.1/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 289 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.800 ns ( 75.86 % ) " "Info: Total cell delay = 8.800 ns ( 75.86 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.800 ns ( 24.14 % ) " "Info: Total interconnect delay = 2.800 ns ( 24.14 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "11.600 ns" { lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[2] Equal0~59 LessThan0~407 LessThan0~408 lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[7]~1 lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } } { "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "11.600 ns" { lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[2] Equal0~59 LessThan0~407 LessThan0~408 lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[7]~1 lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } { 0.000ns 1.100ns 0.200ns 0.200ns 0.200ns 1.100ns } { 0.000ns 2.000ns 1.900ns 1.900ns 1.700ns 1.300ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 1.900 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK\" to destination register is 1.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns CLK 1 CLK PIN_79 8 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 8; CLK Node = 'CLK'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "cont2060.vhd" "" { Text "D:/Quartus/cont2060/cont2060.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(0.000 ns) 1.900 ns lpm_counter:CQI_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\] 2 REG LC1_H34 7 " "Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC1_H34; Fanout = 7; REG Node = 'lpm_counter:CQI_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\]'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "1.400 ns" { CLK lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "d:/program files/quartus7.1/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 289 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.500 ns ( 26.32 % ) " "Info: Total cell delay = 0.500 ns ( 26.32 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.400 ns ( 73.68 % ) " "Info: Total interconnect delay = 1.400 ns ( 73.68 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { CLK lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } } { "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "1.900 ns" { CLK CLK~out lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 1.900 ns - Longest register " "Info: - Longest clock path from clock \"CLK\" to source register is 1.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns CLK 1 CLK PIN_79 8 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 8; CLK Node = 'CLK'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "cont2060.vhd" "" { Text "D:/Quartus/cont2060/cont2060.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(0.000 ns) 1.900 ns lpm_counter:CQI_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[2\] 2 REG LC3_H34 22 " "Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC3_H34; Fanout = 22; REG Node = 'lpm_counter:CQI_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[2\]'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "1.400 ns" { CLK lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[2] } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "d:/program files/quartus7.1/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 289 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.500 ns ( 26.32 % ) " "Info: Total cell delay = 0.500 ns ( 26.32 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.400 ns ( 73.68 % ) " "Info: Total interconnect delay = 1.400 ns ( 73.68 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { CLK lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[2] } "NODE_NAME" } } { "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "1.900 ns" { CLK CLK~out lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[2] } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { CLK lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } } { "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "1.900 ns" { CLK CLK~out lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } "" } } { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { CLK lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[2] } "NODE_NAME" } } { "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "1.900 ns" { CLK CLK~out lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[2] } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "alt_counter_f10ke.tdf" "" { Text "d:/program files/quartus7.1/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 289 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.700 ns + " "Info: + Micro setup delay of destination is 0.700 ns" {  } { { "alt_counter_f10ke.tdf" "" { Text "d:/program files/quartus7.1/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 289 2 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "11.600 ns" { lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[2] Equal0~59 LessThan0~407 LessThan0~408 lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[7]~1 lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } } { "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "11.600 ns" { lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[2] Equal0~59 LessThan0~407 LessThan0~408 lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[7]~1 lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } { 0.000ns 1.100ns 0.200ns 0.200ns 0.200ns 1.100ns } { 0.000ns 2.000ns 1.900ns 1.900ns 1.700ns 1.300ns } "" } } { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { CLK lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } } { "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "1.900 ns" { CLK CLK~out lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } "" } } { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { CLK lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[2] } "NODE_NAME" } } { "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "1.900 ns" { CLK CLK~out lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[2] } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "lpm_counter:CQI_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\] SEL CLK 11.500 ns register " "Info: tsu for register \"lpm_counter:CQI_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\]\" (data pin = \"SEL\", clock pin = \"CLK\") is 11.500 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "12.700 ns + Longest pin register " "Info: + Longest pin to register delay is 12.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns SEL 1 PIN PIN_78 4 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_78; Fanout = 4; PIN Node = 'SEL'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SEL } "NODE_NAME" } } { "cont2060.vhd" "" { Text "D:/Quartus/cont2060/cont2060.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.800 ns) + CELL(1.900 ns) 4.200 ns Equal0~59 2 COMB LC5_H35 1 " "Info: 2: + IC(1.800 ns) + CELL(1.900 ns) = 4.200 ns; Loc. = LC5_H35; Fanout = 1; COMB Node = 'Equal0~59'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "3.700 ns" { SEL Equal0~59 } "NODE_NAME" } } { "d:/program files/quartus7.1/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/program files/quartus7.1/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.900 ns) 6.300 ns LessThan0~407 3 COMB LC6_H35 1 " "Info: 3: + IC(0.200 ns) + CELL(1.900 ns) = 6.300 ns; Loc. = LC6_H35; Fanout = 1; COMB Node = 'LessThan0~407'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "2.100 ns" { Equal0~59 LessThan0~407 } "NODE_NAME" } } { "d:/program files/quartus7.1/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/program files/quartus7.1/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1473 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.900 ns) 8.400 ns LessThan0~408 4 COMB LC7_H35 1 " "Info: 4: + IC(0.200 ns) + CELL(1.900 ns) = 8.400 ns; Loc. = LC7_H35; Fanout = 1; COMB Node = 'LessThan0~408'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "2.100 ns" { LessThan0~407 LessThan0~408 } "NODE_NAME" } } { "d:/program files/quartus7.1/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/program files/quartus7.1/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1473 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.700 ns) 10.300 ns lpm_counter:CQI_rtl_0\|alt_counter_f10ke:wysi_counter\|counter_cell\[7\]~1 5 COMB LC1_H35 8 " "Info: 5: + IC(0.200 ns) + CELL(1.700 ns) = 10.300 ns; Loc. = LC1_H35; Fanout = 8; COMB Node = 'lpm_counter:CQI_rtl_0\|alt_counter_f10ke:wysi_counter\|counter_cell\[7\]~1'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { LessThan0~408 lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[7]~1 } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "d:/program files/quartus7.1/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 329 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.100 ns) + CELL(1.300 ns) 12.700 ns lpm_counter:CQI_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\] 6 REG LC1_H34 7 " "Info: 6: + IC(1.100 ns) + CELL(1.300 ns) = 12.700 ns; Loc. = LC1_H34; Fanout = 7; REG Node = 'lpm_counter:CQI_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\]'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "2.400 ns" { lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[7]~1 lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "d:/program files/quartus7.1/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 289 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "9.200 ns ( 72.44 % ) " "Info: Total cell delay = 9.200 ns ( 72.44 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.500 ns ( 27.56 % ) " "Info: Total interconnect delay = 3.500 ns ( 27.56 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "12.700 ns" { SEL Equal0~59 LessThan0~407 LessThan0~408 lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[7]~1 lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } } { "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "12.700 ns" { SEL SEL~out Equal0~59 LessThan0~407 LessThan0~408 lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[7]~1 lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } { 0.000ns 0.000ns 1.800ns 0.200ns 0.200ns 0.200ns 1.100ns } { 0.000ns 0.500ns 1.900ns 1.900ns 1.900ns 1.700ns 1.300ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.700 ns + " "Info: + Micro setup delay of destination is 0.700 ns" {  } { { "alt_counter_f10ke.tdf" "" { Text "d:/program files/quartus7.1/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 289 2 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 1.900 ns - Shortest register " "Info: - Shortest clock path from clock \"CLK\" to destination register is 1.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns CLK 1 CLK PIN_79 8 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 8; CLK Node = 'CLK'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "cont2060.vhd" "" { Text "D:/Quartus/cont2060/cont2060.vhd" 5 -1 0 } }  } 0 0 "%4!d!: +